Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

Abstract: A semiconductor device and a manufacturing method therefor, wherein, during lift-off, no cracks due to internal stresses occur in the compound semiconductor layer. A method for manufacturing a semiconductor device having a structure in which a semiconductor layer is bonded on a supporting substrate, including: a device region formation step of forming a device region including the semiconductor layer on a growth substrate through a lift-off layer; a columnar member formation step of forming a columnar member on the growth substrate; a bonding step of bonding the tops of the semiconductor layer and the columnar member to a supporting substrate; a lift-off step of separating the bottom face of the semiconductor layer from the growth substrate by removing the lift-off layer, and not separating the columnar member from the growth substrate; and a step of separating the columnar member from the supporting substrate.

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method comprises following steps. A substrate is provided. A sacrificial layer is formed on the substrate. The sacrificial layer is patterned to develop a first opening and a second opening. The first opening corresponds to an exposed portion of the substrate and the second opening corresponds to an unexposed portion of the substrate. A heat procedure is performed. A target material is formed on the exposed portion of the substrate and a rest part of the sacrificial layer. The rest part of the sacrificial layer and parts of the target material on the rest part of the sacrificial layer are removed. A predetermined patterned target material is obtained.

Abstract: An integrated optical waveguide has a first optical waveguide, a second optical waveguide, and a groove. The second optical waveguide is coupled to the first optical waveguide and has a refractive index that is different from the first optical waveguide. The groove is disposed so as to traverse an optical path of the first optical waveguide and is separated from an interface between the first optical waveguide and the second optical waveguide by a predetermined spacing. The spacing from the interface and the width of the groove are determined such that reflection at a boundary between the first optical waveguide and the second optical waveguide is weakened. A semiconductor board may be disposed at a boundary between the first optical waveguide and the second optical waveguide.

Abstract: Ordered, two-dimensional arrays of pyramidal particulates and related methods of preparation.

Abstract: A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal -semiconductor or Schottky contact is produced only after the application of a protective layer system, as a result of which it is possible to use any metals, particularly platinum, without the risk of contamination.

Abstract: An in-place bonding method in which a metal template layer under a carbon layer is removed while the carbon layer is still attached to a substrate is described for forming a carbon-on-insulator substrate. In one embodiment of the in-place bonding method, at least one layered metal/carbon (M/C) region is formed on an insulating surface layer of an initial substrate structure. The at least one layered M/C region has edges that are bordered by exposed regions of the insulating surface layer. Some edges of the at least one layered M/C region are then secured to a base substrate of the initial structure via a securing structure, while other edges are left exposed. A selective metal etchant removes the metal layer under the carbon layer using the exposed edges for access. After metal etching, the now-unsupported carbon layer bonds to the underlying insulating surface layer by attraction.

Abstract: In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in the window (106); and substantially all of the conformal layer (108) is selectively removed from the photoresist layer (102) and a bottom portion of the window to form dielectric sidewalls (110) in the window (106).

Abstract: In one implementation, a method for fabricating a tiered structure is provided, which includes forming a source and a drain on a substrate with a gate formed therebetween. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening through it to define the gate foot over the substrate. After forming the gate foot, the gate foot mask is stripped. A gate head mask is formed over the gate foot with the gate head mask exposing a top portion of the gate foot. A gate head is formed on the top portion of the gate foot using the gate head mask. A lift-off process is performed, removing the gate head mask.

Abstract: A method of forming a solder bump may involve forming a first photoresist pattern on a wafer having a pad. The first photoresist pattern may have an opening that exposes a portion of the pad. A first under bump metallurgy (UBM) layer may be formed on the pad, and a second UBM layer may be formed on the first photoresist pattern. A second photoresist pattern may be formed that exposes the first UBM layer and covers the second UBM layer. A solder bump may be formed in the opening. The second photoresist pattern and the first photoresist pattern may be removed using a stripper, thereby removing the second UBM layer by a lift-off method.

Abstract: A method for forming small, isolated device structures by photolithography, utilizing overlapping bi-layer suspension-bridge shaped photomasks. The use of a suspended mask to define a device shape beneath it eliminates the problems associated with uneven undercutting of the usual bi-layer mask which is a stencil portion formed on a lower pedestal. In particular, the use of a suspended mask eliminates undesirable dielectric buildup around the device caused by an insufficiently undercut pedestal or of premature mask lift-off caused by an overly undercut pedestal.

Abstract: Disclosed are layered groupings and methods for constructing digital circuitry, such as memory known as Permanent Inexpensive Rugged Memory (PIRM) cross point arrays which can be produced on flexible substrates by patterning and curing through the use of a transparent embossing tool.

Abstract: A method of forming a gate structure includes forming sequentially a pad layer and a first photoresist layer over a substrate. A cross-linked surface layer is formed on the surface of the first photoresist layer, followed by rounding the profile of the first photoresist layer, and removing the exposed pad layer to expose the substrate. A second photoresist layer is formed over the first photoresist layer, wherein a portion of the first photoresist layer and the exposed substrate are exposed by the second photoresist layer. Thereafter, a conductive layer is formed, wherein the conductive layer formed on the second photoresist layer is separated from the conductive layer formed on the first photoresist layer and the exposed substrate. The first and the second photoresist layers are removed while the conductive layer on the second photoresist layer is concurrently being striped. The remaining conductive layer serves as a gate structure.

Abstract: Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing only fluorine (e.g. BCl3+SF6 or so forth). By about 100% over-etching is performed for the undoped GaAs layer, etching (side etching) propagates in transverse direction of the undoped GaAs layer. With using the mask, a gate electrode of WSi is formed. Thus, a gap in a width of about 20 nm is formed by etching in the transverse direction on the drain side of the gate electrode. By this, a hetero junction FET having reduced fluctuation of characteristics of an FET, such as a threshold value, lower a rising voltage and higher breakdown characteristics.

Abstract: A gate electrode is formed in the following manner. A first resist layer having a first opening is formed on a semiconductor substrate. A second resist layer having a second opening larger than the first opening is formed on the first resist layer. A first conductor layer containing a high-melting-point metal is formed. Subsequently, a second conductor layer containing low-resistance metal is formed, and then the first conductor layer within the second opening is removed by etching. Next, the second resist layer is removed by a lift-off process, and finally the first resist layer is removed by ashing.

Abstract: A process of simultaneously forming a plurality of metal features on a substrate, in which at least one metal feature has undercut sides and at least one metal feature does not have undercut sides involves the application of a lower photoresist feature having rounded sides and an upper photoresist feature having undercut sides wherein the upper photoresist feature is positioned in offset relation to the lower photoresist feature such that one edge of the upper photoresist feature does not extend over the corresponding edge of the lower photoresist feature and the other edge of the upper photoresist feature does extend beyond the corresponding edge of the lower photoresist feature.

Abstract: A method of fabricating an insulating layer starts by forming at least one gate, having at least a conductive layer and a cap oxide layer, on a surface of a semiconductor substrate. An insulating layer thicker than a height of the gate on the semiconductor substrate is then formed to follow the topography of the gate to produce an uneven surface. A planar layer is then formed on the insulating layer to form an approximately flat surface for the semiconductor substrate. By performing a planarization process, a portion of the planar layer is removed down to the surface of the insulating layer. A first etching process is then performed to completely remove the remaining portions of the planar layer. Finally, a second etching process is performed to remove the insulating layer and the cap oxide layer atop the gate, so that the remaining insulating layer outside the gate has a protrusive surface after the second etching process.

Abstract: A method of forming a gate electrode of a compound semiconductor device includes forming a first insulating film pattern having a first aperture, forming a second insulating film pattern having a second aperture consisting of inverse V-type on the first insulating film pattern, forming a T-type gate electrode by depositing a conductivity film on the entire structure, removing a second insulating film pattern, forming a insulating spacer on a pole sidewall by etching a first insulating film pattern, and forming an ohmic electrode of the source and drain by self-aligning method using T-type gate electrode as a mask. Thereby T-type gate electrode of materials such as refractory metals can be prevented to be deteriorate because of high annealing, as well as it is stably formed, by using an insulating film. Ohmic metal and gate electrodes formed by self-aligning method can be prevented an interconnection by forming an insulating film spacer between these electrodes.

Abstract: An insulating layer is formed on a semiconductor substrate, and a first resist layer having a first resist opening portion is formed on the insulating layer. Then, the insulating layer is etched thought the opening portion to expose the substrate. After removing the first resist layer, a second resist layer having second resist opening portions are formed. One of the second resist opening portions is provided to expose the substrate, and a recess is formed in the substrate through the opening portion. Further, the insulating layer exposed from the other of the second resist opening portions is removed. Then, an electrode member for gate, source, and drain electrodes is deposited on the substrate. As a result, variations in intervals between the gate and drain electrodes and between the gate and source electrodes can be reduced.

Abstract: A method of producing a platinum-metal structure or pattern on a substrate, which includes the steps of applying a silicon oxide layer to the substrate; applying a mask to the silicon oxide layer which is formed with an opening at a location thereof at which the platinum-metal structure or pattern is to be produced; etching the silicon oxide layer so that the substrate surface area exposed by the opening formed in the mask is larger than the opening in the mask; applying a platinum-metal layer to the mask and the exposed substrate surface area; and removing the silicon oxide layer in an etching process, so that the platinum metal present on the mask is removed simultaneously therewith, and the platinum metal present on the substrate surface forms the platinum-metal pattern or structure.

Abstract: A method for fabricating a CCD image sensor includes the steps of forming a P type well in a surface of a semiconductor substrate, forming a buried CCD (BCCD) in a surface of the P type well, forming an offset gate and a reset gate on the BCCD at a predetermined interval, forming a floating diffusion region in the BCCD between the offset gate and the reset gate, forming a mask layer on an entire surface of the semiconductor substrate to form a contact hole in the floating diffusion region, forming a metal layer on the entire surface of the semiconductor substrate including the contact hole, and selectively removing the metal layer on the mask layer together with the mask layer to form a floating gate in the contact hole.

Abstract: An improved method for forming a T-gate structure in a MESFET includes dielectric lift-off steps.

Abstract: In the case where ohmic electrodes are formed on a semiconductor wafer, first of all, an insulating layer is formed on the semiconductor wafer, then a resist layer is formed on the insulating layer. Next, apertures for forming electrodes are formed in first regions of the resist layer corresponding to regions where the electrodes are formed, while dummy apertures are also formed in a second region of the resist layer in a rest part other than the first regions. Thereafter, the insulating layer is etched using the resist layer as a mask. With the resist layer remaining, electrode material is accumulated on the surface of the semiconductor wafer, and thereafter, the resist layer is removed. As a result, electrodes with desirable ohmic characteristics are stably formed.

Abstract: A method for fabricating a periodic table group III-IV metal semiconductor metal field-effect transistor device is described. The disclosed fabrication arrangement uses a single metalization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch stop layer, employs a non-alloyed ohmic contact semiconductor layer and includes a permanent non photosensitive secondary mask element. The invention includes provisions for both an all optical lithographic process and a combined optical and electron beam lithographic process. These concepts are combined to provide a field-effect transistor device of reduced fabrication cost, increased dimensional accuracy and state-of-the-art electrical performance.

Abstract: A dielectric film is formed on a semiconductor substrate, and on the dielectric film an inorganic dielectric mask film is deposited by CVD. The mask film comprises a first component which is relatively high in etch rate by isotropic plasma etching and a second component relatively low in etch rate, and the content of the first component is linearly gradient in the film thickness direction so as to become lowest at the interface between the mask film and the underlying dielectric film. For example, the mask film is a phosphosilicate glass (P.sub.2 O.sub.5 --SiO.sub.2) film. A resist film is formed on the mask film, and a window is opened in the resist film by electron beam lithography. Then a window is opened in the mask film by isotropic plasma etching, and the underlying dielectric film is also etched to form a window under the window in the mask film.

Abstract: A method for fabricating a T-shaped gate electrode includes the steps of: forming a fine gate pattern on a semiconductor substrate; forming an insulating layer on the semiconductor substrate on which the gate pattern is formed, and forming a planarizing layer on the insulating layer to planarize the surface of the semiconductor substrate; etching the planarizing layer to expose the top of the insulating layer; isotropically etching the insulating layer to expose the gate pattern using the planarizing layer as a mask; etching the exposed gate pattern to selectively expose the semiconductor substrate; depositing a gate metal to cover the exposed substrate, the insulating layer and the planarizing layer, to form a T-shaped gate; and simultaneously removing the planarizing layer, thereby forming a T-shaped gate metal with improved productivity.

Abstract: An apparatus and method of processing a planar HEMT or FET semiconductor device is disclosed. An ohmic metalization is patterned on a semiconductor surface then lifted-off. A plurality of process control monitors are isolated, preferably using a wet etch process. The process control monitors preferably include transmission line patterns (TLMs) and etch field effect transistors The TLMs measure the contact resistance during the ohmic alloy process, and the etch field effect transistors monitor the drain current during the gate-recess step. The ohmic metalizations are then alloyed, and a gate is written using an electron beam. The semiconductor device is isolated, followed by application of an overlay which connects all resulting planar device connecting pads.

Abstract: On a semiconductor substrate with an active layer, a first-stage recess groove is formed by photolithography and wet or dry etching. On the semiconductor substrate and the surface of the first-stage recess groove, a surface passivation film a crystalline material such as i-GaAs or an insulating film of, e.g., SiON, is formed. The surface passivation film on an area where an ohmic electrodes is to be formed is removed and the ohmic electrode is formed on the area by vapor deposition. Thereafter, in the first-stage recess groove, a second-stage recess groove is formed by photolithography and wet or dry etching. A gate electrode is formed on the second-stage recess groove by sputtering or the like.

Abstract: A method for forming a self-aligned semiconductor device (10) having sidewall spacers (16,17) used to align the formation of a source region (23) and a drain region (24) along with the formation of a gate structure (35). Spacers (16,17) can be formed using a sacrificial structure process where a sacrificial structure (14) is formed which determines the location of a final gate structure (35). The deposition of a dielectric layer over the sacrificial structure (14) and subsequent etch will form spacers (16,17). A second method for forming spacers (18,19), uses a photolithographic process to pattern a dielectric layer without the use of a sacrificial structure process. The spacers (16,17) are used in conjunction with implant mask regions (22) to form the source and drain regions (23,24) which are aligned to the gate structure (35).