Abstract: The present disclosure provides a method of operating a benchmark device embedded on a semiconductor wafer. The method includes applying a first voltage to a first electrode of the benchmark device, and applying a second voltage to a second electrode of the benchmark device. The method further includes electrically isolating a first component of the benchmark device from a second component of the benchmark device through a disconnecting switch connected between the first component and the second component.

Abstract: A microelectronic device comprises semiconductive pillar structures each individually comprising a digit line contact region disposed laterally between two storage node contact regions. At least one semiconductive pillar structure of the semiconductive pillar structures comprises a first end portion comprising a first storage node contact region, a second end portion comprising a second storage node contact region, and a middle portion between the first end portion and the second end portion and comprising a digit line contact region, a longitudinal axis of the first end portion oriented at an angle with respect to a longitudinal axis of the middle portion. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of the topmost select gate transistors to strings of memory cells upon application of a voltage to the gates of the topmost select gate transistors. This electric field can be provided by using a dissected plug as a contact to the channel structure of the topmost select gate transistor, where the dissected plug has one or more conductive regions contacting the channel structure and one or more non-conductive regions contacting the channel structure. The dissected plug can be part of a contact between the data line and the channel structure. Additional devices, systems, and methods are discussed.

Abstract: Methods and devices are described herein for random cut patterning. A first metal line and a second metal line are formed within a cell of a substrate and extend in a vertical direction. A third metal line and a fourth metal line are formed within the cell and are perpendicular to the first metal line and the second metal line, respectively. A first circular region at one end of the first metal line is formed using a first patterning technique and a second circular region at one end of the second metal line is formed using a second patterning technique. The first circular region is laterally extended using a second patterning technique to form the third metal line and the second circular region is laterally extended using the second patterning technique to form the fourth metal line.

Abstract: A printed circuit board includes: a base substrate including a unit region; a plurality of connection pads disposed on one surface of the base substrate; and first and second lead-in lines disposed on the one surface and respectively connected to at least a portion of the plurality of connection pads. The first and second lead-in lines have first and second cut surfaces on the one surface, respectively. The first cut surface is disposed in a position spaced apart from a side surface of the printed circuit board. The second cut surface is exposed to the side surface of the printed circuit board.

Abstract: NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

Abstract: The present disclosure provides an array substrate, a fabrication method thereof and a display device. The array substrate includes an insulating layer provided with a first via therein. The array substrate further includes a detection structure including a first conductive structure, a second conductive structure and an insulating structure therebetween. The insulating structure is a portion of the insulating layer. The second conductive structure includes a first portion and a second portion which are separated from each other, and the first portion and the second portion partially overlap with the first conductive structure in a thickness direction of the array substrate, respectively. A second via is provided in the insulating structure between overlapping portions of the first portion and the first conductive structure, and a third via is provided in the insulating structure between overlapping portions of the second portion and the first conductive structure.

Abstract: The present disclosure provides a display device and a display panel thereof, and a pixel drive circuit of a display panel. By changing a width-to-length ratio of a drive transistor in the pixel drive circuit of each sub-pixel, or changing a capacitance of a storage capacitor at the same time, such that: under the same gray scale, the width-to-length ratio of a drive transistor of each sub-pixel in same color is in direct proportion to a drive current; or at the same time a charging saturation of a storage capacitor of each sub-pixel in same color is the same, and the capacitance of the storage capacitor of each sub-pixel in same color is in direct proportion to the drive current, and the charging saturation is a difference value between an actual charging voltage and a theoretical charging voltage of the storage capacitor when a charging phase ends.

Abstract: A variable resistance memory device including a substrate; first and second transistors on the substrate; first conductive lines on the transistors, each of the first conductive lines extending in a first direction, and the first conductive lines being spaced apart from each other; first contact plugs directly contacting substrate-facing surfaces of the first conductive lines, the first contact plugs being electrically connected to the first transistors, respectively; second conductive lines on the first conductive lines, each of the second conductive lines extending in the second direction, and the second conductive lines being spaced apart from each other; second contact plugs directly contacting substrate-facing surfaces of the second conductive lines, the second contact plugs being electrically connected to the second transistors, respectively; and memory units between the conductive lines, wherein each of the second contact plugs does not overlap with any of the memory units in the third direction.

Abstract: A monitoring structure for a critical dimension of a lithography process including a dummy pattern layer and a patterned photoresist layer is provided. The dummy pattern layer includes a dummy pattern. The patterned photoresist layer includes at least one monitoring mark located above the dummy pattern. The monitoring mark includes a first portion and a second portion that intersect each other. The first portion extends in a first direction, the second portion extends in a second direction, and the first direction intersects the second direction.

Abstract: A 3D semiconductor device, the device comprising: a first level, wherein said first level comprises a first layer, said first layer comprising first transistors, and wherein said first level comprises a second layer comprising first interconnections; a second level overlaying said first level, wherein said second level comprises a third layer, said third layer comprising second transistors, and wherein said second level comprises a fourth layer comprising second interconnections; and a plurality of connection paths, wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors, wherein said second level is bonded to said first level, wherein said bonded comprises oxide to oxide bond regions and metal to metal bond regions, wherein said second level comprises at least one memory array, wherein said third layer comprises crystalline silicon, and wherein said second level comprises at least one SerDes circuit.

Abstract: The present disclosure provides methods and apparatus for designing an interconnection structure and methods for manufacturing an interconnection structure, and relates to the technical field of semiconductors. An implementation of the method may include: designing n virtual interconnection units according to a number of metal interconnection layers in a circuit area of a chip design drawing, where an ith virtual interconnection unit includes i metal interconnection layers, and where adjacent metal interconnection layers in a jth virtual interconnection unit are connected by using vias, and n?2, 1?i?n, and 2?j?n; and filling an area in the chip design drawing outside the circuit area with virtual interconnection units, where the jth virtual interconnection unit is filled, and a (j?1)th virtual interconnection unit is not filled unless there is no space in the area for the jth virtual interconnection unit.

Abstract: Devices, components and methods containing one or more light emitter devices, such as light emitting diodes (LEDs) or LED chips, are disclosed. In one aspect, a light emitter device component can include a metallic substrate with a mirrored surface, one or more light emitter devices mounted directly or indirectly on the mirrored surface, and one or more electrical components mounted on the top surface and electrically coupled to the one or more light emitter devices, wherein the one or more electrical components can be spaced from the mirrored metal substrate by one or more non-metallic layers. Components disclosed herein can result in improved thermal management and light output.

Abstract: A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact.

Abstract: An electronic device can include a substrate and an insulating structure laterally surrounded by the substrate. In an aspect, the electronic device can include a first conductive structure or an active region that is laterally surrounded by the insulating structure and the substrate. In another aspect, the electronic device can include an inductor surrounded by the insulating structure. In a further aspect, a process of forming an electronic device can include patterning a substrate to define a trench and a plurality of features, including a first feature and a second feature, within the trench; forming a first insulating layer within the trench; removing the first feature to create a first cavity; forming a second insulating layer to at least partly fill the first cavity; removing the second feature to create a second cavity; and forming a conductive or semiconductor structure within the second cavity.

Abstract: A method of manufacturing a semiconductor structure including a conductive structure, a dielectric layer, and a plurality of conductive features is disclosed. The dielectric layer is formed on the conductive structure. A plurality of through holes is formed in the dielectric layer using a metal hard mask, and at least one of the through holes exposes the conductive structure. The conductive features are formed in the through holes. At least one of the conductive features has a bottom surface and at least one sidewall. The bottom surface and the sidewall of the conductive feature intersect to form an interior angle. The interior angles of adjacent two of the conductive features have a difference less than or substantially equal to about 3 degrees.

Abstract: A stitched image sensor array on a semiconductor substrate with identical blocks that have wherein said first configuration includes enable inputs, which vary a function of the block depending on the connection to the enable inputs. The enable inputs can set an SRAM to receive different numbers of inputs.

Abstract: An apparatus for a monolithic integrated circuit die is disclosed. In this apparatus, the monolithic integrated circuit die has a plurality of modular die regions. The modular die regions respectively have a plurality of power distribution networks for independently powering each of the modular die regions. Each adjacent pair of the modular die regions is stitched together with a respective plurality of metal lines.

Abstract: A method for patterning a plurality of features in a non-rectangular pattern, such as on an integrated circuit device, includes providing a substrate including a surface with a plurality of elongated protrusions, the elongated protrusions extending in a first direction. A first layer is formed above the surface and above the plurality of elongated protrusions, and patterned with an end cutting mask. The end cutting mask includes two nearly-adjacent patterns with a sub-resolution feature positioned and configured such that when the resulting pattern on the first layer includes the two nearly adjacent patterns and a connection there between. The method further includes cutting ends of the elongated protrusions using the pattern on the first layer.

Abstract: A touch structure is disclosed. The touch structure includes an active region including a plurality of first conductive patterns, and an inactive region including a wiring. The first conductive patterns at an edge of the active region are electrically connected with each other and are electrically connected with the wiring of the inactive region to form a coil. A touch panel and a touch device including the touch structure are also disclosed.

Abstract: Methods and apparatus for spectrum-based endpointing. An endpointing method includes selecting a reference spectrum. The reference spectrum is a spectrum of white light reflected from a film of interest on a first substrate and has a thickness greater than a target thickness. The reference spectrum is empirically selected for particular spectrum-based endpoint determination logic so that the target thickness is achieved when endpoint is called by applying the particular spectrum-based endpoint logic. The method includes obtaining a current spectrum. The current spectrum is a spectrum of white light reflected from a film of interest on a second substrate when the film of interest is being subjected to a polishing step and has a current thickness that is greater than the target thickness. The method includes determining, for the second substrate, when an endpoint of the polishing step has been achieved. The determining is based on the reference and current spectra.

Abstract: An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof. Embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge.

Abstract: An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.

Abstract: The present invention relates to a surface mount package for a micro-electro-mechanical system (MEMS) microphone die and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components that simplifies manufacturing and lowers costs. The surface mount package features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the MEMS microphone die is mechanically attached, providing an interior surface for making electrical connections between the MEMS microphone die and the package, and providing an exterior surface for surface mounting the microphone package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The microphone package has a substrate with metal pads on its top and bottom surfaces, a sidewall spacer, and a lid.

Abstract: To form an interconnect conductor structure, a stack of pads, coupled to respective active layers of a circuit, is formed. Rows of interlayer conductors are formed to extend in an X direction in contact with landing areas on corresponding pads in the stack. Adjacent rows are separated from one another in a Y direction generally perpendicular to the X direction. The interlayer conductors in a row have a first pitch in the X direction. The interlayer conductors in adjacent rows are offset in the X direction by an amount less than the first pitch. Interconnect conductors are formed over and in contact with interlayer conductors. The interconnect conductors extend in the Y direction and have a second pitch less than the first pitch.

Abstract: A semiconductor device and a method for manufacturing a local interconnect structure for a semiconductor device is provided. The method includes forming removable sacrificial sidewall spacers between sidewall spacers and outer sidewall spacers on two sides of a gate on a semiconductor substrate, and forming contact through-holes at source/drain regions in the local interconnect structure between the sidewall spacer and the outer sidewall spacer on the same side of the gate immediately after removing the sacrificial sidewall spacers. Once the source/drain through-holes are filled with a conductive material to form contact vias, the height of the contact vias shall be same as the height of the gate. The contact through-holes, which establish the electrical connection between a subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, shall be made in the same depth.

Abstract: A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.

Abstract: An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.

Abstract: A fully-passive, dynamically configurable directed cooling system for a microelectronic device is disclosed. In general, movable pins are suspended within a cooling plenum between an active layer and a second layer of the microelectronic device. In one embodiment, the second layer is another active layer of the microelectronic device. The movable pins are formed of a material that has a surface tension that decreases as temperature increases such that, in response to a temperature gradient on the surface of the active layer, the movable pins move by capillary flow in the directions of decreasing temperature. By moving in the direction of decreasing temperature, the movable pins move away from hot spots on the surface of the active layer, thereby opening a pathway for preferential flow of a coolant through the cooling plenum at a higher flow rate towards the hot spots.

Abstract: A method for manufacturing a printed wiring board includes forming a removable layer on a support substrate, forming an interlayer resin insulation layer on the removable layer, forming a penetrating hole in the interlayer resin insulation layer, forming a first conductive layer on the interlayer resin insulation layer and on a side wall of the penetrating hole, forming a conductive circuit on the interlayer resin insulation layer, forming a via conductor in the penetrating hole, removing the support substrate from the interlayer resin insulation layer by using the removable layer, forming a protruding portion of the via conductor protruding from a surface of the interlayer resin insulation layer, and forming a surface-treatment coating on a surface of the protruding portion of the via conductor.

Abstract: A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region and the second via is in communication with the second contact region. A buried void provides a communication path between the first and second vias. The vias and buried void are at least partially filled with a dielectric filler. The partially filled buried void blocks the communication path between the first and second vias created by the buried void. The dielectric filler in the vias is removed, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias and contact plugs are formed in the vias.

Abstract: In one embodiment of the invention, there is provided a method for manufacturing a magnetic memory device, comprising: depositing a carbon layer comprising amorphous carbon on a substrate; annealing the carbon layer to activate dopants contained therein; and selectively etching portions of the carbon layer to forms lines of spaced apart carbon conductors.

Abstract: A method for defining parallel lines extending along a first direction in a same level of an integrated circuit, among which at least first and second lines separated by an even number of lines are interconnected, a space having a width at least equal to the minimum space between two lines separated by one line being left free, in a second direction perpendicular to the first direction, on either side of a minimum rectangle containing the first and the second lines.

Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

Abstract: A method for producing at least one semiconductor component group, in particular a SiC semiconductor component group, includes the step of producing a number of semiconductor components on a substrate, particularly on a wafer. The individual semiconductor components are tested for detecting operative semiconductor components. At least one semiconductor component group is assembled, which is formed of a number of operative semiconductor components and which forms a coherent flat structure. The operative semiconductor components of the semiconductor component group are electrically connecting in parallel.

Abstract: A method for manufacturing of a device including a first substrate including a plurality of sets of nanostructures arranged on the first substrate, wherein each of the sets of nanostructures is individually electrically addressable, the method including the steps of: providing a substrate having a first face, the substrate having an insulating layer including an insulating material arranged on the first face of the substrate forming an interface between the insulating layer and the substrate; providing a plurality of stacks on the first substrate, wherein each stack includes a first conductive layer and a second conductive layer; heating the first substrate having the plurality of stacks arranged thereon in a reducing atmosphere to enable formation of nanostructures on the second conductive material; heating the first substrate having the plurality of stacks arranged thereon in an atmosphere such that nanostructures are formed on the second layer.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.

Abstract: An approach for providing layout designs with via routing structures is disclosed. Embodiments include: providing a gate structure and a diffusion contact on a substrate; providing a gate contact on the gate structure; providing a metal routing structure that does not overlie a portion of the gate contact, the diffusion contact, or a combination thereof; and providing a via routing structure over the portion and under a part of the metal routing structure to couple the gate contact, the diffusion contact, or a combination thereof to the metal routing structure.

Abstract: A method for fabricating a device, the method including: providing a first layer including first transistors, where the first transistors include a mono-crystalline semiconductor; overlaying a second semiconductor layer over the first layer; fabricating a plurality of memory cell control lines where the control lines include a portion of the second layer; where the second layer includes second transistors, where the second transistors include a mono-crystalline semiconductor, and where the second transistors are configured to be memory cells.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.

Abstract: A semiconductor apparatus and a design method for the semiconductor apparatus allow debugging or repairs by using a spare cell. The semiconductor apparatus includes a plurality of metal layers. At least one repair block performs a predetermined function. A spare block is capable of substituting for a function of the repair block. And at least one of the plurality of metal layers is predetermined to be a repair layer for error revision. At least one pin of the repair block is connected to the repair layer through a first pin extension, and at least one pin of the spare block is capable of extending to the repair layer. When the repair block is to be repaired, the pin extension of the repair layer and the repair block is disconnected, and at least one pin of the spare block is connected to the repair layer through a second pin extension.

Abstract: Integrated circuits that include SRAM cells having additional read stacks and methods for their fabrication are provided. In accordance with one embodiment a method for fabricating such an integrated circuit includes forming a plurality of SRAM cells in and on a semiconductor substrate, each of the plurality of SRAM cells including a read pull down transistor and a read pass gate transistor. First conductivity-determining impurity ions are implanted to establish a first threshold voltage in each of the read pull down transistors; and second conductivity-determining impurity ions are implanted to establish a second threshold voltage different than the first threshold voltage in each of the read pass gate transistors.

Abstract: An integrated circuit die includes a substrate having an upper surface, at least one active device formed in a first area of the upper surface of the substrate, and a plurality of layers formed on the upper surface of the substrate above the at least one active device. A first stacked heat conducting structure is provided, spanning from a point proximate the first area of the upper surface of the substrate through the plurality of layers. A lateral heat conducting structure is formed above the uppermost layer of the plurality of layers and in thermal contact with the first stacked heat conducting structure. The invention advantageously facilitates the dissipation of heat from the integrated circuit die, particularly from high-power sources or other localized hot spots.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.

Abstract: An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's sprinted circuit board.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.

Abstract: The present invention relates to a surface mount package for a silicon condenser microphone and methods for manufacturing the surface mount package. The surface mount package uses a limited number of components which simplifies manufacturing and lowers costs, and features a substrate that performs functions for which multiple components were traditionally required, including providing an interior surface on which the silicon condenser die is mechanically attached, providing an interior surface for making electrical connections between the silicon condenser die and the package, and providing an exterior surface for surface mounting the package to a device's printed circuit board and for making electrical connections between package and the device's printed circuit board.