Abstract: The present invention provides a bonding pad for an optical semiconductor device, including: a first supplementary adhesive layer made of Si3N4, being formed on a semiconductor substrate; a bonding pad layer made of benzocyclobutene, being formed on the first supplementary adhesive layer; a second supplementary adhesive layer made of Si3N4, being formed on the bonding pad layer; and a metallic electrode layer formed on the second supplementary adhesive layer.

Abstract: For filling an interconnect opening within an insulating layer on a semiconductor wafer, an adhesion skin layer is deposited conformally onto an underlying material comprised of one of a barrier material or a dielectric material at sidewalls and a bottom wall of the interconnect opening. The adhesion skin layer includes a metal alloy doping element. A conformal seed layer is deposited onto the adhesion skin layer using a conformal deposition process, such as an ECD (electrochemical deposition) or a CVD (chemical-vapor-deposition) process. The adhesion skin layer promotes adhesion of the conformal seed layer to the underlying material at the sidewalls and the bottom wall of the interconnect opening. The interconnect opening is filled with a conductive material grown from the conformal seed layer. In this manner, the adhesion skin layer promotes adhesion of the conformal seed layer to the underlying material to minimize electromigration failure of the interconnect.

Abstract: A diffusion barrier layer having nitrogen at least on the top surface thereof is formed before activating the diffusion barrier layer used as an underlying layer during an electroless plating process, thereby enabling catalytic metal nuclei to be densely and uniformly formed on the diffusion barrier layer during the activation of the diffusion barrier layer. In a method for forming metal interconnections, a diffusion barrier layer having a nitrogen-containing layer exposed on the top surface thereof is formed on a semiconductor substrate. Then, the surface of the diffusion barrier layer is activated, and an electroless plated layer is formed on the activated diffusion barrier layer.

Abstract: Disclosed is a method for forming selective protection layers on copper interconnects in a damascene process. A copper layer is deposited overlying a dielectric layer and filling interconnect trenches which are previously formed in the dielectric layer. The excess copper layer is polished by a chemical mechanical polishing process with a slurry comprising an aluminum organic substance. The aluminum organic substance reacts with copper via annealing to selectively form aluminum-copper alloys on the copper interconnects. The aluminum-copper alloys are then oxidized to form aluminum oxide protection layers capping the copper interconnects.

Abstract: Corrosion and degradation of tantalum-based adhesion/barrier layers used in multi-level semiconductor devices employing copper-based interconnect metallization systems are avoided or minimized. In embodiments of the present invention, deleterious fluorine-containing contaminants formed on underlying copper-based metal features as a result of etching through-holes in silicon-based interlevel dielectric material layers for via holes is prevented by the use of fluorine-free etching processes. Other embodiments of the present invention include performing a two-step etching sequence comprising a first, fluorine-containing process and a second, fluorine-free process.

Abstract: A semiconductor device has an interlayer insulation film formed on a first metal wiring and formed of an organic compound having a lower dielectric constant than that of SiO2, a second metal wiring formed on the interlayer insulation film, and an interlayer adhesion layer to improve adherence between the interlayer insulation film and the second metal wiring. The semiconductor device is provided with a stress buffer layer of which the elastic modulus is higher than that of the interlayer insulation film and is lower than that of the interlayer adhesion layer between the interlayer insulation film and the interlayer adhesion layer.

Abstract: The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a SixGe1−x (0<x<1) layer. Thus, only moderate doping is required, which in turn protects the device from short channel effect and leakage. The low resistance, tunable contact is suitable for CMOS devices.

Abstract: A process for making a semiconductor device, comprises a first step of embedding a conductive material in a via-hole formed in a first interlayer dielectric film to form a conductive plug connected to a lower layer wiring line, a second step of forming an upper layer wiring groove in a second interlayer dielectric film formed on the conductive plug such that a target area of the conductive plug is exposed in the upper layer wiring groove, a third step of forming a first barrier layer on an entire surface of the second interlayer dielectric film including the upper layer wiring groove, and a fourth step of embedding a wiring material in the upper layer wiring groove to form an upper layer wiring line. The process further comprises a fifth step of selectively removing the first barrier layer formed only on the conductive plug prior to the fourth step.

Abstract: A process is described for depositing a copper film on a substrate surface by chemical vapor deposition of a copper precursor. The process includes treating a diffusion barrier layer surface and/or a deposited film with an adhesion-promoting agent and annealing the copper film to the substrate. Suitable adhesion-promoting agents include, e.g., organic halides, such as methylene chloride, diatomic chlorine, diatomic bromine, diatomic iodine, HCl, HBr and Hl. Processes of the invention provide copper-based films, wherein a texture of the copper-based films is predominantly (111). Such films provide substrates having enhanced adhesion between the diffusion barrier layer underlying the (111) film and the copper overlying the (111) film.

Abstract: Disclosed is a copper film selective formation method capable of reducing the material cost by selectively depositing copper in a necessary region of an undercoat film made of an arbitrary material such as a metal or an insulating material. This copper film selective formation method includes the steps of forming a thin film of a silane coupling agent or a surfactant on an undercoat film on a substrate, making a prospective copper film region of the thin film hydrophilic, and selectively forming a copper film in the hydrophilic prospective copper film region of the undercoat film by CVD of copper.

Abstract: For filling an interconnect opening of an integrated circuit formed on a semiconductor substrate, an underlying material is formed at any exposed walls of the interconnect opening. A sacrificial layer of protective material is formed on the underlying material at the walls of the interconnect opening. The underlying material and the sacrificial layer of protective material are formed without a vacuum break. The protective material of the sacrificial layer is soluble in an acidic catalytic solution used for depositing a catalytic seed layer. The semiconductor substrate having the interconnect opening is placed within an acidic catalytic solution for depositing a catalytic seed layer. The sacrificial layer of protective material is dissolved away from the underlying material by the acidic catalytic solution such that the underlying material is exposed to the acidic catalytic solution.

Abstract: According to the present invention, a semiconductor device is fabricated by: forming an insulation layer on a substrate; forming a groove in the surface of the insulation layer; forming a diffusion protection layer on the surface of the insulation layer including inside of the groove; forming a reaction layer on the diffusion protection layer; forming an oxide layer on the surface of the reaction layer; forming a layer of a wiring material on the oxide layer to embed the groove; forming a layer of a mixture of the reaction layer, the layer of the wiring material and the oxide layer by annealing; and removing the diffusion protection layer, the mixture layer and the layer of the wiring material from the surface of the insulation layer except for the diffusion protection layer, the mixture layer and the layer of the wiring material in the groove.

Abstract: A method for creating a highly reflective surface on an electroplated conduction layer. A barrier layer is deposited on a substrate using a self ionized plasma deposition process. The barrier layer has a thickness of no more than about one hundred angstroms. An adhesion layer is deposited on the barrier layer, using a self ionized plasma deposition process. A seed layer is deposited on the adhesion layer, also using a self ionized plasma deposition process, at a bias of no less than about one hundred and fifty watts. The combination of the barrier layer, adhesion layer, and seed layer is at times referred to herein as the barrier seed layer. The conduction layer is electroplated on the seed layer, thereby forming the highly reflective surface on the conduction layer, where the highly reflective surface has a reflectance of greater than about seventy percent.

Abstract: Methods and apparatus for forming conductive interconnect layers useful in articles such as semiconductor chips, memory devices, semiconductor dies, circuit modules, and electronic systems. The number of necessary processing steps to form conductive interconnects are reduced by removing the need to employ a seed layer interposed between the barrier layer and the conductive interconnect layer. This is accomplished in part through the electrochemical reduction of oxides on a dual-purpose layer. The present invention can be advantageously utilized to deposit copper interconnects onto tungsten.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is formed over the semiconductor substrate has an opening formed therein. A barrier layer of titanium, tantalum, tungsten, or a nitride of the aforegoing lines the opening, and a copper or copper alloy conductor core fills the channel opening over the barrier layer. After planarization of the conductor core and the barrier layer, an ammonia, nitrogen hydride, or hydrogen plasma treatment is performed below 300° C. and above 3000 watts source power to reduce the residual oxide on the conductor core material. A silicon nitride capping layer is deposited by high density plasma (HDP) deposition with the source power between 2250 and 2750 watts and the bias power between 1800 and 2200 watts to suppress the formation of hillocks.

Abstract: A semiconductor device including a semiconductor substrate, and a plurality of first interconnects formed over the semiconductor substrate. A first insulating layer covers the plurality of first interconnects, and a second insulating layer is formed between the plurality of first interconnects. The second insulating layer has substantially the same height as the plurality of first interconnects. An intermediate insulating layer is formed over the second insulating layer.

Abstract: A method for manufacturing integrated circuits; particularly, a method for fabricating a copper interconnect system and a copper interconnect system, having a layer of CrO, fabricated by the method.

Abstract: A method for improving adhesion of copper films to transition metal based barrier layers. Tantalum or other transition metal based barrier layers are deposited by chemical vapor deposition techniques using transition metal halide precursor materials which generate halogen atom impurities in the barrier layer. The barrier layer is treated with a plasma generated from a nitrogen-containing gas, such as ammonia. Halogen impurity levels are thereby decreased at the surface of the barrier layer. On this surface is subsequently applied a copper film by physical vapor deposition. The copper film exhibits improved adherence to the barrier layer.

Abstract: A method of forming a semiconductor device having selectively fabricated copper interconnect structure that is encapsulated within selectively formed metallic barriers. An exemplary encapsulated copper interconnect structure includes a first low dielectric constant layer (low K1) formed over a substantially completed semiconductor device on which a first sidewall metallic barrier, consisting of metallic material is formed to line the wall structure of a via. The metallic liner encapsulates a first, substantially thin (≦0.25 &mgr;m) copper interconnect structure. A second selectively formed thicker (>>0.25 &mgr;m) copper interconnect trench structure is formed overlying and integral with the first copper interconnect structure. A second metallic barrier is deposited over the second selectively formed copper interconnect structure and is formed integral with the first sidewall metallic barrier.

Abstract: A metal wiring layer of a semiconductor device in which a nucleation liner is formed prior to forming an aluminum liner. A barrier metal layer is formed on a semiconductor substrate. A nucleation liner for growing an aluminum layer is formed on the barrier metal layer in a vacuum state. An aluminum liner is formed by growing an aluminum layer on the nucleation liner using chemical vapor deposition in a vacuum state in situ with the step of forming the nucleation liner. A metal layer is formed on the aluminum liner using physical vapor deposition. The semiconductor substrate is heat-treated and reflowed.

Abstract: A lower aluminum line is exposed to a via-hole formed in an inter-level insulating layer, and an outgassing is carried out before deposition for an upper aluminum line connected through the via-hole to the lower aluminum line, wherein the outgassing is carried out at a substrate temperature equal to or less than the maximum substrate temperature in the formation of the inter-level insulating layer so that a hillock and a whisker due to the thermal stress do not take place in the lower aluminum line.

Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber.

Abstract: The present invention pertains to systems and methods for reducing the agglomeration of copper deposited by physical vapor deposition. More specifically, the invention pertains to systems and methods for depositing copper seed layers on a semiconductor wafer. The invention involves the use of an anti-agglomeration agent, so that the copper deposition is completed in an even, continuous and conformal manner.

Abstract: After phosphorus is ion implanted into a portion of a polysilicon film, first RTA is performed. After boron is ion implanted into another portion of the polysilicon film, the polysilicon film is patterned to form a gate electrode and a resistor film. A TEOS film is deposited and patterned to form a silicidation mask having an opening corresponding to a silicidation region. Thereafter, annealing for activating boron is performed in an atmosphere containing oxygen, thereby forming oxide films on a gate electrode and on heavily doped source/drain regions in the silicidation region. The oxide films suppress out-diffusion of the impurities and inhibit the impurity ions from penetrating the gate electrode 8 during ion implantation for promoting silicidation, which is performed subsequently.

Abstract: The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved by treating the exposed planarized surface of the Cu or Cu alloy with a plasma containing NH3 and N2 under mild steady state conditions, thereby avoiding sensitizing the Cu or Cu alloy surface before capping layer deposition with an attendant improvement in electromigration resistance and wafer-to-wafer uniformity. Embodiments include treating the Cu or Cu alloy surface with a plasma at a relatively high N2 flow rate of about 8,000 to about 9,200 sccm and a relatively low NH3 flow rate of about 210 to about 310 sccm.

Abstract: A method of manufacturing integrated circuits using a thin metal oxide film as a seed layer for building multilevel interconnects structures in integrated circuits. Thin layer metal oxide films are deposited on a wafer, and standard optical lithography is used to expose the metal oxide film in a pattern corresponding to a metal line pattern. The metal oxide film is converted to a layer of metal, and a metal film may then be deposited on the converted oxide film by either selective CVD or electroless plating. Via holes are then fabricated in a similar process using via hole lithography. The process is continued until the desired multilevel structure is fabricated.

Abstract: In a semiconductor device, a contact layer is provided between a silicon-containing insulating film SiO2, etc. or a metal wiring layer, and a fluorine-containing carbon CF film to increase their adhesion. For this purpose, SiC film deposition gases, such as SiH4 gas and C2H4 gas, are excited into plasma to stack a SiC film [200] as the contact layer on the top surface of a SiO2 film [110]. After that, switching of deposition gases is conducted for about 1 second by introducing SiH4 gas, C2H4 gas, C4F8 gas and C2H4 gas. Subsequently, CF film deposition gases, such as C4F8 gas and C2H4 gas, for example, are excited into plasma to deposit[e] a CF film [120] on the SiC film [200].

Abstract: A method of manufacturing multilevel interconnects. A single or dual damascene interconnect structure is formed in a first dielectric layer. A cap layer or middle etch stop layer is formed over the interconnect structure and the first dielectric layer. The cap layer or the middle etch stop layer is treated with nitrogen plasma to convert a hydrophobic surface into a hydrophilic surface. An adhesion promoter layer is formed over the cap layer or middle etch stop layer. A low-k dielectric layer is formed over the adhesion promoter layer. A single or dual damascene structure is formed in the low-k dielectric layer, thereby forming a multilevel interconnect.

Abstract: The electromigration resistance of nitride capped Cu lines is significantly improved by controlling the nitride deposition conditions to reduce the compressive stress of the deposited nitride layer, thereby reducing diffusion along the Cu-nitride interface. Embodiments include depositing a silicon nitride capping layer on inlaid Cu at a reduced RF power, e.g., about 400 to about 500 watts and an increased spacing, e.g., about 680 to about 720 mils, to reduce the compressive stress of the deposited silicon nitride layer to below about 2×107 Pascals. Embodiments also include sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a soft plasma containing NH3 diluted with N2, ramping up the introduction of SiH4 and then initiating plasma enhanced chemical vapor deposition of a silicon nitride capping layer, while maintaining substantially the same pressure and N2 flow rate during plasma treatment, SiH4 ramp up and silicon nitride deposition.

Abstract: The present disclosure pertains to particular Ti/TiN/TiNx barrier/wetting layer structures which enable the warm aluminum filling of high aspect vias while providing an aluminum fill exhibiting a high degree of aluminum <111> crystal orientation. It has been discovered that an improved Ti/TiN/TiNx barrier layer deposited using IMP techniques can be obtained by increasing the thickness of the first layer of Ti to range from greater than about 100 Å to about 500 Å (the feature geometry controls the upper thickness limit); by decreasing the thickness of the TiN second layer to range from greater than about 100 Å to less than about 800 Å (preferably less than about 600 Å); and, by controlling the application of the TiNx third layer to provide a Ti content ranging from about 50 atomic percent titanium (stoichiometric) to about 100 atomic percent titanium.

Abstract: A novel and improved method of fabricating an integrated circuit, in which special copper films are formed by a combination of physical vapor deposition (PVD), chemical mechanical polish (CMP) and electrochemical copper deposition (ECD) techniques. The methods of the present invention make efficient use of several process steps resulting in less processing time, lower costs and higher device reliability. By these techniques, high aspect ratio trenches can be filled with copper without the problem of dishing. A special, selective electrochemical deposition (ECD) of copper metal is utilized taking place only on the seed layer in the trench. This auto-plating or “plate-up” occurs only in the trench and provides good sealing around the trench perimeter and fine copper metal coverage of the trench for subsequent robust interconnects.

Abstract: The invention provides a technology for reducing the direct contact resistance and for reducing the junction leak while maintaining the punch through margin. A semiconductor integrated circuit device is provided which comprises: a substrate; a transistor formed on the substrate, which comprises a source, a drain and a gate which controls a current flowing from said source to said drain; and a contact plug being electrically connected to at least one of the source and drain and made of a conductive material including a dopant. The contact plug is formed of at least a first layer and a second layer. The first layer contacts with one of the source and drain and is made of said material including the dopant of a first concentration. The second layer is formed of a layer of said material including the dopant of a second concentration, which is lower than the second concentration.

Abstract: Interconnects in porous dielectric materials are coated with a SiC-containing material to inhibit moisture penetration and retention within the dielectric material. Specifically, SiC coatings doped with boron such as SiC(BN) show particularly good results as barrier layers for dielectric interconnects.

Abstract: A metal contact structure of a semiconductor device and a method for forming the same are provided. The diameter of the upper portion of a contact hole that exposes a region of a lower conductive layer is formed to be larger than the diameter of the lower portion of the contact hole. The metal contact structure is formed without a void or a key hole. This is accomplished by forming at least two metal layers to fill the contact hole by performing a first deposition, an etch back, and a second deposition. The metal layer which fills the contact hole is etched back using a barrier metal layer formed on the entire surface of the contact hole as an etching stop layer. Thus, a void or key hole is not generated by making the upper portion of the contact hole to be wider than the lower portion of the contact hole and by depositing the metal which fills the contact hole through the processes of firstly depositing the metal, etching back the metal, and secondly depositing the metal.

Abstract: A method is disclosed to improve copper barrier and adhesion properties of copper interconnections in integrated circuits. It is shown that combining ion metal plasma (IMP) deposition along with in-situ chemical vapor deposition (CVD) of barrier and adhesion materials provides the desired adhesion of and barrier to diffusion of copper in damascene structures. IMP deposition is performed with tantalum or tantalum nitride while CVD deposition is performed with a binary or a ternary compound from a group consisting of titanium nitride, tungsten nitride, tungsten silicon nitride, tantalum silicon nitride, titanium silicon nitride. IMP deposition provides good adhesion of copper to insulator materials, while CVD deposition provides good sidewall coverage in a copper filled trench and a copper seed layer provides good adhesion of bulk copper to adhesion/barrier layer. The IMP/CVD deposited adhesion/barrier layer is thin, thus providing low via resistance.

Abstract: A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A seed layer is deposited over the barrier layer and a conductor core is deposited over the seed layer, filling the opening of in the channel dielectric layer. The seed and barrier layers are then removed above the dielectric layer. A conductive layer is then deposited, filling any voids or depressions in the conductor core, and is subsequently removed above the dielectric layer resulting in a conductive channel of uniform thickness.

Abstract: The invention provides a method for filling a structure on a substrate comprising: depositing a barrier layer on one or more surfaces of the structure, depositing a seed layer over the barrier layer, removing a portion of the seed layer, and electrochemically depositing a metal to fill the structure. Preferably, a portion or all of the seed layer formed on the sidewall portion of the structure is removed using a electrochemical de-plating process prior to the electroplating process.

Abstract: We have discovered particular wetting layer or wetting/barrier layer structures which enable depositing of overlying aluminum interconnect layers having <111> texturing sufficient to provide a Rocking Curve FWHM angle &thgr; of about 1° or less. The aluminum interconnect layer exhibiting a Rocking Curve FWHM angle &thgr; of about 1° or less exhibits excellent electromigration properties. In addition when the aluminum layer is subsequently pattern etched, the sidewalls of the etched aluminum pattern exhibit a surprising reduction in pitting compared with pattern etched aluminum layers exhibiting higher Rocking Curve FWHM angles.

Abstract: An improved method of preventing copper poisoning in the fabrication of metal interconnects on a semiconductor substrate comprises sequential formation of a copper layer, a first stop layer, a first inter-metal dielectric layer, a second stop layer, and a second inter-metal dielectric layer over the substrate. The second inter-metal dielectric layer and the second stop layer are defined to form an opening. A conformal first glue/barrier layer is formed over the substrate. The first glue/barrier layer and the first inter-metal dielectric layer are patterned to form a via hole below the opening until the first stop layer is exposed. Spacers are formed on sidewalls of the opening and the via hole below the opening. The first stop layer at bottom of the via hole is removed to expose the copper layer.

Abstract: A semiconductor device has a dielectric film made of a fluorine-added carbon film formed on a substrate, a metallic layer formed on the fluorine-added carbon film and an adhesive layer formed between the dielectric film and the metallic layer. The adhesive layer is made of a compound layer having carbon and the metal (or metal the same as the metal included in the metallic layer), to protect the metallic layer from being peeled-off from the fluorine-added carbon film.

Abstract: A method of forming a contact structure in a semiconductor device is provided. In this method, a semiconductor layer, an ohmic metal layer, and a barrier metal layer are formed on the surface of a semiconductor substrate on which a metal contact hole has been formed. A compound material layer having a uniform thickness is formed on the bottom, sidewalls and lower corners of the contact hole by thermally reacting the semiconductor layer with the ohmic metal layer. Accordingly, when the contact hole exposes an impurity layer and portions of an isolation layer adjacent to the impurity layer, the junction leakage current characteristics of the impurity layer and a contact resistance are improved.

Abstract: A method that enhances performance of copper damascene by embedding TiN layer is proposed. The spirit of the invention is that a CVD TiN layer is inserted between the copper seed layer and the dielectric layer to improve the quality of copper layer. Herein, the TiN layer can either be located between the copper seed layer and the barrier layer or be located between the barrier layer and the dielectric layer. Because the barrier layer and the copper seed layer are formed by physical vapor deposition in current mass product, a higher side wall converge of the CVD TiN layer can be obtained owing to the higher conformity nature of CVD technology. Therefore, a better sidewall CVD TiN converge serves as an extra protection layer for copper self diffusion. Furthermore, it also acts as a copper seed layer to remedy side wall void problems due to copper seed layer discontinuity. Thus, not only the quality of copper layer is improved but also the performance of copper damascene process is enhanced.

Abstract: A semiconductor device includes first and second conductive layers which are electrically connected to each other through a contact plug. A first insulating film is formed on the first conductive layer and has a first opening which reaches the surface of the first conductive layer. A second insulating film is formed on the first insulating film and has a second opening at the same position as the first opening. The contact plug is filled in the first and second openings and has the surface which is substantially flush with the surface of the second insulating film and also contains a metal having a high melting point. The second conductive layer is formed on the second insulating film and on the contact plug.

Abstract: A semiconductor interconnect structure having a substrate with an interconnect structure patterned thereon, a barrier layer, a pre-seed layer, a seed layer, a bulk interconnect layer, and a sealing layer. A process for creating such structures is described. The barrier layer is formed using atomic layer deposition techniques. Subsequently, a pre-seed layer is formed to create a heteroepitaxial interface between the barrier and pre-seed layers. This is accomplished using atomic layer epitaxy techniques to form the pre-seed layer. Thereafter, a seed layer is formed by standard deposition techniques to create a homoepitaxial interface between the seed and pre-seed layers. Upon this layered structure further bulk deposition of conducting materials is done. Excess material is removed from the bulk layer and a sealing layer is formed on top to complete the interconnect structure.

Abstract: The present invention discloses an integrated method for I/O redistribution and in-situ passive components fabrication such that passive components such as resistors and capacitors can be formed simultaneously during the I/O redistribution process. Only minor modifications in the I/O redistribution process need to be made for accomplishing the present invention method. In the method, an adhesion layer formed of a high resistance material such as TiW, TiN, NiCr,or NiV can be used to connect between connective traces and to function as passive resistors. Passive capacitors can be formed by the additional deposition steps of a dielectric layer and a conductive metal layer on top of an existing connective trace formed on a bonding pad.

Abstract: A new method of forming a damascene interconnect in the manufacture of an integrated circuit device has been achieved. The damascene interconnect may be a single damascene or a dual damascene. Copper conductors are provided overlying a semiconductor substrate. A first passivation layer is provided overlying the copper conductors. A low dielectric constant layer is deposited overlying the first passivation layer. An optional capping layer is deposited overlying the low dielectric constant layer. A photoresist layer is deposited overlying the capping layer. The capping layer and the low dielectric constant layer are etched through to form via openings. The photoresist layer is simultaneously stripped away while forming a sidewall passivation layer on the sidewalls of the via openings using a sulfur-containing gas. Sidewall bowing and via poisoning are thereby prevented. The first passivation layer is etched through to expose the underlying copper conductors.

Abstract: The present invention is a new and improved method for fabricating aluminum metal pad structures wherein a thin adhesion layer of aluminum is placed in between the underlying copper metal and the top tantalum nitride pad barrier layer providing improved adhesion to the pad metal stack structure. In summary, present invention teaches a method comprising of forming a copper underlayer, forming the key aluminum adhesion layer, forming the tantalum nitride barrier layer, and finally forming the aluminum pad. The problem of adhesion of metal pad to underlying layers, dielectrics, and polymers in is not unique to the manufacture of multi-layer electronic circuit chips and modules, but is encountered in other technologies involved in other types of electronic elements, e.g., the formation of capacitors or even other technologies entirely unrelated to the fabrication of electrical devices.

Abstract: A method for autoaligning lines of a conductive material in circuits integrated on a semiconductor substrate is presented. The method includes forming several regions projecting from the substrate surface and aligned to one another, and forming a fill layer in the gaps between the projecting regions. The fill layer is planarized to expose the regions, and a portion of the regions is removed to form holes at the locations of the regions. Next an insulating layer is formed in the holes. The insulating layer is selectively removed to form spacers along the edges of said holes and at least one conductive layer is deposited over the exposed surface. Later, a step of photolithograpy with a mask is performed and the conductive layer is etched to define lines and collimate them to the underlying regions.

Abstract: This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the use an alternate etch stop in dual damascene interconnects that improves adhesion between low dielectric constant organic materials. In addition, the etch stop material is a silicon containing material and is transformed into a low dielectric constant material (k=3.5 to 5), which becomes silicon-rich silicon oxide after UV radiation and silylation, oxygen plasma.

Abstract: A method for manufacturing a multi-level interconnection structure in a semiconductor device includes the steps of consecutively forming an anti-diffusion film and an interlevel dielectric film on a first level Cu layer, forming first through third hard mask films on the interlevel dielectric film, etching the interlevel dielectric film by using the first hard mask to form first through-holes, etching the first and second hard mask films and a top portion of the interlevel dielectric film by using the third hard mask film to form trenches, and etching the anti-diffusion film to form through-holes. The first hard mask film protects the interlevel dielectric film during removal of the second and third hard mask films.