Using Running Length Substrate Patents (Class 438/62)
-
Patent number: 7736935Abstract: The present invention provides, in part, methods producing multilayer semiconductor structures having one or more at least partially relaxed strained layers, where the strained layer is at least partially relaxed by annealing. In particular, the invention forms diffusion barriers that prevent diffusion of contaminants during annealing. The invention also includes embodiments where the at least partially relaxed strained layer is patterned into islands by etching trenches and the like. The invention also provides semiconductor structures resulting from these methods, and further, provides such structures where the semiconductor materials are suitable for application to LED devices, laser devices, photovoltaic devices, and other optoelectronic devices.Type: GrantFiled: December 22, 2008Date of Patent: June 15, 2010Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Bruce Faure, Pascal Guenard
-
Patent number: 7732243Abstract: This invention comprises manufacture of photovoltaic cells by deposition of thin film photovoltaic junctions on metal foil substrates. The photovoltaic junctions may be heat treated if appropriate following deposition in a continuous fashion without deterioration of the metal support structure. In a separate operation, an interconnection substrate structure is provided, optionally in a continuous fashion. Multiple photovoltaic cells are then laminated to the interconnection substrate structure and conductive joining methods are employed to complete the array. In this way the interconnection substrate structure can be uniquely formulated from polymer-based materials employing optimal processing unique to polymeric materials. Furthermore, the photovoltaic junction and its metal foil support can be produced in bulk without the need to use the expensive and intricate material removal operations currently taught in the art to achieve series interconnections.Type: GrantFiled: May 19, 2008Date of Patent: June 8, 2010Inventor: Daniel Luch
-
Patent number: 7709288Abstract: The present invention provides a method for manufacturing a multi-junction solar cell which makes it possible to implement a 4-junction solar cell and to increase the area of a device. A nucleus generation site is disposed on a substrate 2 made of a first semiconductor. A first material gas is fed to the nucleus generation site to form a wire-like semiconductor 3 in the nucleus generation site. A third material gas and a fourth material gas are fed to form a wire-like semiconductor 4 on the semiconductor 3 and a wire-like semiconductor 5 on the semiconductor 4. A nucleus generation site is disposed on a substrate 6. The first material gas is fed to the nucleus generation site to form a wire-like semiconductor 2a in the nucleus generation site. A second material gas to the fourth material gas are fed to form the wire-like semiconductor 3 on the semiconductor 2a, the wire-like semiconductor 4 on the semiconductor 3, and the wire-like semiconductor 5 on the semiconductor 4.Type: GrantFiled: July 17, 2007Date of Patent: May 4, 2010Assignee: Honda Motor Co., Ltd.Inventor: Hajime Goto
-
Publication number: 20100075455Abstract: The present invention relates to a film formation apparatus including a first transfer chamber having a roller for sending a substrate, a film formation chamber having a discharging electrode, a buffer chamber provided between the transfer chamber and the film formation chamber or between the film formation chambers, a slit provided in a portion where the substrate comes in and out in the buffer chamber, and a second transfer chamber having a roller for rewinding the substrate. The slit is provided with at least one touch roller, and the touch roller is in contact with a film formation surface of the substrate. In addition, the present invention also relates to a method for forming a film and a method for manufacturing a photoelectric conversion device that are performed by using such a film formation apparatus.Type: ApplicationFiled: November 30, 2009Publication date: March 25, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Yoshikazu HIURA, Hiroki ADACHI, Hironobu TAKAHASHI, Yuusuke SUGAWARA, Tatsuya ARAO, Kazuo NISHI, Yasuyuki ARAI
-
Patent number: 7674710Abstract: A method for integrating a metal-containing film in a semiconductor device, for example a gate stack. In one embodiment, the method includes providing a substrate in a process chamber, depositing the tungsten-containing film on the substrate at a first substrate temperature by exposing the substrate to a deposition gas containing a tungsten carbonyl precursor, heat treating the tungsten-containing film at a second substrate temperature greater than the first substrate temperature to remove carbon monoxide gas from the tungsten-containing film, and forming a barrier layer on the heat treated tungsten-containing film. Examples of tungsten-containing films include W, WN, WSi, and WC. Additional embodiments include depositing metal-containing films containing Ni, Mo, Co, Rh, Re, Cr, or Ru from the corresponding metal carbonyl precursors.Type: GrantFiled: November 20, 2006Date of Patent: March 9, 2010Assignee: Tokyo Electron LimitedInventors: Shigeo Ashigaki, Hideaki Yamasaki, Tomoyuki Sakoda, Mikio Suzuki, Genji Nakamura, Gert Leusink
-
Patent number: 7667233Abstract: A display device and a flat lamp that have simple structures and can be fabricated using simple fabricating processes, and a method of fabricating the display device and the flat lamp. The display device includes: a first substrate and a second substrate facing each other across a predetermined distance; barrier ribs defining light emitting cells with the first substrate and the second substrate; an anode electrode disposed in the light emitting cell; a conductive silicon layer disposed on an inner surface of one of the first and second substrates; an oxidized porous silicon layer, at least a part of which is disposed on the conductive silicon layer; and a gas contained in the light emitting cell. The fabrication method includes doping part of a silicon layer on the inner surface of the first or second substrate and changing another part of the silicon layer to an oxidized porous silicon layer.Type: GrantFiled: November 20, 2006Date of Patent: February 23, 2010Assignee: Samsung SDI Co., Ltd.Inventors: Hyoung-Bin Park, Seung-Hyun Son, Sang-Hun Jang, Gi-Young Kim, Sung-Soo Kim, Ho-Nyeon Lee
-
Patent number: 7615400Abstract: There is provided a method for producing a multijunction solar cell having four-junctions, the method allowing the area of a device to be increased. On a nucleation site formed on a substrate 2, is grown a semiconductor 2a comprising the same material as the substrate 2 in the shape of a wire. On the semiconductor 2a, are successively grown semiconductors 3, 4, 5, and 6 with a narrower band gap in the shape of a wire. The semiconductor 3 may be directly grown in the shape of a wire on the nucleation site formed on the substrate 2. It is preferred to form the nucleation site by forming an amorphous SiO2 coating 8a on the substrate 2 and etching a part of the amorphous SiO2 coating 8a. Further, it is preferred to form an insulating film 8 in the region except the nucleation sites on the substrate 2 by allowing the amorphous SiO2 coating 8a to remain therein. The semiconductor 2a is GaP; the semiconductor 3 is Al0.3Ga0.7As; the semiconductor 4 is GaAs; the semiconductor 5 is In0.3Ga0.Type: GrantFiled: September 30, 2008Date of Patent: November 10, 2009Assignee: Honda Motor Co., Ltd.Inventors: Hajime Goto, Junichi Motohisa, Takashi Fukui
-
Patent number: 7588957Abstract: The present invention generally comprises a method and apparatus for supplemental pumping, gas feed, and/or RF current for a process. When depositing amorphous silicon, the amount of process gases, RF current, and vacuum may be less than the amount of process gases, RF current, and vacuum necessary to deposit microcrystalline silicon. When a single chamber is used to deposit both amorphous and microcrystalline silicon, coupling a supplemental power supply, a supplemental gas source, and a supplemental vacuum pump to the chamber may be beneficial. The supplemental power supply, vacuum pump, and gas source, may be coupled with the chamber when the microcrystalline silicon is deposited and uncoupled when amorphous silicon is deposited. In a cluster tool arrangement, the supplemental power supply, vacuum pump, and gas source may serve multiple chambers that each deposit both amorphous and microcrystalline silicon.Type: GrantFiled: October 17, 2007Date of Patent: September 15, 2009Assignee: Applied Materials, Inc.Inventor: John M. White
-
Patent number: 7566636Abstract: There is provided a method of scribing a stuck mother substrate for obtaining a plurality of stuck substrates formed by sticking a first square substrate and a second square substrate together so that one side of opposing two sides of the square substrates is aligned and the other side is not aligned so that the first substrate is set back to the second substrate from a stuck mother substrate in which a first mother substrate and a second mother substrate are stuck together. In the method of scribing a stuck mother substrate, the second mother substrate is strongly scribed for a full scribe line and the first mother substrate is strongly scribed for a half scribe line. On the other hand, the first mother substrate is weakly scribed for the full scribe line.Type: GrantFiled: August 28, 2007Date of Patent: July 28, 2009Assignee: Seiko Epson CorporationInventors: Makoto Nakadate, Norihiko Kato, Yoichi Miyasaka
-
Patent number: 7541227Abstract: Thin film devices and methods for forming the same are disclosed herein. A method for forming a thin film device includes forming a first at least semi-conductive strip located at a first height relative to a surface of a substrate, and forming a second at least semi-conductive strip adjacent to the first at least semi-conductive strip. The second strip is located at a second height relative to the substrate surface, and the second height is different than the first height. A nano-gap is formed between the first and second at least semi-conductive strips.Type: GrantFiled: October 30, 2006Date of Patent: June 2, 2009Assignee: Hewlett-Packard Development Company, L.P.Inventors: Ping Mei, Craig M. Perlov, Albert Hua Jeans, Carl Philip Taussig
-
Patent number: 7510901Abstract: With a conventional cylindrical can method, a region used as a film formation ground electrode is a portion of the cylindrical can, and an apparatus becomes larger in size in proportion to the surface area of the electrode. A conveyor device and a film formation apparatus having the conveyor device are provided, which have a unit for continuously conveying a flexible substrate from one end to the other end, and which are characterized in that a plurality of cylindrical rollers are provided between the one end and the other end along an arc with a radius R, the cylindrical rollers being arranged such that their center axes run parallel to each other, and that a mechanism for conveying the flexible substrate while the substrate is in contact with each of the plurality of cylindrical rollers is provided.Type: GrantFiled: June 22, 2005Date of Patent: March 31, 2009Assignees: Semiconductor Energy Laboratory Co., Ltd., TDK CorporationInventors: Masato Yonezawa, Naoto Kusumoto, Hisato Shinohara
-
Publication number: 20080210299Abstract: The invention relates to a method of fabricating photovoltaic cells in which at least one layer of semiconductor material is deposited continuously on a carbon ribbon (10) to form a composite ribbon (20), said layer having a free face (22, 24) opposite from its face in contact with the carbon ribbon. According to the invention, at least one treatment (28) is applied to the layer of semiconductor material, from said free face (22, 24), in order to implement photovoltaic functions of the cells on said layer, prior to eliminating the carbon ribbon (10). The invention makes it possible to increase productivity in the fabrication of photovoltaic cells, which cells can be of very small thicknesses.Type: ApplicationFiled: December 8, 2005Publication date: September 4, 2008Inventors: Christian Belouet, Claud Remy
-
Patent number: 7211460Abstract: A semiconductor device includes alignment marks that are aligned with device features. The semiconductor device includes a device feature, a pair of first alignment marks, a pair of second alignment marks, and a pair of third alignment marks. The first alignment marks are aligned along a first direction with the device feature and adjacent to opposite sides of the device feature. The second alignment marks are aligned along a second direction with the device feature that is substantially perpendicular to the first direction, and adjacent to opposite sides of the device feature. The third alignment marks are aligned with the first alignment marks in the first direction and adjacent to opposite sides of the device feature, wherein the third marks are between the first alignment marks and the device feature, and each of the third marks have a shorter length along the first direction than each of the first alignment marks.Type: GrantFiled: October 7, 2004Date of Patent: May 1, 2007Assignee: Samsung Electronics Co. Ltd.Inventor: Taek-jin Lim
-
Patent number: 7157309Abstract: An elongated strip of a sheetlike substrate bearing microelectronic elements such as semiconductor chips is advanced in a downstream direction through one or more folding stations where successive portions of the substrate are folded so as to form a strip including a plurality of fold packages, each including confronting top and bottom runs and a fold region with one or more of the runs bearing one or more microelectronic elements. The strip incorporating the plural fold packages can be wound on a reel or otherwise handled, stored and shipped to a subsequent manufacturing operation, where individual fold packages can be severed from the strip.Type: GrantFiled: September 27, 2004Date of Patent: January 2, 2007Assignee: Tessera, Inc.Inventors: Nicholas J. Colella, Giles Humpston
-
Patent number: 7063999Abstract: A thin film processing method for processing the thin film by irradiating an optical beam to the thin film. A unit of the irradiation of the optical beam includes a first and a second optical pulse irradiation to the thin film, and the unit of the irradiation is carried out repeatedly to process the thin film. The first and the second optical pulse have pulse waveforms different from each other. Preferably, a unit of the irradiation of the optical beam includes the a first optical pulse irradiated to the thin film and a second optical pulse irradiated to the thin film starting substantially simultaneous with the first optical pulse irradiation. In this case, the relationship between the first and the second optical pulse satisfies (the pulse width of the first optical pulse)<(the optical pulse of the second optical pulse) and (the irradiation intensity of the first optical pulse)?(the irradiation intensity of the second optical pulse).Type: GrantFiled: May 10, 2001Date of Patent: June 20, 2006Assignees: NEC Corporation, Sumitomo Heavy Industries, Ltd.Inventors: Hiroshi Tanabe, Akihiko Taneda
-
Patent number: 6949400Abstract: An ultrasonic slitting device cuts and seals the edges of photovoltaic cells and modules to encapsulate the photoactive components in an environment substantially impervious to the atmosphere.Type: GrantFiled: January 24, 2003Date of Patent: September 27, 2005Assignee: Konarka Technologies, Inc.Inventor: James Ryan
-
Patent number: 6943066Abstract: An electronic device is formed from electronic elements deposited on a substrate. The electronic elements are deposited on the substrate by advancing the substrate through a plurality of deposition vacuum vessels, with each deposition vacuum vessel having at least one material deposition source and a shadowmask positioned therein. The material from at least one material deposition source positioned in each deposition vacuum vessel is deposited on the substrate through the shadowmask positioned in the deposition vacuum vessel to form on the substrate a circuit comprised of an array of electronic elements. The circuit is formed solely by the successive deposition of materials on the substrate.Type: GrantFiled: September 26, 2002Date of Patent: September 13, 2005Assignee: Advantech Global, LTDInventors: Thomas P. Brody, Paul R. Malmberg, David J. Stapleton, Robert E. Stapleton
-
Patent number: 6916509Abstract: With a conventional cylindrical can method, a region used as a film formation ground electrode is a portion of the cylindrical can, and an apparatus becomes larger in size in proportion to the surface area of the electrode. A conveyor device and a film formation apparatus having the conveyor device are provided, which have a unit for continuously conveying a flexible substrate from one end to the other end, and which are characterized in that a plurality of cylindrical rollers are provided between the one end and the other end along an arc with a radius R, the cylindrical rollers being arranged such that their center axes run parallel to each other, and that a mechanism for conveying the flexible substrate while the substrate is in contact with each of the plurality of cylindrical rollers is provided.Type: GrantFiled: November 5, 2004Date of Patent: July 12, 2005Assignees: Semiconductor Energy Laboratory Co., Ltd., TDK CorporationInventors: Masato Yonezawa, Naoto Kusumoto, Hisato Shinohara
-
Patent number: 6794727Abstract: A process for continuous manufacture of electronic modules (6) including the steps of providing a microcircuit and antenna receiving side on a continuous strip (8) and module surface areas; arranging, e.g., by printing, on the module surface area, a plane spiral antenna (2) wholly arranged to this area; fixing on said strip (8) a microcircuit (7) provided with contact pads (13, 14) after placing an insulator between the microcircuit the strip (8); making an electric connection between the antenna (2) and of the microcircuit.Type: GrantFiled: September 25, 2002Date of Patent: September 21, 2004Assignee: GemplusInventors: Michel Leduc, Philippe Martin, Richard Kalinowski
-
Patent number: 6710266Abstract: A technique to simultaneously reduce high-frequency insertion loss and cross-talk for a multi-layered add-in card is disclosed. The technique is based on selective removal of ground and power planes beneath the edge fingers. This selective removal of power and ground planes removes excess capacitance at the edge fingers, lowering the insertion loss at high frequencies, while maintaining an impedance match with an associated connector. Simultaneously, the leftover metallic ground/power plane provides electromagnetic shielding and thus reduces the cross-talk between the differential pairs. Optimum performance of the connector with minimized insertion loss and cross-talk can be obtained for high-speed analog and digital applications.Type: GrantFiled: July 26, 2002Date of Patent: March 23, 2004Assignee: Intel CorporationInventors: Jason A. Mix, Yun Ling, Alok Tripathi, Kent E. Mallory
-
Patent number: 6652904Abstract: The present invention relates to manufacturing of regenerative photovolatic photoelectrochemical (RPEC) devices. The invention describes a method for manufacturing RPEC devices in a production line. The method comprises the steps of: dispensing a protective film in a substantially continuous sheet; attaching at least one substrate to the protective film in such a way that predetermined areas of the substrate are protected from being coated during at least one subsequent manufacturing process; using the protective films as a means to transport the substrate, along the production line through the at least one subsequent manufacturing process.Type: GrantFiled: November 30, 2001Date of Patent: November 25, 2003Assignee: Sustainable Technologies International Pty. LimitedInventors: George Phani, Jason Andrew Hopkins, David Vittorio
-
Patent number: 6642077Abstract: The invention concerns a method for manufacturing and assembling individual photovoltaic silicon cells on a metal substrate, including the operations of: making a metal plate (25) provided with cut out portions (26, 29) separated from each other by points of attachment (27) and delimiting the bases of a plurality of cells; depositing a stack of silicon layers then a metallization on said plate in order to form a group of individual cells (28a-b-c-d); transferring said group onto an interconnection support (30); and perforating the points of attachment in order to separate the cells from the rest of the plate.Type: GrantFiled: September 22, 2000Date of Patent: November 4, 2003Assignee: Asulab S.A.Inventor: Jean-Claude Berney
-
Patent number: 6558990Abstract: A manufacturing method of a SOI substrate (10) comprises the steps of: forming an oxide film (12) at cross-sectional both main surfaces and cross-sectional both end surfaces of a silicon substrate (11); forming a resist layer (13) on the oxide film (12) at cross-sectional both end surfaces of the substrate (11); and removing the oxide film (12) at those portions which are left from the covering of the resist layer (13), to thereby expose the both main surfaces of the substrate (11). Next, the resist layer (13) is removed to thereby leave the oxide film (12) at the both end surfaces of the substrate (11); and oxygen ions (I) are dosed into the substrate (11) from one of the exposed both main surfaces, followed by an anneal processing to thereby form an oxide layer (14) in a region at a predetermined depth from the one main surface of the substrate (11). The oxide film (12) left on the both end surfaces of the substrate (11) is then removed.Type: GrantFiled: March 1, 2001Date of Patent: May 6, 2003Assignees: Mitsubishi Materials Silicon Corporation, Mitsubishi Denki Kabushiki KaishaInventors: Masaru Takamatsu, Takashi Katakura, Toshiaki Iwamatsu, Hideki Naruoka
-
Publication number: 20030049881Abstract: A processed article is provided with a plurality of IDs having the same information for machine reading but difference to be confirmed visually. The information such as the production lot number which is read from the plurality of IDs by the reading device is the same, but these plurality of IDs are different in external appearance, for example in size or color. By corresponding such difference of the plurality of IDs in the external appearance to the positional information in the processing apparatus for the article, new information can be added to the ID without introducing a new ID printer or a reading device. A prompt measure to a trouble in production is made possible based on the information such as the position of the article. Also the defective processed article can be easily selected, thereby improving the production yield and achieving a cost reduction.Type: ApplicationFiled: July 31, 2002Publication date: March 13, 2003Inventors: Takeshi Takada, Toshihiko Mimura, Naoto Okada
-
Patent number: 6482668Abstract: In the step of forming a microcrystalline i-type semiconductor layer by high-frequency plasma CVD, wherein an area of the parallel-plate electrode is represented by S; a width of the discharge space in its direction perpendicular to the transport direction of the belt-like substrate, by Ws; a width of a region formed by the parallel-plate electrode together with its surrounding insulating region, in its direction perpendicular to the transport direction of the belt-like substrate, by Wc; a width of the belt-like substrate in the direction perpendicular to its transport, by Wk; a distance between the parallel-plate electrode and the belt-like substrate, by h; a power density at which crystal fraction begins to saturate at predetermined substrate temperature, material gas flow rate and pressure, by Pd; and a high-frequency power, by P, 2h/(Ws−Wc)≧2.5, (Ws/h)×2(Ws−Wk)/[4h+(Ws−Wc) ]≧10, and P≧(10/8)×Pd×S.Type: GrantFiled: March 2, 1999Date of Patent: November 19, 2002Assignee: Canon Kabushiki KaishaInventors: Naoto Okada, Masahiro Kanai, Hirokazu Ohtoshi, Tadashi Hori
-
Patent number: 6399411Abstract: A method for forming a non-single-crystal semiconductor thin film and a photovoltaic device using an apparatus, which has a film deposition chamber with a film-forming space surrounded by a film deposition chamber wall and a belt-like substrate. An external chamber surrounding the deposition chamber wall is provided in the apparatus. While the belt-like substrate is moved in a longitudinal direction, a film-forming gas is introduced through a gas supply device into the film-forming space and microwave energy is radiated from a microwave applicator into the film-forming space to induce a microwave plasma, and thereby form a non-single-crystal semiconductor thin film on a surface of the belt-like substrate. A cooling mechanism and a temperature-increasing mechanism covering a part of an outside surface of the deposition chamber wall provide temperature control.Type: GrantFiled: June 15, 2000Date of Patent: June 4, 2002Assignee: Canon Kabushiki KaishaInventors: Tadashi Hori, Shotaro Okabe, Akira Sakai, Yuzo Kohda, Takahiro Yajima
-
Patent number: 6362020Abstract: The present invention provides a process of forming a deposited film on a belt-like substrate by a roll-to-roll system, the process comprising the step of eliminating a curl deformation of the belt-like substrate resulting from application of a deformation stress, by exerting an external stress on a non-depositing surface of the belt-like substrate. It can prevent occurrence of flaws, defects of appearance, defects of electrode, and so on in succeeding steps etc. and can produce semiconductor elements and photovoltaic elements with high quality at a high yield.Type: GrantFiled: January 28, 1999Date of Patent: March 26, 2002Assignee: Canon Kabushiki KaishaInventors: Hiroshi Shimoda, Keishi Saito
-
Patent number: 6338872Abstract: A film forming method is described using an apparatus with a plurality of vacuum chambers which communicate with each other via a connection, where the apparatus has one or more detachable treatment rooms and where the method includes continuously forming a plurality of films on a band-shaped substrate within the treatment rooms, while continuously moving the substrate through the treatment rooms. The treatment rooms within said desired vacuum chambers are replaced after forming the film for a predetermined period as a part of the film forming method.Type: GrantFiled: June 22, 1999Date of Patent: January 15, 2002Assignee: Canon Kabushiki KaishaInventors: Takehito Yoshino, Hiroshi Echizen, Masahiro Kanai, Hirokazu Otoshi, Atsushi Yasuno, Kohei Yoshida, Koichiro Moriyama, Masatoshi Tanaka
-
Patent number: 6326664Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode and a raised region.Type: GrantFiled: November 17, 1997Date of Patent: December 4, 2001Assignee: Intel CorporationInventors: Robert S. Chau, Chan-Hong Chern, Chia-Hong Jan, Kevin R. Weldon, Paul A. Packan, Leopoldo D. Yau
-
Patent number: 6268235Abstract: In a method of manufacturing a photoelectric conversion device, a step of forming a microcrystalline semiconductor film and a step of implanting an impurity element into the microcrystalline semiconductor film are separated from each other so that the productivity of the photoelectric conversion device by a roll-to-roll system manufacturing apparatus is increased. In the method, first, a first electrode is formed on an organic resin substrate. Then a first microcrystalline semiconductor film, a substantially intrinsic amorphous semiconductor film, and a second microcrystalline semiconductor film are continuously formed by a roll-to-roll system plasma CVD method. The first and second microcrystalline semiconductor films are formed without adding n-type or p-type conductivity determining impurity elements. After the formation of the films, a p-type conductivity determining impurity element is implanted into the second microcrystalline semiconductor film.Type: GrantFiled: January 21, 1999Date of Patent: July 31, 2001Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masayuki Sakakura, Yasuyuki Arai, Shunpei Yamazaki
-
Patent number: 6261862Abstract: A process is provided for producing a photovoltaic element which has at least one pin junction, and a buffering semiconductor layer constituted of plural sublayers between an n-type layer and an i-type layer and/or between an i-type layer and a p-type layer, through production steps of introducing a source material gas into an electric discharge space in a reaction chamber, and decomposing the source material gas by plasma discharge to form a non-monocrystalline semiconductor layer. In the process, in electric discharge generation for formation of at least one of the sublayers, the polarity of the electrode confronting the substrate for formation of a first sublayer and the polarity of the electrode confronting the substrate for formation of a second sublayer adjacent to the first sublayer is made different from each other, or the potential of one of the electrodes is set at zero volt. Thereby, diffusion of the dopant from the p-type layer or the n-type layer into the i-type layer is prevented effectively.Type: GrantFiled: July 23, 1999Date of Patent: July 17, 2001Assignee: Canon Kabushiki KaishaInventors: Tadashi Hori, Masahiro Kanai, Hirokazu Ohtoshi, Naoto Okada, Koichiro Moriyama, Hiroshi Shimoda, Hiroyuki Ozaki
-
Patent number: 6239352Abstract: This invention comprises deposition of thin film photovoltaic junctions on metal substrates which can be heat treated following deposition in a continuous fashion without deterioration of the metal support structure. In a separate operation, an interconnection substrate structure is produced in a continuous roll-to-roll fashion. In this way the interconnection substrate structure can be uniquely formulated from polymer-based materials since it does not have to endure high temperature exposure. Cells comprising the metal foil supported photovoltaic junctions are then laminated to the interconnection substrate structure. Conductive interconnections are deposited to complete the array. The conductive interconnections can be accomplished with a separately prepared interconnection component.Type: GrantFiled: March 30, 1999Date of Patent: May 29, 2001Inventor: Daniel Luch
-
Patent number: 6185472Abstract: A semiconductor device manufacturing method capable of proceeding semiconductor device manufacturing processes according to predetermined schedules or while correcting them without testpieces is provided. The method includes the steps of collecting actually observed data during at least one of plural steps, obtaining prediction data in at least one of plural steps by using an ab initio molecular dynamics process simulator or a molecular dynamics simulator, comparing and verifying the prediction data and the actually observed data sequentially at real time, and correcting and processing the plural manufacturing process factors sequentially at real time if a difference in significance is recognized between set values for the plural manufacturing process factors and the plural manufacturing process factors estimated from the actually observed data according to comparison and verification.Type: GrantFiled: December 27, 1996Date of Patent: February 6, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Onga, Takako Okada, Hiroshi Tomita, Kikuo Yamabe, Haruo Okano
-
Patent number: 6140146Abstract: Processes and apparatus for manufacturing radio frequency transponders having substrates formed from a flexible tape or film are disclosed. The RF transponders are formed on the tape so that their longest dimension (e.g., their length ("L")) is oriented parallel to the length of the tape. This layout places few or no constraints in the transponder's length allowing the length of the transponder's antenna circuit to be adjusted to satisfy the requirements of various applications.Type: GrantFiled: August 3, 1999Date of Patent: October 31, 2000Assignee: Intermec IP Corp.Inventors: Michael John Brady, Dah-Weih Duan, Harley Kent Heinrich
-
Patent number: 6136141Abstract: Lightweight semiconductor devices are fabricated upon a relatively thin substrate member by a process wherein the substrate is first bonded to a relatively thick support member. The semiconductor device is then formed on the bonded substrate, and the substrate is subsequently removed from the support member by utilizing a beam of radiant energy to skive the substrate from the support member without damage to the semiconductor device. Also disclosed herein is a system for implementing the invention.Type: GrantFiled: June 10, 1998Date of Patent: October 24, 2000Assignee: Sky Solar L.L.C.Inventors: Troy Glatfelter, Mark Lycette, Eric Akkashian
-
Patent number: 6069313Abstract: A plurality of series-connected elements are arranged, as parallel elongated stripes, on a common electrically insulating transparent substrate (1). Each element comprises a photoanode (4), a porous counterelectrode or cathode (6) and an intermediate electrically insulating porous layer (5) separating the photoanode (4) from the cathode (6). The pores of the intermediate layer (5), the photoanode (4) and the cathode (6) are at least partially filled with an electron transferring electrolyte. An intermediate layer (2) of a transparent electrically conducting material is interposed between the substrate (1) and each photoanode (4). The cathode (6) of the first photovoltaic element of the series is electrically connected with a first terminal (9) of the battery. The cathode (6) of each following element is connected with the intermediate conducting layer (2) of the preceding element, over a gap (3) separating the respective intermediate layers (2) of these two elements.Type: GrantFiled: June 5, 1998Date of Patent: May 30, 2000Assignee: Ecole Polytechnique Federale de LausanneInventor: Andreas Kay
-
Patent number: 5963789Abstract: A method is disclosed of manufacturing improved device structures which include a device structure having STI and a thin foot charge drain beneath the device area on an inexpensive bulk silicon substrate. The structures retain high speed operation of SOI devices without any adverse effects of charge build-up and floating effects as observed in conventional SOI devices, and, furthermore, are constructed without any extra process steps added to the conventional STI technology except for an isotropic etching step. The invention also contemplates construction of multi-level electronic circuit.Type: GrantFiled: July 8, 1996Date of Patent: October 5, 1999Assignee: Kabushiki Kaisha ToshibaInventor: Masakatsu Tsuchiaki
-
Patent number: 5897332Abstract: A method for manufacturing a photoelectric conversion element containing at least one pin junction, wherein a diffusion preventing layer is provided between an n-type layer and an i-type layer and/or between an i-type layer and a p-type layer, and the diffusion preventing layer is deposited such that deposition temperature differs in its thickness direction.Type: GrantFiled: September 23, 1996Date of Patent: April 27, 1999Assignee: Canon Kabushiki KaishaInventors: Tadashi Hori, Shotaro Okabe, Masahiro Kanai, Akira Sakai, Yuzo Kohda, Tomonori Nishimoto, Takahiro Yajima
-
Patent number: 5800632Abstract: A method for manufacturing a photovoltaic device comprising a metal layer, a first transparent conductive layer, a semiconductor layer, and a second transparent conductive layer sequentially stacked on a substrate comprising iron, comprises the steps of forming the metal layer by electro-deposition of the metal layer from a solution and forming the first transparent conductive layer by electro-deposition of the first transparent conductive layer from a solution.Type: GrantFiled: September 24, 1996Date of Patent: September 1, 1998Assignee: Canon Kabushiki KaishaInventors: Kozo Arao, Katsumi Nakagawa, Yukiko Iwasaki
-
Patent number: 5753531Abstract: A method of continuous manufacture of semiconductor integrated circuits, said method and apparatus adapted to contain the semiconductor substrate, semiconductor deposition coating processes, and etching processes within a substantially collocated series of process chambers so that the semiconductor travels from one chamber to the next without exposure to airborne impurities and contact with manufacturing personnel. The invention has particular utility in the high volume fabrication of large surface area semiconductor circuits such as active matrix liquid crystal displays. The present invention contains a roll-to-roll and continuous belt embodiment.Type: GrantFiled: June 3, 1996Date of Patent: May 19, 1998Assignee: The University of Maryland at College ParkInventor: Jeffrey Frey
-
Patent number: 5712199Abstract: A method of making a semiconductor body includes the steps of preparing a sheet-like substrate having an insulating film and holes which pass through the insulating film, the holes being disposed at a uniform density, preparing a solution in which a semiconductor material is dissolved, and conveying the sheet-like substrate along a surface of the solution so as to grow a single crystal nucleus from each of the holes and thereby form a set of single crystal semiconductors on the sheet-like substrate. A solar cell can be manufactured by forming a semiconductor active area on the sheet-like support member made of a conductive material by a process containing the above-described semiconductor body forming method, and then by forming an electrode which makes a pair with the sheet-like support member.Type: GrantFiled: June 6, 1995Date of Patent: January 27, 1998Assignee: Canon Kabushiki KaishaInventors: Katsumi Nakagawa, Takao Yonehara