Abstract: A method of manufacturing a semiconductor device includes a groove portion formation process of forming a groove portion in a base body, a bather layer formation process of forming a barrier layer covering at least the inner wall surface of the groove portion, a seed layer formation process of forming a seed layer covering the barrier layer, and a seed layer melting process of causing the seed layer to be melted using the reflow method. The seed layer is made of Cu.

Abstract: Forming of a microelectronic device including a substrate containing at least one conductive pad, the pad being provided with a bottom surface resting on the substrate and an upper surface opposite the bottom surface. The upper surface of the pad has a stack applied thereto formed of a conductive layer and a protective dielectric layer including an opening called first opening facing the pad and exposing the conductive layer. At least one insulating block is arranged on a peripheral region of the upper surface of the pad, the insulating block having a cross-section forming a closed contour and having an opening called second opening. A conductive pillar is located in the center of the contour in the second opening.

Abstract: A technique for forming nanostructures including introducing a plurality of molecular-size scale and/or nanoscale building blocks to a region near a substrate and simultaneously scanning a pattern on the substrate with an energy beam, wherein the energy beam causes a change in at least one physical property of at least a portion of the building blocks, such that a probability of the portion of the building blocks adhering to the pattern scanned by the energy beam is increased, and wherein the building blocks adhere to the pattern to form the structure. The energy beam and at least a portion of the building blocks may interact by electrostatic interaction to form the structure.

Abstract: Provided is a conductive paste, an electrode for a semiconductor device manufactured by using the conductive paste, a semiconductor device and a method for manufacturing the semiconductor device. The conductive paste includes conductive powder made of a plurality of conductive particles and silver powder made of a plurality of silver particles. The conductive particles includes a base material made of ceramics and a conductive layer configured to cover at least a part of an outer surface of the base material. The ratio of the mass of the conductive layer relative to the total mass of the conductive particles is 10% or more by mass, and the ratio of the mass of the conductive powder relative to the total mass of the conductive powder and the silver powder is 25% or less by mass.

Abstract: A method for producing a metal contact structure of a photovoltaic solar cell, including: applying an electrically non-conductive insulating layer to a semiconductor substrate, applying a metal contact layer to the insulating layer, and generating a plurality of local electrically conductive connections between the semiconductor substrate and the contact layer right through the insulating layer. The metal contact layer is formed using two pastes containing metal particles: the first paste containing metal particles is applied to local regions, and the second paste containing metal particles is applied covering at least the regions covered with the first paste and partial regions located therebetween.

Abstract: A method for forming a non-volatile memory device includes providing a substrate having a surface region, forming a first wiring structure overlying the surface region, depositing a first dielectric material overlying the first wiring structure, forming a via opening in the first dielectric material to expose a portion of the first wiring structure, while maintaining a portion of the first dielectric material, forming a layer of resistive switching material comprising silicon, within the via opening, forming a silver material overlying the layer of resistive switching material and the portion of the first dielectric material, forming a diffusion barrier layer overlying the silver material, and selectively removing a portion of the silver material and a portion of the diffusion barrier layer overlying the portion of the first dielectric material while maintaining a portion of the silver material and a portion of the diffusion barrier material overlying the layer of silicon material.

Abstract: In using Ni(P) and Sn-rich solders in Pb free interconnections, the prevention and control of the formation of intermetallic compound inclusions can be achieved through a reaction-preventative or control layer that is positioned on top of an electroless Ni(P) metallization, such as by application of a thin layer of Sn on the Ni(P) or through the application of a thin layer of Cu on the Ni(P).

Abstract: In using Ni(P) and Sn-rich solders in Pb free interconnections, the prevention and control of the formation of intermetallic compound inclusions, can be achieved through a reaction preventive or control layer that is positioned on top of an electroless Ni(P) metallization, such as by application of a thin layer of Sn on the Ni(P) or through the application of a thin layer of Cu on the Ni(P).

Abstract: A method of fabricating a semiconductor device includes forming a bottom electrode material layer containing aluminum and copper over the substrate. An insulating material layer and a top electrode material layer are sequentially formed on the surface of the bottom electrode material layer. A photoresist pattern is formed on the top electrode material layer, and then the top electrode material layer is patterned to form a top electrode by using the photoresist pattern as mask. The photoresist pattern is removed by plasma ash and then an alloy process is performed to the bottom electrode material layer. Thereafter, the insulating material layer, and the bottom electrode material layer are patterned to form a patterned insulating layer and a patterned bottom electrode layer.

Abstract: A method of fabricating a nonvolatile memory device includes providing an intermediate structure in which a floating gate and an isolation film are disposed adjacent to each other on a semiconductor substrate and a gate insulating film is disposed on the floating gate and the isolation film, forming a conductive film on the gate insulating film, and annealing the conductive film so that part of the conductive film on an upper portion of the floating gate flows down onto a lower portion of the floating gate and an upper portion of the isolation film.

Abstract: A lead-free conductive paste composition contains a source of an electrically conductive metal, a fusible material, an optional additive, and an organic vehicle. An article such as a high-efficiency photovoltaic cell is formed by a process of deposition of the lead-free paste composition on a semiconductor substrate (e.g., by screen printing) and firing the paste to remove the organic vehicle and sinter the metal and fusible material.

Abstract: A wiring substrate may include: a base having a predetermined thickness; a plurality of electrode portions formed to protrude on one surface in a thickness direction of the base; a wiring provided in the base and electrically connected to the electrode portions; and a resin layer formed on the base to fill between the plurality of electrode portions. An upper surface of the resin layer may be formed in a concave shape lower than a maximum height of the electrode portion, and an upper surface of the electrode portion and the upper surface of the resin layer form a continuous curved surface.

Abstract: A method for producing an interconnection structure is disclosed. In one aspect, there is formation in a substrate of at least one trench forming a closed contour and at least one hole situated inside the closed contour, the trench and the hole being separated by a zone of the substrate. Furthermore, the trench is filled with a dielectric material and the hole is filled with a conducting material.

Abstract: A method of manufacturing a solid electrolytic capacitor includes the steps of forming an anode element by sintering powders of a valve metal, washing the anode element with a first wash solution, forming a dielectric film on the anode element after the washing step, and forming a solid electrolytic layer on the dielectric film. The first wash solution is an aqueous solution containing ammonia and hydrogen peroxide.

Abstract: A semiconductor device includes a vertical transistor and an external contact plane. The transistor includes: a first side with a first load electrode and a control electrode, and an opposite second side with a second load electrode. The first side of the transistor faces the external contact plane. A dielectric layer extends from at least one edge side of the transistor as far as the second load terminal. An electrically conductive deposited layer is arranged on the dielectric layer and electrically connects the second load electrode to the second load terminal.

Abstract: The method for processing a metal layer including the following steps is illustrated. First, a semiconductor substrate is provided. Then, a metal layer is formed over the semiconductor substrate. Furthermore, a microwave energy is used to selectively heat the metal layer without affecting the underlying semiconductor substrate and other formed structures, in which the microwave energy has a predetermined frequency in accordance with a material of the metal layer, and the predetermined frequency ranges between 1 KHz to 1 MHz.

Abstract: A nitride-based semiconductor light-emitting device 100 includes a GaN substrate 10, of which the principal surface is an m-plane 12, a semiconductor multilayer structure 20 that has been formed on the m-plane 12 of the GaN-based substrate 10, and an electrode 30 arranged on the semiconductor multilayer structure 20. The electrode 30 includes an Mg alloy layer 32 which is formed of Mg and a metal selected from a group consisting of Pt, Mo, and Pd. The Mg alloy layer 32 is in contact with a surface of a p-type semiconductor region of the semiconductor multilayer structure 20.

Abstract: A nitride-based semiconductor light-emitting device 100 includes: a GaN substrate 10 with an m-plane surface 12; a semiconductor multilayer structure 20 provided on the m-plane surface 12 of the GaN substrate 10; and an electrode 30 provided on the semiconductor multilayer structure 20. The electrode 30 includes a Zn layer 32 and an Ag layer 34 provided on the Zn layer 32. The Zn layer 32 is in contact with a surface of a p-type semiconductor region of the semiconductor multilayer structure 20.

Abstract: A nitride-based semiconductor light-emitting device 100 includes: a GaN substrate 10 with an m-plane surface 12; a semiconductor multilayer structure 20 provided on the m-plane surface 12 of the GaN substrate 10; and an electrode 30 provided on the semiconductor multilayer structure 20. The electrode 30 includes an Mg layer 32 and an Ag layer 34 provided on the Mg layer 32. The Mg layer 32 is in contact with a surface of a p-type semiconductor region of the semiconductor multilayer structure 20.

Abstract: A method for forming a functional element includes a first step of forming an insulating layer composed of an insulator phase of a transition metal oxide serving as a metal-to-insulator transition material, the transition metal oxide being mainly composed of vanadium dioxide, and a second step of causing part of the insulating layer to transition to a metallic phase, in which the insulator phase differs from the metallic phase in terms of electrical resistivity and/or light transmittance.

Abstract: A method includes allowing a work piece having a solder bump to contact a bond head; heating the bond head until the solder bump is melted; and conducting a cooling media into the bond head to cool the solder bump and to solidify the solder bump.

Abstract: A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points. Also, a flip chip package is made by the method. The metallurgical connection includes an alloy of gold and tin at the interface between the bumps and the interconnect points.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a bottom electrode material layer containing aluminum and cupper over the substrate. An insulating material layer and a top electrode material layer are sequentially formed on the surface of the bottom electrode material layer. A photoresist pattern is formed on the top electrode material layer, and then the top electrode material layer is patterned to form a top electrode by using the photoresist pattern as mask. The photoresist pattern is removed by plasma ash and then an alloy process is performed to the bottom electrode material layer. Thereafter, the insulating material layer, and the bottom electrode material layer are patterned to form a patterned insulating layer and a patterned bottom electrode layer.

Abstract: The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnOx (x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a metallic material mainly composed of Cu on the metal film.

Abstract: A semiconductor device includes a substrate, a metal layer, an alloy layer and a Sn—Ag—Cu-based solder ball. The metal layer is configured to be formed on the substrate. The alloy layer is configured to be formed on the metal layer. The Sn—Ag—Cu-based solder ball is configured to be placed on the alloy layer. The alloy layer includes Ni and Zn as essential elements.

Abstract: Disclosed is a method of providing a poly-Si layer used in fabricating poly-Si TFT's or devices containing poly-Si layers. Particularly, a method utilizing at least one metal plate covering the amorphous silicon layer or the substrate, and applying RTA (Rapid Thermal Annealing) for light illuminating process, then the light converted into heat by the metal plate will further be conducted to the amorphous silicon layer to realize rapid thermal crystallization. Thus the poly-Si layer of the present invention is obtained.

Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

Abstract: A method for producing an interconnection structure is disclosed. In one aspect, there is formation in a substrate of at least one trench forming a closed contour and at least one hole situated inside the closed contour, the trench and the hole being separated by a zone of the substrate. Furthermore, the trench is filled with a dielectric material and the hole is filled with a conducting material.

Abstract: The method for forming first and second metal-based materials comprises providing a substrate comprising an area made from a first semi-conductor material and an area made from a second semi-conductor material comprising germanium separated by a pattern made from dielectric material, depositing a metal layer and performing a first heat treatment in an atmosphere comprising a quantity of oxygen comprised between 0.01% and 5%. The metal layer reacts with the first semi-conductor material and the second semi-conductor material comprising germanium to respectively form the first metal-based material and the second metal-based material containing germanium.

Abstract: A semiconductor device includes: a monocrystalline substrate; an inter-layer film formed on the monocrystalline substrate; a contact hole penetrating the inter-layer film and partially exposing an upper surface of the monocrystalline substrate; a sidewall formed on an inner surface of the contact hole; a plurality of first monocrystalline layers which include few defects, fill the contact hole, and cover the inter-layer film; and a plurality of second monocrystalline layers which include many defects and cover the sidewall and an upper surface of the inter-layer film so as to be sandwiched between the first monocrystalline layers and the inter-layer film.

Abstract: Methods for forming thin dielectric films by selectively depositing a conformal film of dielectric material on a high aspect ratio structure have uses in semiconductor processing and other applications. A method for forming a dielectric film involves providing in a deposition reaction chamber a substrate having a gap on the surface. The gap has a top opening and a surface area comprising a bottom and sidewalls running from the top to the bottom. A conformal silicon oxide-based dielectric film is selectively deposited in the gap by first preferentially applying a film formation catalyst or a catalyst precursor on a portion representing less than all of the gap surface area. The substrate surface is then exposed to a silicon-containing precursor gas such that a silicon oxide-based dielectric film layer is preferentially formed on the portion of the gap surface area.

Abstract: A method for fabricating a capacitor includes providing a substrate having a capacitor region is employed, forming a first Ru1?xOx layer over the substrate, forming a Ru layer for a lower electrode over the first Ru1?xOx layer and deoxidizing the first Ru1?xOx layer, forming a dielectric layer over the Ru layer for a lower electrode, and forming a conductive layer for an upper electrode over the dielectric layer, wherein the first Ru1?xOx layer contains oxygen in an amount less than an oxygen amount of a RuO2 layer.

Abstract: A die-on-die assembly has a first die (10) and a second die (50). The first die (10) has a first contact extension (28,42) and a peg (32,44,45) extending a first height above the first die. The second die (50) has a second contact extension (68) connected to the first contact extension and has a containing feature (62) extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.

Abstract: In a semiconductor device manufacturing method which includes a mounting a semiconductor element having a bonding electrode on a substrate, the mounting includes supplying solder paste containing Au—Sn series solder particles onto the substrate, putting the semiconductor element having a film of an Sn alloy or Sn formed on the bonding electrode on the solder paste, and melting the Au—Sn series solder particles and the film of the Sn alloy or Sn to bond the semiconductor element to the substrate.

Abstract: The present invention provides a semiconductor device with a fuse part and a method of forming the same. The method includes forming a selective metal layer on a via hole which is connected to a metal line in a semiconductor device, forming a fuse metal layer on the selective metal layer, and forming a fuse metal layer pattern by using a photosensitive layer pattern which is formed on the fuse metal layer.

Abstract: In a method for producing bases with external contacts for surface mounting on circuit mounts, bases with external contacts are electrodeposited on semiconductor wafers or semiconductor chips. Subsequently, electrodeposited bases with external contacts are heat treated on the semiconductor wafers or the semiconductor chips at temperatures below the melting temperature of the deposited contact base material. Thereafter, a so-called RTP process is carried out in the form of a high-temperature interval in which the melting temperature is reached. Subsequently, the surfaces of the bases with external contacts are wet etched, the overall method being terminated by a cooling and drying operation. The bases with external contacts thus produced can be reliably surface mounted on circuit mounts.

Abstract: A method and apparatus for processing a thin metal layer on a substrate to control the grain size, grain shape, and grain boundary location and orientation in the metal layer by irradiating the metal layer with a first excimer laser pulse having an intensity pattern defined by a mask to have shadow regions and beamlets. Each region of the metal layer overlapped by a beamlet is melted throughout its entire thickness, and each region of the metal layer overlapped by a shadow region remains at least partially unmelted. After completion of resolidification of the melted regions following irradiation by the first excimer laser pulse, the metal layer is irradiated by a second excimer laser pulse having a shifted intensity pattern so that the shadow regions overlap regions of the metal layer having fewer and larger grains.

Abstract: A method for fabricating a silicide gate field effect transistor includes masking a silicon source/drain region prior to forming the silicide gate by annealing a metal silicide forming metal layer contacting a silicon-containing gate. The silicide gate may be either a fully silicided gate or a partially silicided gate. After unmasking the source/drain region a silicide layer may be formed upon the source/drain region, and also upon the partially silicided gate. The second silicide layer and the partially silicided gate also provide a fully silicided gate.

Abstract: A method of fabricating a semiconductor device includes forming a preliminary gate pattern on a semiconductor substrate. The preliminary gate pattern includes a gate oxide pattern, a conductive pattern, and a sacrificial insulating pattern. The method further includes forming spacers on opposite sidewalls of the preliminary gate pattern, forming an interlayer dielectric pattern to expose the sacrificial insulating pattern, removing the sacrificial insulating pattern to form an opening to expose the conductive pattern, transforming the conductive pattern into a metal silicide layer and forming a metal barrier pattern along an inner profile of the opening and a metal conductive pattern to fill the opening including the metal barrier pattern. The metal silicide layer and the metal conductive pattern constitute a gate electrode.

Abstract: A method comprises applying a paste comprising metal grains, a solvent, and a sintering inhibitor to one of a die and a metal layer. The method comprises evaporating the solvent in the paste and placing the one of the die and the metal layer on the other of the die and the metal layer such that the paste contacts the die and the metal layer. The method comprises applying a force to the one of the die and the metal layer and decomposing the sintering inhibitors to form a sintered joint joining the die to the metal layer.

Abstract: A process for fabricating an electrically conductive feature comprising: (a) liquid depositing a low viscosity composition comprising starting ingredients including an organic anine, a silver compound, and optionally an organic acid, to result in a deposited composition; and (b) heating the deposited composition, resulting in the electrically conductive feature comprising silver.

Abstract: A method used during the formation of a semiconductor device assembly can include contacting an end of a conductive bump (which can be a pillar, ball, pad, post, stud, or lead as well as other types of bumps) with a conductive powder such as a solder powder to adhere the conductive powder to the end of the bump. The powder can be flowed, for example by heating, to distribute it across the end of the bump. The flowed powder can be placed in contact with a conductive pad of a receiving substrate and can then be reflowed to facilitate electrical connection between the bump and the conductive pad.

Abstract: In using Ni(P) and Sn-rich solders in Pb free interconnections, the prevention and control of the formation of intermetallic compound inclusions, can be achieved through a reaction preventive or control layer that is positioned on top of an electroless Ni(P) metallization, such as by application of a thin layer of Sn on the Ni(P) or through the application of a thin layer of Cu on the Ni(P

Abstract: Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during thermal post-treatment, such as thermal annealing, conducted after two separately depositing the noble metal and the barrier material, which are substantially soluble in one another. The use of a barrier material within the underlayer prevents the electromigration of the interconnect conductive material and the use of noble material within the underlayer allows for the direct plating of the interconnect conductive material.

Abstract: A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.

Abstract: A method for structuring a laterally extending first layer in a semiconductor device with the aid of a reactive second layer, which together with the first layer to be structured forms first reaction products, which products are removed by material removal that acts selectively on the first reaction products, whereby the structuring takes place in a vertical direction.

Abstract: A process for manufacturing a wiring board comprising a substrate made of an insulation material and having first and second surfaces, first and second conductor patterns formed on the first and second surfaces, respectively, and a via conductor penetrating the substrate to electrically connect the first conductor pattern with the second conductor pattern; the process comprising the following steps of: forming the substrate with a through-hole penetrating thereto and defining openings at the first and second surfaces, respectively; plating the substrate with a metal so that a metal layer having a predetermined thickness is formed on the respective first and second surfaces of the substrate and the through-hole is substantially filled with the metal to be the via conductor; irradiating a laser beam, as a plurality of spots, around a metal-less portion of the plated metal, such as a dimple or seam, at positions corresponding to the openings of the through-hole, so that the a part of the plated metal melts to fi

Abstract: A method and apparatus for processing a thin metal layer on a substrate to control the grain size, grain shape, and grain boundary location and orientation in the metal layer by irradiating the metal layer with a first excimer laser pulse having an intensity pattern defined by a mask to have shadow regions and beamlets. Each region of the metal layer overlapped by a beamlet is melted throughout its entire thickness, and each region of the metal layer overlapped by a shadow region remains at least partially unmelted. Each at least partially unmelted region adjoins adjacent melted regions. After irradiation by the first excimer laser pulse, the melted regions of the metal layer are pemitted to resolidify. During resolidification, the at least partially unmelted regions seed growth of grains in adjoining melted regions to produce larger grains.

Abstract: A porous, flexible, resilient heat transfer material which comprises network of metal flakes. Such heat transfer materials are preferably produced by first forming a conductive paste comprising a volatile organic solvent and conductive metal flakes. The conductive paste is heated to a temperature below the melting point of the metal flakes, thereby evaporating the solvent and sintering the flakes only at their edges. The edges of the flakes are fused to the edges of adjacent flakes such that open pores are defined between at least some of the adjacent flakes, thereby forming a network of metal flakes. This network structure allows the heat transfer material to have a low storage modulus of less than about 10 GPa, while having good electrical resistance properties.

Abstract: Formation of a mixed-material composition through diffusion using photo-thermal energy. The diffusion may be used to create electrically conductive traces. The diffusion may take place between material layers on one of a package substrate, semiconductor substrate, substrate for a printed circuit board (PCB), or other multilayered substrate. The photo-thermal energy may be supplied by various devices, for example a YAG laser device, CO2 laser device, or other energy source.