Abstract: An annealing method and apparatus for semiconductor manufacturing is described. The method and apparatus allows an anneal that can span a thermal budget and be tailored to a specific process and its corresponding activation energy. In some cases, the annealing method spans a timeframe from about 1 millisecond to about 1 second. An example for this annealing method includes a sub-second anneal method where a reduction in the formation of nickel pipes is achieved during salicide processing. In some cases, the method and apparatus combine the rapid heating rate of a sub-second anneal with a thermally conductive substrate to provide quick cooling for a silicon wafer. Thus, the thermal budget of the sub-second anneal methods may span the range from conventional RTP anneals to flash annealing processes (including duration of the anneal, as well as peak temperature). Other embodiments are described.

Abstract: A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal procedure results in formation of a silicon-germanium source/drain region via consumption of a bottom portion of the silicon-germanium layer and a top portion of the underlying source/drain region. Optimization of the formation of the silicon-germanium source/drain region via laser annealing can be achieved via a pre-amorphization implantation (PAI) procedure applied to exposed portions of the source/drain region prior to deposition of the silicon-germanium layer. Un-reacted top portions of the silicon-germanium layer are selectively removed after the laser anneal procedure.

Abstract: A first via opening is formed to a first conductor and a second via opening is formed to a second conductor. The first and second via openings are formed through insulative material. Then, the first conductor is masked from being exposed through the first via opening and to leave the second conductor outwardly exposed through the second via opening. An antifuse dielectric is formed within the second via opening over the exposed second conductor while the first conductor is masked. Then, the first conductor is unmasked to expose it through the first via opening. Then, conductive material is deposited to within the first via opening in conductive connection with the first conductor to form a conductive interconnect within the first via opening to the first conductor and to within the second via opening over the antifuse dielectric to form an antifuse comprising the second conductor, the antifuse dielectric within the second via opening and the conductive material deposited to within the second via opening.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide.

Abstract: A first structure is formed, having a contact plug formed on the bottom of a first opening in an interlayer insulating film, a second opening formed through the interlayer insulating film to reach a semiconductor substrate, and a third opening formed through the interlayer insulating film to reach a polymetal gate electrode. A cobalt layer is deposited on the surface of the structure, and thermally treated to form a cobalt silicide layer on the surface of the contact plug and on the bottom face of the second opening. The structure is then treated to remove the cobalt, in the state in which the cobalt silicide layer is formed, with the use of a chemical solution capable of dissolving cobalt but not the polymetal.

Abstract: A semiconductor device includes a plurality of channel structures on a semiconductor substrate. A bit line groove having opposing sidewalls is defined between sidewalls of adjacent ones of the plurality of channel structures.

Abstract: A method and an apparatus for fabricating a high tensile stress film includes providing a substrate, forming a poly stressor on the substrate, and performing an ultra violet rapid thermal process (UVRTP) for curing the poly stressor and adjusting its tensile stress status, thus the poly stressor serves as a high tensile stress film. Due to a combination of energy from photons and heat, the tensile stress status of the high tensile stress film is adjusted in a relatively shorter process period or under a relatively lower temperature.

Abstract: An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their silicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.

Abstract: A semiconductor device fabrication method by which the thermal stability of nickel silicide can be improved. Nickel (or a nickel alloy) is formed over a semiconductor substrate on which a gate region, a source region, and a drain region are formed. Dinickel silicide is formed by performing a first annealing step, followed by a selective etching step. By performing a plasma treatment step, plasma which contains hydrogen ions is generated and the hydrogen ions are implanted in the dinickel silicide or the gate region, the source region, and the drain region under the dinickel silicide. The dinickel silicide is phase-transformed into nickel silicide by performing a second annealing step.

Abstract: Gate electrode structures having a thin layer of ReO3 formed with high effective work function and high heat resistance are disclosed. The thin layer of ReO3 is formed by providing a semiconductor structure having an oxygen-containing metal alloy layer and a rhenium layer. A heat annealing step diffuses Re from the rhenium layer through the high-oxygen containing metal alloy layer to form a thin layer of ReO3.

Abstract: According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate.

Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed.

Abstract: A method for manufacturing a semiconductor device includes forming an insulation layer having a contact hole on a semiconductor substrate. A metal silicide layer is deposited on a surface of the contact hole and the insulation layer to have a concentration gradient that changes from a silicon-rich composition to a metal-rich composition, with the lower portion of the metal silicide layer having the silicon-rich composition and the upper portion of the metal silicide layer having the metal-rich composition. The metal silicide layer is then annealed so that the compositions of metal and silicon in the metal silicide layer become uniform.

Abstract: The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions. Specifically, each MOSFET comprises source and drain regions located in a semiconductor substrate. Such source and drain regions comprise recesses with one or more sidewall surfaces that are slanted in relation to an upper surface of the semiconductor substrate. A stress-inducing dielectric layer is located over the slanted sidewall surfaces of the recesses at the source and drain regions. Such MOSFETs can be readily formed by crystallographic etching of the semiconductor substrate to form the recesses with the slanted sidewall surfaces, followed by deposition of a stress-inducing dielectric layer thereover.

Abstract: Adhesion of dielectric layer stacks to be formed after completing the basic configuration of transistor elements may be increased by avoiding the formation of a metal silicide in the edge region of the substrate. For this purpose, a dielectric protection layer may be selectively formed in the edge region prior to a corresponding pre-clean process or immediately prior to deposition of the refractory metal. Hence, non-reacted metal may be efficiently removed from the edge region without creating a non-desired metal silicide. Hence, the further processing may be continued on the basis of enhanced process conditions for forming interlayer dielectric materials.

Abstract: A semiconductor device according to the present invention comprises a silicon carbide semiconductor substrate (1) including a silicon carbide layer (2); a high-concentration impurity region (4) provided in the silicon carbide layer (2); an ohmic electrode (9) electrically connected with the high-concentration impurity region (4); a channel region electrically connected with the high-concentration impurity region; a gate insulating layer (14) provided on the channel region; and a gate electrode (7) provided on the gate insulating layer (14). The ohmic electrode (9) contains an alloy of titanium, silicon and carbon, and the gate electrode (7) contains titanium silicide.

Abstract: By performing a silicidation process on the basis of a patterned dielectric layer, such as an interlayer dielectric material, the respective metal silicide portions may be provided in a highly localized manner at the respective contact regions, while the overall amount of metal silicide may be significantly reduced. In this way, a negative influence of the stress of metal silicide on the channel regions of field effect transistors may be significantly reduced, while nevertheless maintaining a low contact resistance.

Abstract: A composite dielectric layer including a nitride layer over an oxide layer serves the dual function of acting as an SMT (stress memorization technique) film while an annealing operation is carried out and then remains partially intact as it is patterned to further serve as an RPO film during a subsequent silicidation process. The need to form and remove two separate dielectric material layers is obviated. The nitride layer protects the oxide layer to alleviate oxide damage during a pre-silicidation PAI (pre-amorphization implant) process thereby preventing oxide attack during a subsequent HF dip operation and preventing nickel silicide spiking through the attacked oxide layer during silicidation.

Abstract: Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate; and at least one n-channel field effect transistor (NFET) having a gate stack over the substrate. The NFET gate stack comprises an NFET gate stack metal gate layer; a first NFET gate stack silicon layer over the NFET gate stack metal gate layer; a second NFET gate stack silicon layer over a side of the first NFET gate stack silicon layer opposite the NFET gate stack metal gate layer, wherein an interface is defined between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer; and an NFET gate stack silicide region that extends through the interface between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer.

Abstract: A method of manufacturing a semiconductor device includes forming a first conductive film on a semiconductor substrate via a first insulating film; forming a second conductive film on the first conductive film via a second insulating film; patterning the first and the second conductive films and the second insulating film to form a plurality of gate electrodes; filling a third insulating film between the plurality of gate electrodes; exposing an upper portion of the second conductive film by removing the third insulating film; covering surfaces of the exposed upper portion of the second conductive film with fluoride (F) or carbon (C) or oxygen (O); and forming a metal film on an upper surface of the second conductive film; and forming silicide layers on the upper portion of the second conductive films by thermally treating the metal film.

Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening by a metal deposition process employing a target which includes metal and silicon. The metal-silicide layer may then be annealed.

Abstract: A preferred embodiment includes a method of manufacturing a fuse element that includes forming a polysilicon layer over a semiconductor structure, doping the polysilicon layer with carbon or nitrogen, depositing a metal over the polysilicon layer; and annealing the metal and polysilicon layer to form a silicide in an upper portion of the polysilicon layer.

Abstract: Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface.

Abstract: A semiconductor device manufacturing method has conducting first heating processing at a first heating temperature in an inert atmosphere under a first pressure in a first process chamber to silicide an upper part of the source-drain diffusion layer and form a silicide film; conducting second heating processing at a second heating temperature in an oxidizing atmosphere under a second pressure in a second process chamber to selectively oxidize at least a surface of the metal film on the element isolating insulation film and form a metal oxide film; conducting third heating processing at a third heating temperature which is higher than the first heating temperature and the second heating temperature in an atmosphere in a third process chamber to increase a concentration of silicon in the silicide film; and selectively removing the metal oxide film and an unreacted part of the metal film on the element isolating insulation film.

Abstract: A method for fabricating a semiconductor device, includes the steps of (a) forming a metal film containing a precious metal on a substrate having a semiconductor layer containing silicon or on a conductive film containing silicon formed on the substrate, (b) after step (a), heat-treating the substrate to allow the precious metal to react with silicon to form a silicide film containing the precious metal on the substrate or the conductive film, (c) after step (b), forming an oxide film on a portion of the silicide film underlying an unreacted portion of the precious metal using a first chemical solution, and (d) dissolving the unreacted portion of the precious metal using a second chemical solution.

Abstract: A method for fabricating a semiconductor device includes the steps of: (a) forming an alloy film containing a precious metal on a substrate having a semiconductor layer or on a conductive film formed on the substrate; (b) heat-treating the substrate to allow the precious metal to react with silicon forming a silicide film containing the precious metal on the substrate or the conductive film; (c) removing an unreacted portion of the alloy film with a first chemical solution after the step (b); (d) forming a silicon oxide film on the top surface of the silicide film including a portion underlying a residue of the precious metal by exposing the substrate to an oxidative atmosphere; and (e) dissolving the residue of the precious metal with a second chemical solution.

Abstract: A method of forming a buried interconnection includes removing a semiconductor substrate to form a groove in the semiconductor substrate. A metal layer is formed on inner walls of the groove using an electroless deposition technique. A silicidation process is applied to the substrate having the metal layer, thereby forming a metal silicide layer on the inner walls of the groove.

Abstract: A method for forming an interconnect structure includes forming a dielectric layer above a first layer having a conductive region defined therein. An opening is defined in the dielectric layer to expose at least a portion of the conductive region. A metal silicide is formed in the opening to define the interconnect structure. A semiconductor device includes a first layer having a conductive region defined therein, a dielectric layer formed above the first layer, and a metal silicide interconnect structure extending through the dielectric layer to communicate with the conductive region.

Abstract: A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.

Abstract: A method of self-aligned silicidation on structures having high aspect ratios involves depositing a metal oxide film using atomic layer deposition (ALD) and converting the metal oxide film to metal film in order to obtain uniform step coverage. The substrate is then annealed such that the metal in regions directly overlying the patterned and exposed silicon reacts with the silicon to form uniform metal silicide at the desired locations.

Abstract: The present invention discloses a semiconductor device and a manufacturing method thereof which improves its characteristics even though it is miniaturized. According to one aspect of the present invention, it is provided a semiconductor device comprising a first semiconductor element device including a pair of first diffusion layers formed in the semiconductor substrate with a first gate electrode therebetween, and a first conductor layer formed in the first diffusion layer and having an internal stress in a first direction, and a second semiconductor element device including a pair of second diffusion layers formed in the semiconductor substrate with a second gate electrode therebetween, and a second conductor layer formed in the second diffusion layer, having an internal stress in a second direction opposite to the first direction, and constituted of the same element as that of the first conductor layer.

Abstract: The present invention provides a method for forming a transistor on a silicon substrate, the method comprising: providing a substrate comprising: a gate electrode with a liner comprising silicon and oxygen, and with a sidewall spacer, and source and/or drain region(s) in the substrate adjacent to the gate electrode, a layer at least 5 nm thick comprising silicon dioxide covering at least the source and/or drain regions; etching the layer comprising silicon and oxygen from at least the source and/or drain regions; and forming contacts for the source and/or drain region(s), characterized in that the layer comprising silicon and oxygen is etched from the substrate by steps comprising: forming an etchant from a plasma formed from a mixture comprising nitrogen trifluoride and ammonia; exposing the substrate to the etchant; and annealing the substrate.

Abstract: A simple and cost effective method of forming a fully silicided (FUSI) gate of a MOS transistor is disclosed. In one example, the method comprises forming a nitride hardmask overlying a polysilicon gate, forming an S/D silicide in source/drain regions of the transistor, oxidizing a portion of the S/D silicide to form an oxide barrier overlying the S/D silicide in the source/drain regions, removing the nitride hardmask from the polysilicon gate, and forming a gate silicide such as by deposition of a gate silicide metal over the polysilicon gate and the oxide barrier in the source/drain regions to form a fully silicided (FUSI) gate in the transistor. Thus, the oxide barrier protects the source/drain regions from additional silicide formation by the gate silicide metal formed thereafter. The method may further comprise selectively removing the oxide barrier in the source/drain regions after forming the fully silicided (FUSI) gate.

Abstract: Post-laser annealing dopant deactivation is minimized by performing certain low temperature process steps prior to laser annealing.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide.

Abstract: In a multiple gate transistor, the plurality of Fins of the drain or source of the transistor are electrically connected to each other by means of a common contact element, wherein enhanced uniformity of the corresponding contact regions may be accomplished by an enhanced silicidation process sequence. For this purpose, the Fins may be embedded into a dielectric material in which an appropriate contact opening may be formed to expose end faces of the Fins, which may then act as silicidation surface areas.

Abstract: A semiconductor device including silicide layers with different thicknesses corresponding to diffusion layer junction depths, and a method of fabricating the same are provided. According to one aspect, there is provided a semiconductor device comprising a first semiconductor element device and a second semiconductor element device, wherein the first semiconductor element device includes a first gate electrode, first diffusion layers disposed to sandwich the first gate electrode, and having a first junction depth, and a first silicide layer disposed in the first diffusion layers and having a first thickness, and the second semiconductor element device includes a second gate electrode, second diffusion layers disposed to sandwich the second gate electrode, and having a second junction depth greater than the first junction depth, and a second silicide layer disposed in the second diffusion layers and having a second thickness greater than the first thickness.

Abstract: The invention relates to a method for fabricating a layer comprising nickel monosilicide NiSi on a substrate comprising silicon successively comprising the following steps: a) a step of incorporating, on a portion of the thickness of the said substrate comprising silicon, an element selected from W, Ti, Ta, Mo, Cr and mixtures thereof; b) a step of depositing, on the said substrate obtained in step a), a layer of nickel and a layer of an element selected from Pt, Pd, Rh and mixtures thereof or a layer comprising both nickel and an element selected from Pt, Pd, Rh and mixtures thereof; c) a step of heating to a temperature sufficient for obtaining the formation of a layer comprising nickel silicide optionally in the form of nickel monosilicide NiSi; d) a step of incorporating fluorine in the said layer obtained in c); and e) optionally, a step of heating to a sufficient temperature to convert the layer mentioned in d) to a layer comprising nickel silicide entirely in the form of nickel monosilicide NiSi.

Abstract: Removal compositions and processes for removing at least one material layer from a rejected microelectronic device structure having same thereon. The removal composition includes hydrofluoric acid. The composition achieves substantial removal of the material(s) to be removed while not damaging the layers to be retained, for reclaiming, reworking, recycling and/or reuse of said structure.

Abstract: A semiconductor device including a semiconductor substrate, an interface layer formed on the semiconductor substrate including at least 1×1020 atoms/cm3 of S (Sulfur), a metal-semiconductor compound layer formed on the interface layer, the metal-semiconductor compound layer including at least 1×1020 atoms/cm3 of S in the its whole depth, and a metal electrode formed on the metal-semiconductor compound layer.

Abstract: A method of forming a plurality of transistor gates having at least two different work functions includes forming first and second transistor gates over a substrate having different widths, with the first width being narrower than the second width. A material is deposited over the substrate including over the first and second gates. Within an etch chamber, the material is etched from over both the first and second gates to expose conductive material of the first gate and to reduce thickness of the material received over the second gate yet leave the second gate covered by the material. In situ within the etch chamber after the etching, the substrate is subjected to a plasma comprising a metal at a substrate temperature of at least 300° C. to diffuse said metal into the first gate to modify work function of the first gate as compared to work function of the second gate.

Abstract: One inventive aspect relates to a method of controlling the gate electrode in a silicidation process. The method comprises applying a sacrificial cap layer on top of each of at least one gate electrode, each of the at least one gate electrode deposited with a given height on a semiconductor substrate. The method further comprises applying an additional layer of oxide on top of the sacrificial layer. The method further comprises covering with a material the semiconductor substrate provided with the at least one gate electrode having the sacrificial cap layer with the additional oxide layer on top. The method further comprises performing a CMP planarization step. The method further comprises removing at least the material and the additional layer of oxide until on top of each of the at least one gate electrode the sacrificial cap layer is exposed.

Abstract: A method for forming a nickel silicide layer on a MOS device with a low carbon content comprises providing a substrate within an ALD reactor and performing an ALD process cycle to form a nickel layer on the substrate, wherein the ALD process cycle comprises pulsing a nickel precursor into the reactor, purging the reactor after the nickel precursor, pulsing a mixture of hydrogen and silane into the reactor, and purging the reactor after the hydrogen and silane pulse. The ALD process cycle can be repeated until the nickel layer reaches a desired thickness. The silane used in the ALD process functions as a getterer for the advantageous carbon, resulting in a nickel layer that has a low carbon content. The nickel layer may then be annealed to form a nickel silicide layer with a low carbon content.

Abstract: Some embodiments include methods of titanium deposition in which a silicon-containing surface and an electrically insulative surface are both exposed to titanium-containing material, and in which such exposure forms titanium silicide from the silicon-containing surface while not depositing titanium onto the electrically insulative surface. The embodiments may include atomic layer deposition processes, and may include a hydrogen pre-treatment of the silicon-containing surfaces to activate the surfaces for reaction with the titanium-containing material. Some embodiments include methods of titanium deposition in which a semiconductor material surface and an electrically insulative surface are both exposed to titanium-containing material, and in which a titanium-containing film is uniformly deposited across both surfaces.

Abstract: Embodiments relate to a method of manufacturing a transistor having a metal silicide layer. In embodiments, the method may include sequentially forming a gate insulating layer pattern and a gate conductive layer pattern on a semiconductor substrate, forming a first metal silicide layer on the gate conductive layer pattern and a second metal silicide layer on the semiconductor substrate, forming a spacer layer on side-walls of the gate insulating layer pattern and the gate conductive layer pattern, and forming a source/drain region in the semiconductor substrate below the second metal silicide layer by performing ion implantation.

Abstract: To provide a semiconductor device with improved reliability which includes a metal silicide layer formed by a salicide process. After forming gate electrodes, an n+-type semiconductor region, and a p+-type semiconductor region for a source or drain, a Ni1?xPtx alloy film is formed over a semiconductor substrate. The alloy film reacts with the gate electrodes, the n+-type semiconductor region, and the p+-type semiconductor region by a first heat treatment to form a metal silicide layer in a (Ni1?yPty)2Si phase. At this time, the first heat treatment is performed at a heat treatment temperature where a diffusion coefficient of Ni is larger than that of Pt. Further, the first heat treatment is performed such that a reacted part of the alloy film remains at the metal silicide layer. This results in y>x. Then, after removing the unreacted part of the alloy film, the metal silicide layer is further subjected to a second heat treatment to form a metal silicide layer in a Ni1?yPtySi phase.

Abstract: A method for manufacturing an integrated circuit system includes: providing a first material; forming a second material over a first side of the first material; and exposing a second side of the first material to an energy source to form an electrical contact at an interface of the first material and the second material.

Abstract: A semiconductor device includes: a P-type semiconductor layer formed in a surface region of a semiconductor substrate; a first gate insulating film formed on the P-type semiconductor layer; a first gate electrode; and a first source region and a first drain region formed in the P-type semiconductor layer to interpose a region under the first gate electrode in a direction of gate length. The first gate electrode includes: a first silicide film formed on the first gate insulating film and containing nickel silicide having a first composition ratio of nickel to silicon as a main component; a conductive film formed on the first silicide film; and a second silicide film formed on the conductive film and containing nickel silicide having a second composition ratio of nickel to silicon as a main component. The second composition ratio is larger than the first composition ratio.

Abstract: A method comprises forming a gate stack comprising a polysilicon layer, a metal layer and a polysilicon layer over a gate dielectric and substrate. The metal layer is buried inside the gate stack to alloy the silicon and metal at the bottom of the gate. The gate stack is then etched to form a gate. A silicidation is then performed to form a silicide at the bottom of the gate. Optionally, a second metal layer may be formed on top of the gate stack. As such, during silicidation, a silicide may be formed at the top of the gate.

Abstract: Provided is a method for manufacturing a semiconductor device. In the method, a gate oxide layer, a gate polysilicon layer, and a capping oxide layer are sequentially formed on a semiconductor substrate. A photoresist pattern is formed on the capping oxide layer. The capping oxide layer, gate polysilicon layer, and gate oxide layer are sequentially etched using the photoresist pattern as an etch mask. Ions are then implanted into the semiconductor substrate using the photoresist pattern as a mask. A thermal diffusion process is performed to form source/drain regions. The capping oxide layer is removed, and ions are implanted into the gate polysilicon layer. After metal is deposited on the gate polysilicon layer, a silicide is formed.