Abstract: A method of forming a semiconductor structure is disclosed. A multi-layer structure is formed over a substrate. A photoresist stack with a stepped sidewall is formed on the multi-layer structure. A pattern of the photoresist stack is transferred to the multi-layer structure.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes providing a to-be-etched layer; forming an initial mask layer over the to-be-etched layer; forming a patterned structure, on the initial mask layer and exposing a portion of the initial mask layer; forming a barrier layer on a sidewall surface of the patterned structure; using the patterned structure and the barrier layer as a mask, performing an ion doping process on the initial mask layer to form a doped region and an un-doped region between doped regions in the initial mask layer; removing the patterned structure and the barrier layer; and forming a mask layer on a top surface of the to-be-etched layer by removing the un-doped region. The mask layer includes a first opening exposing the top surface of the to-be-etched layer.

Abstract: A method of manufacturing an array substrate is provided, which comprises: forming a first metal layer and an insulating layer in sequence on a base substrate, the insulating layer covering the first metal layer; forming an etch barrier layer on the insulating layer; etching the etching barrier layer and the insulating layer multiple times, wherein an effective blocking area of the etching barrier layer decreases successively in each etching to form a connection hole penetrating the insulating layer, the connection hole includes a plurality of via holes connected in sequence, and a slope angle of a hole wall of each via hole is smaller than a preset slope angle; and forming a second metal layer, the second metal layer being connected to the first metal layer through the connection hole.

Abstract: A semiconductor device includes a plurality of conductive structures arranged on a substrate and spaced apart from each other in a second direction substantially perpendicular to a first direction, in which each of the plurality of conductive structures extends in the first direction. A plurality of contact structures are arranged between the conductive structures in an alternating arrangement and spaced apart from each other in the first direction. A plurality of insulation structures are arranged in a space between the conductive structures and between the contact structures. A plurality of air spacers are arranged between the alternating arrangement of the plurality of conductive structures and the plurality of contact structures, respectively and spaced apart from each other in the first direction.

Abstract: The present disclosure provides an array substrate, a manufacturing method thereof, and a display device. The array substrate includes a base substrate, and a first functional layer and a second functional layer laminated one on another on the base substrate. The first functional layer forms a level-different region on the base substrate, and the second functional layer covers the level-different region. A portion of the first functional layer at the level-different region is provided with a target gradient angle, the target gradient angle is a maximum gradient angle when the second functional layer has a predetermined thickness, and the predetermined thickness is a thickness when a functional requirement of the second functional layer has been met and the second functional layer is not broken at the level-different region.

Abstract: An array substrate, a method for manufacturing the same and a display device are provided. The method includes: providing a base substrate; forming a conductive material thin film on the base substrate; forming a first photoresist layer on a side of the conductive material thin film distal to the base substrate; etching the conductive material thin film by using the first photoresist layer as a mask to obtain a first etched pattern; removing third covering portions of the first photoresist layer to obtain a second photoresist layer; and etching the first etched pattern by using the second photoresist layer as a mask to obtain a gate electrode and a signal line.

Abstract: A manufacturing method for a magnetic head includes the steps of: forming a main pole; forming a spin torque oscillator; and forming a trailing shield. The step of forming the spin torque oscillator includes: a step of forming a layered film; a step of forming an interposition layer; a step of forming a mask; a first etching step of etching a portion of the interposition layer using the mask; a second etching step of etching a portion of the layered film using the mask and the interposition layer as an etching mask; a step of removing the interposition layer and the mask; and a patterning step of patterning the layered film into the spin torque oscillator.

Abstract: A method for making a metal grating is provided. The method includes providing a substrate, applying a metal layer on a surface of the substrate, forming a number of protrusions spaced from each other on a surface of the metal layer, wherein each of the number of protrusions is made of two resist layer, one of the two resist layers being made of silicone oligomer, etching the surface of the metal layer exposed out of the number of protrusions using a physical etching gas and a reactive etching gas, and dissolving the number of protrusions on the surface of the metal layer.

Abstract: The present invention has an object to perform a peeling treatment in a short time. Peeling is performed while a peeling layer is exposed to an atmosphere of an etching gas. Alternatively, peeling is performed while an etching gas for a peeling layer is blown to the peeling layer in an atmosphere of an etching gas. Specifically, an etching gas is blown to a part to be peeled while a layer to be peeled is torn off from a substrate. Alternatively, peeling is performed in an etchant for a peeling layer while supplying an etchant to the peeling layer.

Abstract: A spacer etching process produces ultra-narrow conductive lines in a plurality of semiconductor dice. Trenches are formed in a first dielectric then a sacrificial film is deposited onto the first dielectric and the trench surfaces formed therein. Planar sacrificial film is removed from the face of the first dielectric and bottom of the trenches, leaving only sacrificial films on the trench walls. A gap between the sacrificial films on the trench walls is filled in with a second dielectric. A portion of the second dielectric is removed to expose tops of the sacrificial films. The sacrificial films are removed leaving ultra-thin gaps that are filled in with a conductive material. The tops of the conductive material in the gaps are exposed to create “fence conductors.” Portions of the fence conductors and surrounding insulating materials are removed at appropriate locations to produce desired conductor patterns comprising isolated fence conductors.

Abstract: There is provided a dry film photoresist including a substrate layer constituted by a certain substrate, a resist layer disposed over the substrate layer, the resist layer including a plurality of layers, and a protective film layer disposed over the resist layer, the protective film layer protecting the resist layer. A photosensitive layer is positioned on a side of the substrate layer of the resist layer, the photosensitive layer having a dissolution rate to a certain developer that decreases by being exposed to light, and a non-photosensitive layer is positioned on a side of the protective film layer of the resist layer, the non-photosensitive layer being soluble to the developer. A dissolution rate of the non-photosensitive layer to the developer is higher than a dissolution rate of an unexposed portion in the photosensitive layer to the developer.

Abstract: An implantable medical device formed from one or more layers of thin film polymer is assembled by providing by adhesively securely one or more polymer coupons on individual rigid backings. After each coupon is shaped or components mounted to the coupon, the coupons are bonded together. The adhesive is dissolved to remove the device from the backing or backings to which it is attached.

Abstract: The present disclosure provides semiconductor packaging techniques that form a substrate using metal and insulating materials. The substrate includes a first surface that is bonded to a semiconductor device and a second surface that is bonded to a printed circuit board. The substrate is formed using several techniques that minimize the amount of mask levels used to form the substrate. For example, a metal substrate is patterned to form a three dimensional pattern on the surface. A dielectric material is deposited on the three dimensional pattern. Using several patterning and polishing embodiments described herein, the metal/dielectric substrate is patterned and polished to form a substantially flush surface that is bonded to the semiconductor device. In one embodiment, the top surface of the metal/dielectric substrate is patterned to expose the underlying metal substrate and the bottom surface of the metal substrate is polished to be substantially flush with the dielectric material.

Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

Abstract: The present apparatus and method are configured to remove challenging polymer films and structures from semiconductor wafers. This technique involves the use of a double soak and spray sequence with unique parameters and can be varied depending upon the application. The initial immersion step is used to initiate the swelling and dissolution of the polymer. The first spray step may include a high pressure needle to pierce through the top layer allowing more solvent to penetrate in the subsequent soak process. The second immersion can then penetrate further and faster allowing substantial penetration of the polymer by the solvent. The final high pressure spray proceeds to remove all of the polymer coating. The process ends with a final rinse and dry sequence.

Abstract: On a surface of a substrate (3) on which surface a vapor-deposited film is to be formed, a photoresist (13) is formed so as to have an opening in a sealing region including a display region (R1) which sealing region is formed by a sealing resin (11) of a frame shape. Then, luminescent layers (8R, 8G, and 8B) having a striped pattern are formed. Subsequently, the photoresist (13) is removed with the use of an exfoliative solution so as to form the luminescent layers (8R, 8G, and 8B) patterned with high definition.

Abstract: Methods for depositing nanomaterial onto a substrate are disclosed. Also disclosed are compositions useful for depositing nanomaterial, methods of making devices including nanomaterials, and a system and devices useful for depositing nanomaterials.

Abstract: A method of fabricating a semiconductor device includes forming switching devices on a substrate. A lower structure is formed in the substrate having the switching devices. A lower conductive layer is formed on the lower structure. Sacrificial mask patterns are formed on the lower conductive layer. Lower conductive patterns are formed by etching the lower conductive layer using the sacrificial mask patterns as an etch mask. An interlayer insulating layer is formed on the substrate having the lower conductive patterns. Interlayer insulating patterns are formed by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed. Openings exposing the lower conductive patterns are formed by removing the exposed sacrificial mask patterns. Upper conductive patterns self-aligned with the lower conductive patterns are formed in the openings.

Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

Abstract: A method for making a mask for semiconductor manufacturing. The method includes providing a base layer, forming a conductive layer on the base layer, and forming a photoresist layer on the conductive layer. Additionally, the method includes exposing selectively the photoresist layer to an energy illumination, developing the photoresist layer by removing a first portion of the photoresist layer, and depositing a metal layer by an electroforming process. The electroforming process includes submerging the conductive layer into a chemical bath, and applying a deposition voltage across a negative electrode and a positive electrode. Moreover, the method includes removing a second portion of the photoresist layer, and removing a first portion of the conductive layer.

Abstract: Described are three-dimensional stacked semiconductor structures having one or more vertical interconnects. Vertical stacking relies on vertical interconnects and wafer bonding using a patternable polymer. The polymer is preferably lithographically patternable and photosensitive. Curing of the polymer is preselected from about 35% to up to about 100%, depending on a desired outcome. When fabricated, such vertically stacked structures include electrical interconnects provided by solder reflow. Solder reflow temperature is bounded by a curing and glass transition temperatures of a polymer used for bonding.

Abstract: For semiconductor chips using thin film technology, an active layer sequence is applied to a growth substrate, on which a reflective electrically conductive contact material layer is then formed. The active layer sequence is patterned to form active layer stacks, and reflective electrically conductive contact material layer is patterned to be located on each active layer stack. Then, a flexible, electrically conductive foil is applied to the contact material layers as an auxiliary carrier layer, and the growth substrate is removed.

Abstract: A method for forming a non-volatile memory device includes providing a substrate having a surface region, forming a first wiring structure overlying the surface region, depositing a first dielectric material overlying the first wiring structure, forming a via opening in the first dielectric material to expose a portion of the first wiring structure, while maintaining a portion of the first dielectric material, forming a layer of resistive switching material comprising silicon, within the via opening, forming a silver material overlying the layer of resistive switching material and the portion of the first dielectric material, forming a diffusion barrier layer overlying the silver material, and selectively removing a portion of the silver material and a portion of the diffusion barrier layer overlying the portion of the first dielectric material while maintaining a portion of the silver material and a portion of the diffusion barrier material overlying the layer of silicon material.

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method comprises following steps. A substrate is provided. A sacrificial layer is formed on the substrate. The sacrificial layer is patterned to develop a first opening and a second opening. The first opening corresponds to an exposed portion of the substrate and the second opening corresponds to an unexposed portion of the substrate. A heat procedure is performed. A target material is formed on the exposed portion of the substrate and a rest part of the sacrificial layer. The rest part of the sacrificial layer and parts of the target material on the rest part of the sacrificial layer are removed. A predetermined patterned target material is obtained.

Abstract: One object of the present invention is to provide a method for producing a thick film metal electrode that is able to form a positive-negative reverse type resist, which has a thickness of 7 ?m or more and excellent in-plane uniformity, on the circuit element formed on the silicon carbide substrate, and a method for producing a thick film resist, and the present invention provides a method for producing a thick film resist wherein a first positive-negative reverse type resist having a first viscosity is formed on an upper surface of a circuit element layer which is treated with HMDS, and a second positive-negative reverse type resist having a second viscosity, which is larger than the first viscosity, on the first positive-negative reverse type resist such that a total thickness of the first and second positive-negative reverse type resists constituting a thick film resist be 7 ?m or more.

Abstract: A method includes: forming a gate electrode and a gate line at a pixel part of a first substrate through a first masking process; forming a gate insulation film; forming an active pattern and source/drain electrodes and forming a data line crossing the gate line through a second masking process; forming a passivation layer; forming a photosensitive film pattern including a first pattern and a second pattern through a third masking process; selectively removing a portion of the passivation layer to form a first contact hole exposing a portion of the drain electrode; removing portions of the first and second patterns to remove the second pattern and form a third pattern; removing the third pattern and a conductive film on the third pattern to form a pixel electrode electrically connected with the drain electrode via the first contact hole; and attaching the first and second substrates.

Abstract: A method of manufacturing, at a reduced cost, a semiconductor device assembly and a semiconductor device, having a conductive support which is not eroded by an etchant for a lift-off layer even when the lift-off layer is made of a material for which no suitable selective etching solution has been found is provided. In the method of manufacturing the semiconductor device assembly, a plating step of forming a conductive support is carried out such that a first metal which is dissolved with an etchant is encapsulated in second metal which are not dissolved with the etchant, and through-holes for supplying etchant are formed in the second metal.

Abstract: A method of forming conductive pattern is provided. A seeding layer is formed on an underlayer. By using an energy ray, an irradiation treatment is performed on a portion of a surface of the seeding layer. The seeding layer thus includes a plurality of irradiated regions and a plurality of unirradiated regions. A conversion treatment is performed on the irradiated regions of the seeding layer. A selective growth process is performed, so as to form a conductive pattern on each unirradiated region of the seeding layer. The irradiated regions of the seeding layer are removed, so that the conductive patterns are insulated from each other.

Abstract: The present invention provides a semiconductor light-emitting element comprising an electrode part excellent in ohmic contact and capable of emitting light from the whole surface. An electrode layer placed on the light-extraction side comprises a metal part and plural openings. The metal part is so continuous that any pair of point-positions in the part is continuously connected without breaks, and the metal part in 95% or more of the whole area continues linearly without breaks by the openings in a straight distance of not more than ? of the wavelength of light emitted from an active layer. The average opening diameter is of 10 nm to ? of the wavelength of emitted light. The electrode layer has a thickness of 10 nm to 200 nm, and is in good ohmic contact with a semiconductor layer.

Abstract: Composite films comprising two-dimensional hole arrays, and related methods of preparing hole arrays.

Abstract: A method of forming conductive pattern is provided. A seeding layer is formed on an underlayer. By using an energy ray, an irradiation treatment is performed on a portion of a surface of the seeding layer. The seeding layer thus includes a plurality of irradiated regions and a plurality of unirradiated regions. A conversion treatment is performed on the irradiated regions of the seeding layer. A selective growth process is performed, so as to form a conductive pattern on each unirradiated region of the seeding layer. The irradiated regions of the seeding layer are removed, so that the conductive patterns are insulated from each other.

Abstract: A method of forming a pattern includes forming a photoresist pattern on a substrate, forming a first material layer on substantially an entire surface of the substrate including the photoresist pattern, heat-treating the substrate including the first material layer and the photoresist pattern, and forming the pattern by removing the photoresist pattern and the portion of the first material layer on the photoresist pattern. A method of manufacturing an array substrate includes forming a pixel region bounded by gate and data lines, and a thin film transistor; an insulating layer is selectively removed to form a passivation layer using a photoresist pattern as an etching mask; a transparent conductive layer is formed on substantially the entire substrate, and the substrate is heat treated. The photoresist pattern and the portion of the transparent conductive layer on the photoresist pattern are removed by a stripping material.

Abstract: A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.

Abstract: A nonvolatile semiconductor memory device includes: a substrate; a stacked body with a plurality of dielectric films and electrode films alternately stacked therein, the stacked body being provided on the substrate and having a step in its end portion for each of the electrode films; an interlayer dielectric film burying the end portion of the stacked body; a plurality of semiconductor pillars extending in the stacking direction of the stacked body and penetrating through a center portion of the stacked body; a charge storage layer provided between one of the electrode films and one of the semiconductor pillars; and a plug buried in the interlayer dielectric film and connected to a portion of each of the electrode films constituting the step, a portion of each of the dielectric films in the center portion having a larger thickness than a portion of each of the dielectric films in the end portion.

Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

Abstract: A method for applying a predetermined structure of a structural material to a semiconductor element. The method includes the following steps: A) partially covering a surface of the semiconductor element with a masking layer, B) applying a film of a structural material to the masking layer and to the surface of the semiconductor element in the zones that are devoid of the masking layer and C) removing the masking layer together with the structural material present on the masking layer. The method according to the invention provides that between process steps B and C, the film of structural material is partially removed in a process step B2.

Abstract: A method for producing planar extended electrodes with nanoscale spacings that exhibit very large SERS signals, with each nanoscale gap having one well-defined hot spot. The resulting highly sensitive substrate has extended metal electrodes separated by a nanoscale gap. The electrodes act as optical antennas to enhance dramatically the local electromagnetic field for purposes of spectroscopy or nonlinear optics. SERS response is consistent with a very small number of molecules in the hotspot, showing blinking and wandering of Raman lines. Sensitivity is sufficiently high that SERS from physisorbed atmospheric contaminants may be detected after minutes of exposure to ambient conditions.

Abstract: A thin film patterning method comprising: depositing a first thin film and applying a photoresist layer on the first thin film; exposing and developing the photoresist layer to define first, second and third regions, wherein the photoresist layer in the first region is thicker than that in the second region, and no photoresist layer is left in the third region; over-etching to remove the first thin film in the third region and form an over-etched region in the peripheral region of the first region; removing a part of the photoresist layer to expose the first thin film in the second region; depositing a second thin film so that the first thin film contacts the second thin film in the second region; and lifting off the photoresist layer to remove the second thin film in the first region and exposing the substrate in the over-etched region of the first region.

Abstract: A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

Abstract: A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

Abstract: A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

Abstract: A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

Abstract: A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.

Abstract: A semiconductor component has a substrate and a projecting electrode on the substrate. The projecting electrode is configured suitably for electrically and mechanically connecting the semiconductor component to an external substrate. Furthermore, the projecting electrode is formed by a one-dimensional or two-dimensional array of projecting sub-electrodes, which are separated from each other by an electrically insulating fluid beginning from a substrate surface. The semiconductor component has an improved projecting-electrode. It provides the projecting electrode with a sub-structure, which achieves sufficient flexibility without introducing much constructive complexity and processing complexity during fabrication.

Abstract: A method for fabricating optical devices on a reusable handle substrate. The method includes providing a handle substrate having a surface region. The method also includes forming a plurality of optical device using at least an epitaxial growth process overlying the surface region and then releasing the handle substrate from the plurality of optical devices. The method reuses the handle substrate for another fabrication process.

Abstract: A method of manufacturing an array type semiconductor laser device. The method includes forming first and second electrodes on lower and upper surfaces of a wafer comprising a plurality of semiconductor laser arrays having a plurality of laser emission regions, and forming a metal bonding layer on the second electrode of the wafer. The method also includes dicing the wafer into the semiconductor laser arrays and mounting each of the individually separated semiconductor laser arrays on a base with the surface of the metal bonding layer in contact with the base. The method further includes melting the metal bonding layer to fix the mounted semiconductor laser array on the base.

Abstract: A semiconductor device manufacturing method includes: forming a core pattern on a foundation film, the core pattern containing a material generating acid by light exposure; selectively exposing part of the core pattern except an longitudinal end portion; supplying a mask material onto the foundation film so as to cover the core pattern, the mask material being crosslinkable upon supply acid from the core pattern; etching back the mask material to expose an upper surface of the core pattern and remove a portion of the mask material formed on the end portion of the core pattern, thereby leaving a mask material side wall portion formed on a side wall of the core pattern; and removing the core pattern and processing the foundation film by using the mask material sidewall portion left on the foundation film as a mask.

Abstract: A method for fabricating a semiconductor device includes the steps of (a) forming a plasma of a gas having carbon and fluorine, and forming an internal insulation film provided with a fluorine-doped carbon film formed on a substrate using the plasma; (b) forming a metal film on the internal insulation film; (c) etching the metal film according to a pattern to form a hard mask; (d) forming a concave part in the fluorine-doped carbon film by etching the fluorine-doped carbon film using the hard mask; (e) forming a film formation of a wiring material on the substrate for filling the concave part with the wiring material; (f) removing an excess part of the wiring material and the hard mask on the fluorine-doped carbon film for exposing a surface of the fluorine-doped carbon film; and (g) removing an oxide formed on the surface of the fluorine-doped film.

Abstract: An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer.

Abstract: A semiconductor device having good switching characteristics even metallic CNTs are included and a manufacturing method thereof are provided. The semiconductor device includes a source electrode; a drain electrode; and a channel layer formed between the source electrode and the drain electrode and including a carbon nanotube group. The carbon nanotube group includes conductive carbon nanotubes having a characteristic of a conductive material and semiconductive carbon nanotubes having a characteristic of a semiconductive material. The density of the carbon nanotube group is the density where the source electrode and the drain electrode are connected to each other through all of the carbon nanotube group and not connected to each other only through the conductive carbon nanotubes.