Abstract: Fin-defining spacers are formed on an array of mandrel structure. Mask material portions can be directionally deposited on fin-defining spacers located on one side of each mandrel structure, while not deposited on the other side. A photoresist layer is subsequently applied and patterned to form an opening, of which the overlay tolerance increases by a pitch of fin-defining spacers due to the mask material portions. Alternately, a conformal silicon oxide layer can be deposited on fin-defining spacers and structure-damaging ion implantation is performed only on fin-defining spacers located on one side of each mandrel structure. A photoresist layer is subsequently applied and patterned to form an opening, from which a damaged silicon oxide portion and an underlying fin-defining spacer are removed, while undamaged silicon oxide portions are not removed. An array of semiconductor fins including a vacancy can be formed by transferring the pattern into a semiconductor layer.

Abstract: A method for forming etched features in a low-k dielectric layer disposed below the photoresist mask in a plasma processing chamber is provided. Features are etched into the low-k dielectric layer through the photoresist mask. The photoresist mask is stripped, wherein the stripping comprising at least one cycle, wherein each cycle comprises a fluorocarbon stripping phase, comprising flowing a fluorocarbon stripping gas into the plasma processing chamber, forming a plasma from the fluorocarbon stripping gas, and stopping the flow of the fluorocarbon stripping gas into the plasma processing chamber and a reduced fluorocarbon stripping phase, comprising flowing a reduced fluorocarbon stripping gas that has a lower fluorocarbon flow rate than the fluorocarbon stripping gas into the plasma processing chamber, forming the plasma from the reduced fluorocarbon stripping gas, and stopping the flow of the reduced fluorocarbon stripping gas.

Abstract: A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the another patterned line to the substrate.

Abstract: A method for etching features in a silicon layer disposed below a mask in a plasma processing chamber a plurality of cycles is provided. A deposition phase forming a deposition on the silicon layer in the plasma processing chamber is provided comprising providing a deposition gas into the plasma processing chamber wherein the deposition gas comprises a halogen containing etchant component and a fluorocarbon deposition component, forming the deposition gas into a plasma, which provides a net deposition on the silicon layer, and stopping the flow of the deposition gas. A silicon etch phase is provided, comprising providing a silicon etch gas into the plasma processing chamber that is different than the deposition gas, forming the silicon etch gas into a plasma to etch the silicon layer, and stopping the flow of the silicon etch gas.

Abstract: Methods for forming a semiconductor device include forming self-aligned trenches, in which a first set of trenches is used to align a second set of trenches. Methods taught herein can be used as a pitch doubling technique, and may therefore enhance device integration. Further, employing a very thin CMP stop layer, and recessing surrounding materials by about an equal amount to the thickness of the CMP stop layer, provides improved planarity at the surface of the device.

Abstract: Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.

Abstract: A gas distribution system for supplying different gas compositions to a chamber, such as a plasma processing chamber of a plasma processing apparatus is provided. The gas distribution system can include a gas supply section, a flow control section and a switching section. The gas supply section provides first and second gases, typically gas mixtures, to the flow control section, which controls the flows of the first and second gases to the chamber. The chamber can include multiple zones, and the flow control section can supply the first and second gases to the multiple zones at desired flow ratios of the gases. The gas distribution system can continuously supply the first and second gases to the switching section and the switching section is operable to switch the flows of the first and second gases, such that one of the first and second process gases is supplied to the chamber while the other of the first and second gases is supplied to a by-pass line, and then to switch the gas flows.

Abstract: Embodiment of the present invention provides a method of forming a semiconductor device in a sidewall image transfer process with multiple critical dimensions. The method includes forming a multi-level dielectric layer over a plurality of mandrels, the multi-level dielectric layer having a plurality of regions covering the plurality of mandrels, the plurality of regions of the multi-level dielectric layer having different thicknesses; etching the plurality of regions of the multi-level dielectric layer into spacers by applying a directional etching process, the spacers being formed next to sidewalls of the plurality of mandrels and having different widths corresponding to the different thicknesses of the plurality of regions of the multi-level dielectric layer; removing the plurality of mandrels in-between the spacers; and transferring bottom images of the spacers into one or more layers underneath the spacers.

Abstract: An apparatus for forming spacers is provided. A plasma processing chamber is provided, comprising a chamber wall, a substrate support, a pressure regulator, an antenna, a bias electrode, a gas inlet, and a gas outlet. A gas source comprises an oxygen gas source and an anisotropic etch gas source. A controller comprises a processor and computer readable media. The computer readable media comprises computer readable code for placing a substrate of the plurality of substrates in a plasma etch chamber, computer readable code for providing a plasma oxidation treatment to form a silicon oxide coating over the spacer layer, computer readable code for sputtering silicon to form silicon oxide with the oxygen plasma, computer readable code for providing an anisotropic main etch, computer readable code for etching the spacer layer, computer readable code for removing the substrate from the plasma etch chamber after etching the spacer layer.

Abstract: A tungsten film forming method for forming a tungsten film on a surface of a substrate while heating the substrate in a depressurized atmosphere in a processing chamber includes forming an initial tungsten film for tungsten nucleation on the surface of the substrate by alternately repeating a supply of WF6 gas which is raw material of tungsten and a supply of H2 gas which is a reducing gas in the processing chamber while performing a purge in the processing chamber between the supplies of the WF6 gas and the H2 gas and adsorbing a gas containing a material for nucleation onto a surface of the initial tungsten film. The film forming method further includes depositing a crystallinity blocking tungsten film for blocking crystallinity of the initial tungsten film by supplying the WF6 gas and the H2 gas into the processing chamber.

Abstract: In one example, the method includes forming a hard mask layer above a semiconducting substrate, forming a patterned spacer mask layer above the hard mask layer, wherein the patterned spacer mask layer is comprised of a plurality of first spacers, second spacers and third spacers, and performing a first etching process on the hard mask layer through the patterned spacer mask layer to define a patterned hard mask layer. The method also includes performing a second etching process through the patterned hard mask layer to define a plurality of first fins, second fins and third fins in the substrate, wherein the first fins have a width that corresponds approximately to a width of the first spacers, the second fins have a width that corresponds approximately to a width of the second spacers, and the third fins have a width that corresponds approximately to a width of the third spacers.

Abstract: In a semiconductor device manufacturing method, on a film to be processed, a mask material film is formed which has pattern openings for a plurality of contact patterns and connection openings for connecting adjacent pattern openings in such a manner that the connection between them is constricted in the middle. Then, a sidewall film is formed on the sidewalls of the individual openings in the mask material film, thereby not only making the diameter of the pattern openings smaller but also separating adjacent pattern openings. Then, the film to be processed is selectively etched with the mask material film and sidewall film as a mask, thereby making contact holes.

Abstract: A semiconducting device with a dual sidewall spacer and method of forming are provided. The method includes: depositing a first spacer layer over a patterned structure, the first spacer layer having a seam propagating through a thickness of the first spacer layer near an interface region of a surface of the substrate and a sidewall of the patterned structure, etching the first spacer layer to form a residual spacer at the interface region, where the residual spacer coats less than the entirety of the sidewall of the patterned structure, depositing a second spacer layer on the residual spacer and on the sidewall of the patterned structure not coated by the residual spacer, the second spacer layer being seam-free on the seam of the residual spacer, and etching the second spacer layer to form a second spacer coating the residual spacer and coating the sidewall of the patterned structure not coated by the residual spacer.

Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n?2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n?1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n?1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.

Abstract: A substrate processing method that processes a substrate including a processing target layer, an intermediate layer, and a mask layer as stacked in that order. The intermediate layer includes an Si-ARC (Si-containing Anti-Reflection Coating) film and the mask layer has an opening exposing a part of the Si-ARC. The substrate processing method includes a shrink etching step during which an opening width reduction process and an etching process are performed concurrently. In the opening width reduction process, deposits are formed on a sidewall surface of the opening of the mask layer by a plasma generated from a gaseous mixture of an anisotropic etching gas and one of a depositive gas and H2 gas. And in the etching process, the Si-ARC film forming a bottom portion of the opening are etched.

Abstract: A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch. A dielectric material layer is conformally deposited and planarized. The dielectric material layer is etched employing an anisotropic etch that is selective to the first hard mask portion to form a dielectric material portion that laterally surrounds the first hard mask portion. After removal of the second and first hard mask portions, the semiconductor material layer is etched employing the dielectric material portion as an etch mask. Optionally, portions of the semiconductor material layer underneath the first and second hard mask portions can be undercut at a periphery.

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. Self-aligned assist pattern (SAP) is derived from original design layout in an automated manner using geometric Boolean operations based on some predefined design rules, and are included in the mask layout for efficient self-alignment of various sub-layouts of the target pattern during a multiple patterning lithography process. SAP can be of any shape and size, and can have continuous features (e.g., a ring), or discontinuous (e.g., bars not connected to each other) features. An end-to-end multiple patterning lithography using spacer and SAP may use positive tone lithography, and/or negative tone lithography for line and/or space printing.

Abstract: A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask. An epitaxy step is performed to grow a semiconductor material in the second plurality of trenches.

Abstract: A method for sidewall spacer line doubling uses thermal atomic layer deposition (ALD) of a titanium oxide (TiOx) spacer layer. A hardmask layer is deposited on a suitable substrate. A mandrel layer of diamond-like carbon (DLC) is deposited on the hardmask layer and patterned into stripes with tops and sidewalls. A layer of TiOx is deposited, by thermal ALD without the assistance of plasma or ozone, on the tops and sidewalls of the mandrel stripes. Thermal ALD of the TiO2, without energy assistance by plasma or ozone, has been found to cause no damage to the DLC mandrel stripes. After removal of the TiOx from the tops of the mandrel stripes and removal of the mandrel stripes, stripes of TiO2 are left on the hardmask layer and may be used as an etch mask to transfer the pattern into the hardmask layer.

Abstract: Some embodiments include methods of forming semiconductor constructions in which a semiconductor material sidewall is along an opening, a protective organic material is over at least one semiconductor material surface, and the semiconductor material sidewall and protective organic material are both exposed to an etch utilizing at least one fluorine-containing composition. The etch is selective for the semiconductor material relative to the organic material, and reduces sharpness of at least one projection along the semiconductor material sidewall. In some embodiments, the opening is a through wafer opening, and subsequent processing forms one or more materials within such through wafer opening to form a through wafer interconnect. In some embodiments, the opening extends to a sensor array, and the protective organic material is comprised by a microlens system over the sensor array. Subsequent processing may form a macrolens structure across the opening.

Abstract: A method may include forming first hard mask patterns and second hard mask patterns extending in a first direction and repeatedly and alternately arranged on a lower layer, forming third mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the third mask patterns to form first openings, forming filling patterns filling the first openings and gap regions between the third mask patterns, forming spacers on both sidewalls of each of the filling patterns, after removing the third mask patterns, and etching the second hard mask patterns using the filling patterns and the spacers to form second openings.

Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

Abstract: A method for fabricating a semiconductor device includes etching a substrate to form trenches that separate active regions, forming an insulation layer having an opening to open a portion of a sidewall of each active region, forming a silicon layer pattern to gap-fill a portion of each trench and cover the opening in the insulation layer, forming a metal layer over the silicon layer pattern, and forming a metal silicide layer as buried bit lines, where the metal silicide layer is formed when the metal layer reacts with the silicon layer pattern.

Abstract: Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers have substantially straight inner sidewalls and curved outer sidewalls. An augmentation material is formed on the plurality of spacers such that the inner or the outer sidewalls of the spacers are selectively expanded. The augmentation material can bridge the upper portions of pairs of neighboring inner sidewalls to limit deposition between the inner sidewalls. The augmentation material is selectively etched to form a pattern of augmented spacers having a desired augmentation of the inner or outer sidewalls. The pattern of augmented spacers can then be transferred to the substrate through a series of selective etches such that features formed in the substrate achieve a desired pitch.

Abstract: A method of etching a silicon layer through a patterned mask is provided. The method uses an etch chamber in which the silicon layer is placed. The method includes (a) providing the silicon layer having the patterned mask formed thereon, (b) providing an etch gas comprising a fluorine containing gas and an oxygen and hydrogen containing gas into the etch chamber in which the silicon layer has been placed, (c) generating a plasma from the etch gas, (d) etching features into the silicon layer through the patterned mask using the plasma, and (e) stopping the etch gas. The oxygen and hydrogen containing gas contains water vapor.

Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

Abstract: A method for etching features into a silicon substrate disposed below a mask in a plasma processing chamber is provided. The silicon substrate is etched through the mask comprising a plurality of cycles, wherein each cycle comprises a sidewall deposition phase and an etch phase. The sidewall deposition phase comprises providing a flow of sidewall inorganic deposition phase gas comprising a silicon containing compound gas and at least one of oxygen, nitrogen or NOx, into the plasma processing chamber, forming a plasma from the sidewall deposition phase gas in the plasma processing chamber, and stopping the flow of the sidewall deposition gas into the plasma processing chamber. The etch phase comprises, providing a flow of an etching gas comprising a halogen component, forming a plasma from the etching gas in the plasma processing chamber, and stopping the flow of the etching gas.

Abstract: A manufacturing method of a tip type probe includes the steps of: forming on a substrate an etching mask of a shape similar to a shape of a top surface of a truncated pyramid; forming the truncated pyramid by subjecting the substrate to isotropic etching using the etching mask as a mask member; stopping the isotropic etching when an area of the top surface reaches an area capable of generating near-field light; and forming a metal film on at least some of the side surfaces of the truncated pyramid by allowing film forming particles to enter into a space between the etching mask and the side surfaces and adhere onto the truncated pyramid. The directivity of the film forming particles is controlled so that the metal film has a thickness that is reduced gradually from a bottom of the truncated pyramid toward the top surface.

Abstract: Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no greater than about 1000° C., and in which an interface between the silicon dioxide and the silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. Some embodiments include methods of forming transistors in which a trench is formed to extend into monocrystalline silicon. Silicon dioxide is formed along multiple crystallographic planes along an interior of the trench utilizing a first treatment temperature of no greater than about 1000° C., and an interface between the silicon dioxide and the monocrystalline silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. A transistor gate is formed within the trench, and a pair of source/drain regions is formed within the monocrystalline silicon adjacent the transistor gate. Some embodiments include DRAM cells.

Abstract: A method for fabricating a semiconductor device is provided, the method includes forming a double trench including a first trench and a second trench formed below the first trench and having surfaces covered with insulation layers, and removing portions of the insulation layers to form a side contact exposing one sidewall of the second trench.

Abstract: A substrate processing method that forms an opening, which has a size that fills the need for downsizing a semiconductor device and is to be transferred to an amorphous carbon film, in a photoresist film of a substrate to be processed. Deposit is accumulated on a side wall surface of the opening in the photoresist film using plasma produced from a deposition gas having a gas attachment coefficient S of 0.1 to 1.0 so as to reduce the opening width of the opening.

Abstract: Methods for fabricating sub-lithographic, nanoscale microchannels utilizing an aqueous emulsion of an amphiphilic agent and a water-soluble, hydrogel-forming polymer, and films and devices formed from these methods are provided.

Abstract: Techniques disclosed herein include systems and methods for an aspect ratio dependent deposition process that improves gate spacer profile, reduces fin loss, and also reduces hardmask loss in a FinFET or other transistor scheme. Techniques include depositing an aspect ratio dependent protective layer to help tune profile of a structure during fabrication. Plasma and process gas parameters are tuned such that more polymer can collect on surfaces of a structure that are visible to the plasma. For example, upper portions of structures can collect more polymer as compared to lower portions of structures. The variable thickness of the protection layer enables selective portions of spacer material to be removed while other portions are protected.

Abstract: A method for manufacturing a silicon structure according to the present invention includes, in a so-called dry-etching process wherein gas-switching is employed, the steps of: etching a portion in the silicon region at a highest etching rate under a high-rate etching condition such that the portion does not reach the etch stop layer; subsequently etching under a transition etching condition in which an etching rate is decreased with time from the highest etching rate in the high-rate etching condition; and thereafter, etching the silicon region under a low-rate etching condition of a lowest etching rate in the transition etching condition.

Abstract: A method for fabricating a semiconductor device includes etching a substrate to form a plurality of bodies isolated by a first trench, forming a buried bit line gap-filling a portion of the first trench, etching the top portions of the bodies to form a plurality of pillars isolated by a plurality of second trenches extending across the first trench, forming a passivation layer gap-filling a portion of the second trenches, forming an isolation layer that divides each of the second trenches into isolation trenches over the passivation layer, and filling a portion of the isolation trenches to form a buried word line extending in a direction crossing over the buried bit line.

Abstract: Metal contacts are formed within a string overhead area using a double patterning technology (DPT) process thereby allowing for the reduction of a string overhead area and a concomitant reduction in the chip size of a semiconductor device. A first mask pattern is formed by etching a first mask layer, the first mask pattern including a first opening formed in a cell region and a first hole formed in a peripheral region. A first sacrificial pattern is formed on the first mask pattern and the exposed first insulating layer of the cell region using a double patterning technology process. Contact holes are formed by exposing the target layer by etching the first insulating layer using the first mask pattern and the first sacrificial pattern as an etch mask. Metal contacts are then formed in the contact holes.

Abstract: A method of forming an embedded film comprises depositing a first layer on a second layer that is disposed on a substrate and includes a material different from materials included in the first layer, forming an aperture through the first layer and into the second layer, the aperture having a side surface that includes an exposed portion of the first layer and an exposed portion of the second layer, bringing a material that includes organic molecules into contact with the exposed portion of the first layer and the exposed portion of the second layer to form a monomolecular film that covers the side surface, and forming the embedded film in the aperture with a material having a high enough affinity to the monomolecular film to substantially fill the aperture.

Abstract: A photo mask for exposing according to an embodiment includes a mark pattern arranged in a mark region that is different from an effective region to form a semiconductor device; and a regular pattern arranged in the mark region and around the mark pattern and smaller than the mark pattern in size and pitch.

Abstract: A method for performing a spacer etch process is described. The method includes providing a gate structure on a substrate having a low-k spacer material conformally applied over the gate structure, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a spacer protection layer on an exposed surface of said spacer material, and performing one or more etching processes to selectively and anisotropically remove the spacer protection layer and the spacer material to leave behind the sidewall spacer on the sidewall of the gate structure, wherein, while being partly or fully consumed by the one or more etching processes, the spacer protection layer exhibits a reduced variation in composition and/or dielectric constant.

Abstract: Provided are methods of forming field effect transistors. The method includes preparing a substrate with a first region and a second region, forming fin portions on the first and second regions, each of the fin portions protruding from the substrate and having a first width, forming a first mask pattern to expose the fin portions on the first region and cover the fin portions on the second region, and changing widths of the fin portions provided on the first region.

Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a SiOCl-containing layer on an exposed surface of the spacer material to form a spacer protection layer.

Abstract: Methods of fabricating complementary metal-oxide-semiconductor (CMOS) imagers for backside illumination are disclosed. In one embodiment, the method may include forming at a front side of a substrate a plurality of high aspect ratio trenches having a predetermined trench depth, and forming at the front side of the substrate a plurality of photodiodes, where each photodiode is adjacent at least one trench. The method may further include forming an oxide layer on inner walls of each trench, removing the oxide layer, filling each trench with a highly doped material, and thinning the substrate from a back side opposite the front side to a predetermined final substrate thickness. In some embodiments, the substrate may have a predetermined doping profile, such as a graded doping profile, that provides a built-in electric field suitable to guide the flow of photogenerated minority carriers towards the front side.

Abstract: A test probe head for probing integrated circuit (IC) chips and method of making test heads. The test head includes an array of vias (e.g., annular vias or grouped rectangular vias) through, and exiting one surface of, a semiconductor layer, e.g., a silicon layer. The vias, individual test probe tips, may be on a pitch at or less than fifty microns (50 ?m). The probe tips may be stiffened with SiO2 (and optionally silicon) extending along the sidewalls. A redistribution layer connects individual test probe tips externally. The probe tips may be capped with a hardening cap that also caps stiffening SiO2 and silicon along the tip sidewall.

Abstract: Self-aligned sextuple patterning (SASP) processes and mask design methods for the semiconductor manufacturing are invented. The inventions pertain to methods of forming one and/or two dimensional features on a substrate having the feature density increased to six times of what is possible using the standard optical lithographic technique; and methods to release the overlay requirement when patterning the critical layers of semiconductor devices. Our inventions provide production-worthy methods for the semiconductor industry to continue device scaling beyond 15 nm (half pitch).

Abstract: A method for forming fine pattern includes sequentially forming a first thin film and a second thin film over a target layer for patterning, forming a partition over the second thin film, removing the partition after forming spacers on sidewalls of the partition, forming first pattern of the second thin film by etching the second thin film of a first region and the second thin film of a second region while exposing the spacers, forming second pattern of the second thin film by using the spacers as masks and etching the first pattern of the second thin film in the first region, forming first thin film pattern by using the first and second patterns of the second thin film as masks in the first and second regions and etching the first thin film, and etching the pattern target layer.

Abstract: According to a disclosed semiconductor device fabrication method according to one embodiment of the present invention, a layer having a line-and-space pattern extending in one direction is etched using another layer having a line-and-space pattern extending in another direction intersecting the one direction, thereby obtaining a mask having two-dimensionally arranged dots. An underlying layer is etched using the mask, thereby providing two-dimensionally arranged pillars.

Abstract: A method for manufacturing a device comprising a structure with nanowires based on a semiconducting material such as Si and another structure with nanowires based on another semiconducting material such as SiGe, and is notably applied to the manufacturing of transistors.

Abstract: A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.

Abstract: A method for fabricating a metal pattern in a semiconductor device includes forming a metal layer over a substrate, forming a hard mask layer over the metal layer, forming a sacrifice pattern over the hard mask layer, forming a spacer pattern on sidewalks of the sacrifice pattern, removing the sacrifice pattern, forming a hard mask pattern by etching the hard mask layer using the spacer pattern as an etch barrier, forming an etching protection layer over the hard mask pattern and on sidewalks of the hard mask pattern, and forming the metal pattern by performing primary and secondary etching processes on the metal layer using the etching protection layer as an etch barrier.