Abstract: A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.

Abstract: Methods are provided for forming gates in gate-last processes. The methods may include performing chemical mechanical polishing (CMP) on an interlayer dielectric (ILD) that is on a plurality of dummy gates, each of the plurality of dummy gates including a gate mask in an upper portion thereof, and the CMP exposing the gate mask. The methods may also include removing the gate mask by etching the gate mask. The methods may further include performing CMP on the ILD.

Abstract: A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad.

Abstract: The present invention provides an aluminum nitride substrate and an aluminum nitride circuit board having excellent insulation characteristics and heat dissipation properties and having high strength, a semiconductor apparatus, and a method for manufacturing an aluminum nitride substrate.

Abstract: A method of manufacture of an integrated packaging system includes: providing a substrate; mounting an integrated circuit on the substrate; mounting an interposer substrate having an interposer pad on the integrated circuit; covering an encapsulant over the integrated circuit and the interposer substrate; forming a hole through the encapsulant aligned over the interposer pad; and placing a conductive connector on and in direct contact with the interposer pad.

Abstract: A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.

Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure.

Abstract: A method of growing planar non-polar m-plane III-Nitride material, such as an m-plane gallium nitride (GaN) epitaxial layer, wherein the III-Nitride material is grown on a suitable substrate, such as an m-plane Sapphire substrate, using hydride vapor phase epitaxy (HVPE). The method includes in-situ pretreatment of the substrate at elevated temperatures in the ambient of ammonia and argon, growing an intermediate layer such as an aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN) on the annealed substrate, and growing the non-polar m-plane III-Nitride epitaxial layer on the intermediate layer using HVPE. Various alternative methods are disclosed.

Abstract: A semiconductor device is provided which is constituted by semiconductor devices including a thin film transistor with a GOLD structure, the GOLD structure thin film transistor being such that: a semiconductor layer, a gate insulating film, and a gate electrode are formed in lamination from the side closer to a substrate; the gate electrode is constituted of a first-layer gate electrode and a second-layer gate electrode shorter in the size than the first-layer gate electrode; the first-layer gate electrode corresponding to the region exposed from the second-layer gate electrode is formed into a tapered shape so as to be thinner toward the end portion; a first impurity region is formed in the semiconductor layer corresponding to the region with the tapered shape; and a second impurity region having the same conductivity as the first impurity region is formed in the semiconductor layer corresponding to the outside of the first-layer gate electrode, which is characterized in that a dry etching process consisting

Abstract: Techniques for fabricating nanowire-based devices are provided. In one aspect, a method for fabricating a semiconductor device is provided comprising the following steps. A wafer is provided having a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer. Nanowires and pads are etched into the SOI layer to form a ladder-like structure wherein the pads are attached at opposite ends of the nanowires. The BOX layer is undercut beneath the nanowires. The nanowires and pads are contacted with an oxidizing gas to oxidize the silicon in the nanowires and pads under conditions that produce a ratio of a silicon consumption rate by oxidation on the nanowires to a silicon consumption rate by oxidation on the pads of from about 0.75 to about 1.25. An aspect ratio of width to thickness among all of the nanowires may be unified prior to contacting the nanowires and pads with the oxidizing gas.

Abstract: Methods and apparatus for providing constant emissivity of the backside of susceptors are described. Provided is a method comprising: providing a susceptor in a deposition chamber, the susceptor comprising a susceptor plate and a layer comprising an oxide, a nitride, an oxynitride, or combinations thereof, the layer being stable in the presence of the reactive process gases; and locating the wafer on a support surface of the susceptor plate. The method can further comprise selectively depositing an epitaxial layer or a non-epitaxial layer on a surface of the wafer. The method can also further comprise selectively etching to maintain the oxide, nitride, oxynitride, or combinations thereof layer.

Abstract: Processes for forming high density gap-filling silicon oxide on a patterned substrate are described. The processes increase the density of gap-filling silicon oxide particularly in narrow trenches. The density may also be increased in wide trenches and recessed open areas. The densities of the gap-filling silicon oxide in the narrow and wide trenches/open areas become more similar following the treatment which allows the etch rates to match more closely. This effect may also be described as a reduction in the pattern loading effect. The process involves forming then planarizing silicon oxide. Planarization exposes a new dielectric interface disposed closer to the narrow trenches. The newly exposed interface facilitates a densification treatment by annealing and/or exposing the planarized surface to a plasma.

Abstract: An upper board having an opening and forming a circuit on a surface layer, a connection sheet between boards having an opening and forming conductive holes filled with conductive paste in through-holes, and a lower board forming a circuit on a surface layer are stacked up, heated and pressed. In particular, the connection sheet between boards is made of a material different from the upper board and the lower board. A multi-layer circuit board having a cavity structure, and a full-layer IVH structure with high interlayer connection reliability can be manufactured.

Abstract: Planarization methods and microelectronic structures formed therefrom are disclosed. The methods and structures use planarization materials comprising fluorinated compounds or acetoacetylated compounds. The materials are self-leveling and achieve planarization over topography without the use of etching, contact planarization, chemical mechanical polishing, or other conventional planarization techniques.

Abstract: A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material.

Abstract: The present application discloses a method for manufacturing a gate-all-around field effect transistor, comprising the steps of: forming a suspended fin in a semiconductor substrate; forming a gate stack around the fin; and forming source/drain regions in the fin on both sides of the gate stack, wherein an isolation dielectric layer is formed in a portion of the semiconductor substrate which is adjacent to bottom of both the fin and the gate stack. The present invention relates to a method for manufacturing a gate-all-around device on a bulk silicon substrate, which suppress a self-heating effect and a floating-body effect of the SOI substrate, and lower a manufacture cost. The inventive method is a conventional top-down process with respect to a reference plane, which can be implemented as a simple manufacture process, and is easy to be integrated into and compatible with a planar CMOS process. The inventive method suppresses a short channel effect and promotes miniaturization of MOSFETs.

Abstract: Processes for forming high density gap-filling silicon oxide on a patterned substrate are described. The processes increase the density of gap-filling silicon oxide particularly in narrow trenches. The density may also be increased in wide trenches and recessed open areas. The densities of the gap-filling silicon oxide in the narrow and wide trenches/open areas become more similar following the treatment which allows the etch rates to match more closely. This effect may also be described as a reduction in the pattern loading effect. The process involves forming then planarizing silicon oxide. Planarization exposes a new dielectric interface disposed closer to the narrow trenches. The newly exposed interface facilitates a densification treatment by annealing and/or exposing the planarized surface to a plasma.

Abstract: A method for forming through vias connecting the front surface to the rear surface of a semiconductor substrate, including the steps of: forming openings in the substrate, thermally oxidizing walls of the openings, filling the openings with a sacrificial material, forming electronic components in the substrate, etching the sacrificial material, filling the openings with a metal, and etching the rear surface of the substrate all the way to the bottom of the openings.

Abstract: A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.

Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: A method of producing a nitride semiconductor laser device includes: forming a wafer including a nitride semiconductor layer of a first conductivity type, an active layer of a nitride semiconductor, a nitride semiconductor layer of a second conductivity type, and an electrode pad for the second conductivity type stacked in this order on a main surface of a conductive substrate and also including stripe-like waveguide structures parallel to the active layer; cutting the wafer to obtain a first type and a second type of laser device chips; and distinguishing between the first type and the second type of chips by automatic image recognition. The first type and the second type of chips are different from each other in position of the stripe-like waveguide structure with respect to a width direction of each chip and also in area ratio of the electrode pad to the main surface of the substrate.

Abstract: A method of forming a gate of a semiconductor device comprising providing a semiconductor substrate over which a gate insulating layer, a first conductive layer, a dielectric layer, and a second conductive layer are sequentially formed, the semiconductor substrate defining gate line regions; removing he second conductive layer between gate line regions; removing the dielectric layer so that a top surface of the first conductive layer between the gate line regions is exposed; performing a first etch process in order to lower a height of the first conductive layer between the gate line region; removing he dielectric layer between the gate line regions; and, performing a second etch process in order to remove the first conductive layer between the gate line regions.

Abstract: Embodiments described herein generally relate to apparatus and methods for forming Group III-V materials by metal-organic chemical vapor deposition (MOCVD) processes and hydride vapor phase epitaxial (HVPE) processes. In one embodiment, a method for fabricating a nitrogen-face (N-face) polarity compound nitride semiconductor device is provided. The method comprises depositing a nitrogen containing buffer layer having N-face polarity over one or more substrates using a metal organic chemical vapor deposition (MOCVD) process to form one or more substrates having N-face polarity and depositing a gallium nitride (GaN) layer over the nitrogen containing buffer layer using a hydride vapor phase epitaxial (HVPE) deposition process, wherein the nitrogen containing buffer layer and the GaN layer are formed without breaking vacuum and exposing the one or more substrates to atmosphere.

Abstract: The present invention discloses a semiconductor device package structure with redistribution layer (RDL) and through silicon via (TSV) techniques. The package structure comprises an electronic element which includes a dielectric layer on a backside surface of the electronic element, a plurality of first conductive through vias across through the electronic element and the dielectric layer, and a plurality of conductive pads accompanying the first conductive through vias on an active surface of the electronic element; a filler material disposed adjacent to the electronic element; a first redistribution layer disposed over the dielectric layer and the filler material, and connected to the first conductive through vias; a first protective layer disposed over the active surface of the electronic element, the conductive pads, and the filler material; and a second protective layer disposed over the redistribution layer, the dielectric layer, and the filler material.

Abstract: The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer outside the recess is flush to or lower than the bottom of the recess, the etching speed of the surface layer being higher than that of the etching-resist layer; removing the etching-resist layer; and etching the surface layer to a predetermined depth. The method can avoid concentric ring recesses on the surface of the wafer resulted from a chemical mechanical polishing (CMP) process in the prior art, and can be used to obtain a wafer surface suitable for optical applications.

Abstract: A manufacturing method of the present invention includes a process using a first multi-tone mask, in which a first conductive layer in which a transparent conductive layer and a metal layer are stacked over a substrate, a gate electrode formed of a first conductive layer, and a pixel electrode formed of a single layer of the transparent conductive layer are formed, a process using a second multi-tone mask, in which a contact hole to the pixel electrode, and an island of an i-type semiconductor layer and an n+ type semiconductor layer are formed after a gate insulating film, the i-type semiconductor layer, and the n+ type semiconductor layer are formed, a process using a third photomask, in which a source electrode and a drain electrode are formed after a second conductive layer is formed, and a process using a fourth photomask, in which an opening region is formed after a protective film is deposited.

Abstract: A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change material as a mask, reflowing the multi-temperature phase-change material, and patterning the first layer using the reflowed multi-temperature phase-change material as a mask.

Abstract: Methods for etching a dielectric barrier layer with high selectivity to a dielectric bulk insulating layer are provided. In one embodiment, the method includes providing a substrate having a portion of a dielectric barrier layer exposed through a dielectric bulk insulating layer in a reactor, flowing a gas mixture containing H2 gas, fluorine containing gas, at least an insert gas into the reactor, and etching the exposed portion of the dielectric barrier layer selectively to the dielectric bulk insulating layer.

Abstract: A method of reducing threading dislocation densities in non-polar such as a-{11-20} plane and m-{1-100} plane or semi-polar such as {10-1n} plane III-Nitrides by employing lateral epitaxial overgrowth from sidewalls of etched template material through a patterned mask. The method includes depositing a patterned mask on a template material such as a non-polar or semi polar GaN template, etching the template material down to various depths through openings in the mask, and growing non-polar or semi-polar III-Nitride by coalescing laterally from the tops of the sidewalls before the vertically growing material from the trench bottoms reaches the tops of the sidewalls. The coalesced features grow through the openings of the mask, and grow laterally over the dielectric mask until a fully coalesced continuous film is achieved.

Abstract: A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer (19) that is isolated from an underlying first single crystal semiconductor layer (17) by a buried insulator layer (18); patterning and etching the second single crystal semiconductor layer (19) to form a single crystal mandrel (42) having vertical sidewalls; thermally oxidizing the vertical sidewalls of the single crystal mandrel to grow oxide spacers (52) having a substantially uniform thickness; selectively removing any remaining portion of the single crystal mandrel (42) while substantially retaining the oxide spacers (52); and selectively etching the first single crystal semiconductor layer (17) using the oxide spacers (52) to form one or more FinFET channel regions (92).

Abstract: A method for processing a substrate comprising at least a buried oxide (BOX) layer and a semiconductor material layer is provided. The method includes etching the semiconductor material layer to form a vertical semiconductor material structure overlying the BOX layer, leaving an exposed portion of the BOX layer. The method further includes exposing a top surface of the exposed portion of the BOX layer to an oxide etch resistant species to form a thin oxide etch resistant layer overlying the exposed portion of the BOX layer.

Abstract: A method of processing a stack, the method including depositing a fusible material on a first hardmask layer, the first hardmask layer disposed on a surface of a pre-processed stack, the pre-processed stack being disposed on at least a portion of a substrate; heating the fusible material layer to a temperature at or above its melting point to cause it to form a fusible material sphere, the fusible material sphere disposed on less than the entire first hardmask layer; etching the first hardmask layer, wherein the fusible material sphere prevents a portion of the first hardmask layer from etching, thereby forming a second hardmask layer; and etching the pre-processed stack, wherein at least the second hardmask layer prevents a portion of the pre-processed stack from etching, thereby forming a stack.

Abstract: A method of manufacturing a wiring board having a semiconductor chip mounting surface for mounting a semiconductor chip thereon which is manufactured by a process including a step of forming a wiring layer and an insulating layer on a support board and a step of removing the support board, including a peeling layer forming step of forming a peeling layer on the support board formed by a material having a coefficient of thermal expansion which is equal to that of a semiconductor substrate constituting the semiconductor chip, and a support board removing step of removing the support board by carrying out a predetermined treatment over the peeling layer.

Abstract: A manufacturing method of the present invention includes a process using a first multi-tone mask, in which a first conductive layer in which a transparent conductive layer and a metal layer are stacked over a substrate, a gate electrode formed of a first conductive layer, and a pixel electrode formed of a single layer of the transparent conductive layer are formed, a process using a second multi-tone mask, in which a contact hole to the pixel electrode, and an island of an i-type semiconductor layer and an n+ type semiconductor layer are formed after a gate insulating film, the i-type semiconductor layer, and the n+ type semiconductor layer are formed, a process using a third photomask, in which a source electrode and a drain electrode are formed after a second conductive layer is formed, and a process using a fourth photomask, in which an opening region is formed after a protective film is deposited.

Abstract: A method of planarizing a dielectric insulating layer including providing a substrate including forming a first dielectric insulating layer having a concave and convex portion on the substrate; forming an organic resinous layer on the first dielectric insulating layer and exposing the convex portion of the first dielectric insulating layer; isotropically etching the first dielectric insulating layer convex portion; removing the organic resinous layer; and, forming a second dielectric insulating layer on the first dielectric insulating layer.

Abstract: The present invention includes forming an optical guide layer on a substrate, forming a cap layer on the optical guide layer, and forming openings in parts of the optical guide layer and the cap layer to form a diffraction grating from part of the optical guide layer. The substrate is heated to a temperature less than a growth temperature of the cap layer and equal to at least a temperature at which mass transport of the cap layer occurs to cover, with part of the cap layer, the lateral faces of the optical guide layer exposed by the openings. A burying layer burying the diffraction grating is formed on the substrate, after the mass transport.

Abstract: An aqueous solution is useful for selective removal in the presence of a low-k dielectric. The aqueous solution comprises by weight percent 0 to 25 oxidizer; 0.00002 to 5 multi-component surfactant, the multi-component surfactant having a hydrophobic tail, a nonionic hydrophilic portion and an anionic hydrophilic portion, the hydrophobic tail having 6 to 30 carbon atoms and the nonionic hydrophilic portion having 10 to 300 carbon atoms; 0 to 15 inhibitor for a nonferrous metal; 0 to 50 abrasive; 0 to 20 complexing agent for a nonferrous metal; and water.

Abstract: Calibration wafers and methods for calibrating a plasma process performed in a plasma processing apparatus, such as an ionized physical vapor deposition apparatus. The calibration wafer includes one or more selective-redeposition structures for calibrating a plasma process. The selective-redeposition structures receive a controllable and/or measurable amount of redeposited material during the plasma process.

Abstract: Disclosed is a substrate processing method that dissolves and deforms a photoresist film having a first pattern formed on a substrate to reshape the resist film into a second pattern During the reflow process, an atmosphere of a thinner vapor-containing gas is established in a processing chamber. A substrate is placed on a temperature adjusting plate. The target temperature of the temperature adjusting plate is set and controlled by a control unit, and the temperature of the temperature adjusting plate is controlled by a temperature regulator based on the target temperature set by the control unit The control unit set and controls the target temperature so that it meets the following requirement: the atmospheric temperature?the target temperature?(the atmospheric temperature+2° C.). Due to the above, the reflowing of the resist can be performed stably, while achieving a satisfactory reflow rate although it is somewhat low.

Abstract: Provided is a method for manufacturing an image sensor. The method includes the following. A color filter layer is formed on a semiconductor substrate having a photodiode and a transistor formed thereon. A planarization layer is formed on the color filter layer. An LTO (Low Temperature Oxide) layer is formed on the planarization layer. A photoresist pattern is formed to correspond to the color filter layer on the LTO layer, and a reflow process is performed. A microlens array is formed by reactive ion etching the photoresist pattern and the LTO layer. A second reflow process may be performed on the photoresist pattern and/or the LTO layer during the reactive ion etching process.

Abstract: A method of forming a pattern includes forming a first layer on a substrate, forming a second layer on the first layer, depositing a multi-temperature phase-change material on the second layer, patterning the second layer using the multi-temperature phase-change material as a mask, reflowing the multi-temperature phase-change material, and patterning the first layer using the reflowed multi-temperature phase-change material as a mask.

Abstract: There are provided a method of forming a fine metal pattern and a method of forming a metal line using the same. In the method of forming a fine metal pattern, a substrate is prepared where a first interlayer insulating layer is formed. A via plug is formed on the first interlayer insulating layer. A plurality of sidewall buffer patterns are formed on the first interlayer insulating layer having the via plug, wherein the plurality of the sidewall buffer patterns are spaced apart from each other by a predetermined distance. The sidewall layer is deposited on the first interlayer insulating layer and the sidewall buffer patterns. The sidewall layer is etched such that sidewall patterns remains on sidewalls of the sidewall buffer patterns.

Abstract: A method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process is disclosed, in which the gate electrode, a metal silicide layer, a spacer, a silicon nitride cap layer, and a dielectric layer have been formed. The method includes performing a chemical mechanical polishing process to polish the dielectric layer using the silicon nitride cap layer as a polishing stop layer to expose the silicon nitride cap layer over the gate electrode; removing the exposed silicon nitride cap layer to expose the metal silicide layer; and performing a first etching process to remove the metal silicide layer on the gate electrode.

Abstract: A method of making a thin film transistor comprises (a) solution depositing a dispersion comprising semiconducting metal oxide nanoparticles onto a substrate, (b) sintering the nanoparticles to form a semiconductor layer, and (c) optionally subjecting the resulting semiconductor layer to post-deposition processing.

Abstract: A method may involve mounting a first supporting plate on an active surface of a wafer using an adhesive. A portion of the back surface of the wafer may be backlapped. A second supporting plate may be mounted on the back surface of the wafer using an adhesive. The first supporting plate may be removed from the active surface of the wafer. Conductive bumps may be provided on the active surface. A backlapping process may include a first grinding process, a second grinding process, and a polishing process. The first and the second supporting plates may be fabricated from a solid material. The adhesive may be an ultraviolet cure adhesive or a thermal cure adhesive.

Abstract: A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a metallic material formed within the via and on a surface of the insulator. The metallic material may be deposited on the surface and within the via. A hard mask of a flowable oxide is deposited over the metallic material in the via to protect the metallic material in the via. A subsequent dry sputter etch removes the metallic material from the surface of the insulator and a portion of the hard mask. After complete removal of the hard mask, a glass material is recessed over the metallic material in the via. Then, a layer of a metal-containing material is formed over the glass material. Finally, a second conductor is formed on the surface of the insulator.

Abstract: The invention presents a novel polyimide-based thin film self-assembly technology, including five process steps described as follows: (1) deposits a sacrificial layer and a low-stress microstructure layer on a silicon substrate; (2) patterns and etches the low-stress microstructure layer to provide a stationary part and a movable part of the microstructure; (3) coats a photosensitive polyimide thin film as elastic joint of the microstructure layer and defines the shape by using photolithography technique; (4) releases the sacrificial layer beneath the movable part of microstructure layer by wet etching; (5) lastly proceeds the reflow process of polyimide to result in the contraction of the elastic joint further to rotate and lift the movable part in completion of the self-assembly of the microstructure. As the invention can be extensively applied to a myriad of miniaturizing industries, it can solve all the drawbacks of the prior art manufacturing process and miniaturization.

Abstract: A method of making a nitride-based compound semiconductor crystal has the step of growing a nitride-based compound semiconductor crystal with a predetermined thickness by using a nitride-based compound semiconductor substrate as a seed crystal. The nitride-based compound semiconductor substrate as the seed crystal is polished at both surfaces thereof.

Abstract: The present invention provides a method for removing a metal element effectively from a crystalline semiconductor film obtained with the use of the metal element, without increasing the number of processes. In the present invention, an amorphous semiconductor film is formed on an insulating surface, a metal element for promoting crystallization is added to the amorphous semiconductor film, the amorphous semiconductor film is heated to form a crystallized semiconductor film, a continuous wave laser beam is irradiated to the crystallized semiconductor film, and an upper portion of the crystallized semiconductor film is removed.

Abstract: A method of manufacturing a plurality of microlenses on a substrate comprises forming a grid having raised ridges defining a plurality of openings on the substrate and forming a plurality of patterned photoresist features each disposed within one of the plurality of openings. The plurality of patterned photoresist features can then be reflowed inside the grid.