Abstract: In a method for manufacturing a semiconductor device in a wafer having a device formation area and an inspection pattern formation area, an interconnection layer is formed in the device formation area with forming no interconnection layer in the inspection pattern formation area. An interlayer insulating film is formed to cover the whole surface, and then, is selectively removed to form a first hole exposing a portion of the interconnection layer in the device formation area and a second hole exposing a portion of a silicon layer in the inspection pattern formation area. An aluminum-based alloy is filed into the first and second holes. In the second hole, spiking occurs into the silicon layer when aluminum from the aluminum-based alloy comes in contact with the silicon layer. After filling, the surface above the second hole is observed for an indication that spiking occurred into the silicon layer.

Abstract: We have discovered that complete copper filling of semiconductor features such as trenches and vias, without the formation of trapped voids, can be accomplished using a copper reflow process when the unfilled portion of the feature structure prior to reflow comprises a capillary within the feature, wherein the volume of the capillary represents between about 20% and about 90%, preferably between about 20% and about 75% of the original feature volume prior to filling with copper. The aspect ratio of the capillary is preferably at least 1.5. The maximum opening dimension of the capillary is less than about 0.8 &mgr;m. The preferred substrate temperature during the reflow process includes it either a soak at an individual temperature or a temperature ramp-up or ramp-down where the substrate experiences a temperature within a range from about 300° C. to about 600° C., more preferably between about 300° C. and about 450° C.

Abstract: For giving a device surface to a semiconductor device comprising a semiconductor substrate portion which has a substrate surface and a protruding portion protruding from the substrate surface, a method includes the steps of coating the substrate surface and the protruding portion with a first anti-polishing film, depositing an insulator film on the first anti-polishing film, and coating the insulator film with a second anti-polishing film. The insulator film has a first polishing rate for a polishing operation. The second anti-polishing film has a second polishing rate which can be slower than the first polishing rate for the polishing operation. Thereafter, the polishing operation is applied to the second anti-polishing film and to the insulator to make the device surface become substantially planarized. It is preferable that the first anti-polishing film has the second polishing rate for the polishing operation.

Abstract: The occurrence of defects in interconnect metal structure is reduced or eliminated by a method wherein a semiconductor substrate having a dielectric layer, a metal-containing electrically conductive layer and a patterned photoresist layer, the metal-containing electrically conductive layer overlying the dielectric layer and the photoresist layer overlying the conductive layer such that portions of the conductive layer are exposed, is treated using a sequence of at least four reactive ion etching environments, each having a different etchant composition from the previous and/or subsequent environment. The invention is especially applicable for metal interconnect structures having aluminum and/or copper as the primary conductive layer.

Abstract: The process includes the following steps. At first, a masking layer is formed over the semiconductor substrate. A portion of the masking layer is then removed to form an opening to the semiconductor substrate. Sidewall spacers are formed on the opening and a portion of the semiconductor substrate is removed to form a trench, through an aperture defined by the sidewall spacers. The sidewall spacers is then removed and a liner layer is formed conformably over the trench.

Abstract: A method of forming an isolation trench in a semiconductor device results in increasing trench isolation characteristics by optimizing an annealing temperature thereby removing substrate defects caused during the etching of a semiconductor substrate and relieving stress thereby improving yield and reliability of devices. Appropriate adjustment of the rates of temperature change allow higher annealing temperatures to be employed without encountering attendant stresses due to differences in thermal expansion coefficients between the substrate and the trench material.

Abstract: The present invention is directed to wet processing methods for the manufacture of electronic component precursors, such as semiconductor wafers used in integrated circuits. More specifically, this invention relates to methods, for example, prediffusion cleaning, stripping, and etching of electronic component precursors using sequential chemical processing techniques.

Abstract: A process for dry etching a surface within a vacuum treatment reactor includes evacuating the reactor, generating a glow discharge within said reactor, feeding a reactive etching gas into said reactor and reacting said etching gas within said reactor, removing gas with reaction products of said reacting from said reactor and installing an initial flow of said etching gas into said reactor and reducing said flow after a predetermined time span and during said reacting. The vacuum treatment reactor has a reactor with a pumping arrangement for evacuating the reactor. A glow discharge generating arrangement is connected to an electric power supply. A gas tank arrangement is connected to the reactor and has a reactive etching gas such as SF.sub.4.

Abstract: A method for the manufacture of a semiconductor device with trench isolation regions includes forming at least one trench in a substrate to define one or more isolation regions. At least a portion of the trench is filled with a flowable oxide-generating material which is then formed into an oxide layer. An optional dielectric layer can be deposited over the oxide layer. A portion of the oxide layer and/or the optional dielectric layer is removed to generate a substantially planer surface.

Abstract: Semiconductor devices with copper interconnects wherein a barrier metal layer is applied over the surface of a dielectric layer with a plurality of trenches. The barrier metal layer lines the trenches. A copper layer is placed over the barrier metal layer and fills the trenches. The part of the copper layer that is not inside the trenches is polished away, making sure that the barrier metal layer is not polished away. The copper layer is laser annealed to increase the grain size, remove seams, and provide a better interface bond between the barrier metal layer and the copper layer. The barrier metal layer protects the dielectric layer during the annealing process. The part of the barrier metal layer that is not in the trenches is removed by polishing.

Abstract: Improved gap fill of narrow spaces is achieved by using a doped silicate glass having a dopant concentration in a bottom portion thereof which is greater than an amount which causes surface crystal growth and in an upper portion thereof having a lower dopant concentration such that the overall dopant concentration of the doped silicate glass is below that which causes surface crystal growth.

Abstract: A process for forming one or more fluid microchannels on a substrate is disclosed that is compatible with the formation of integrated circuitry on the substrate. The microchannels can be formed below an upper surface of the substrate, above the upper surface, or both. The microchannels are formed by depositing a covering layer of silicon oxynitride over a mold formed of a sacrificial material such as photoresist which can later be removed. The silicon oxynitride is deposited at a low temperature (.ltoreq.100.degree. C.) and preferably near room temperature using a high-density plasma (e.g. an electron-cyclotron resonance plasma or an inductively-coupled plasma). In some embodiments of the present invention, the microchannels can be completely lined with silicon oxynitride to present a uniform material composition to a fluid therein. The present invention has applications for forming microchannels for use in chromatography and electrophoresis.

Abstract: A method of forming a dual damascene structure including contacts and interconnects over a substrate is disclosed. The method comprises the steps of: forming an insulating layer on said substrate; forming a nitride layer over said insulating layer; forming a cap oxide layer over said nitride layer; patterning and etching said insulating layer, nitride layer, and cap oxide layer to correspond to the location of said contacts; patterning and etching said nitride layer and said cap oxide layer to correspond to the pattern of said interconnects; and performing a reflow step.

Abstract: A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with reduced number of masking process steps. This is accomplished by first forming shallow tapered holes to a certain depth over certain regions in a substrate by means of isotropic etching and then extending them by anisotropic etching to full depth corresponding to the regions they are allowed to contact. The net result is a whole set of holes which are self-aligned and which are formed by means of a single photoresist mask.

Abstract: A semiconductor device having a closed step portion and a global step portion including an insulating layer having a planarized surface on the global step portion is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.

Abstract: A method for planarizing a semiconductor structure having a first surface region with a high aspect ratio topography and a second surface region with a low aspect ratio topography. A flowable material is deposited over the first and second surface regions of the structure. A portion of the material fills gaps in the high aspect ratio topography to form a substantially planar surface over the high aspect ratio topography. A doped layer, for example phosphorus doped glass, is formed over the flowable oxide material. The doped layer is disposed over the high aspect ratio and over the low aspect ratio regions. Upper surface portions over the low aspect ratio region are higher than an upper surface of the flowable material. The upper portion of the doped layer is removed over both the first and second surface portions to form a layer with a substantially planar surface above both the high aspect ratio region and the low aspect ratio region.

Abstract: A manufacturing method for semiconductor devices such as dynamic RAM, etc. which removes the layer part more on the high position than an arbitrary position on a step forming a gradation by just a prescribed thickness when flattening a layer with a gradation formed of a high position part and a low position part. Then the projecting part created after the etching existing more on the low position side than at the arbitrary position of the gradation is eliminated by heat treatment.

Abstract: The nucleation efficiency of a thermal ink jet printhead is improved by forming a heater element with a planar surface. A heater resistor, polysilicon in a preferred embodiment, has an irregular surface which can trap gas or vapors in the cracks or crevices. When the heater resistor is pulsed, the nucleation temperature is reduced by these trapped vapors requiring an increase in electrical input to the resistors, thereby reducing efficiency. The invention recognizes that a heater resistor with a planar surface in contact with an ink layer results in a higher nucleation temperature and increased efficiency. In one embodiment, a phosphosilicate glass (PSG) is flowed directly onto the resistor surface forming a planarization layer. Subsequent deposition of tantalum substantially replicates the underlying topography creating a heater resistor with a smooth surface adjacent the ink.

Abstract: A composite that protects thermal barrier coatings from the deleterious effects of environmental contaminants at operational temperatures is discovered. The thermal barrier coated parts have least two outer protective coatings that decrease infiltration of molten contaminant eutectic mixtures into openings in the thermal barrier coating.

Abstract: A method for forming a contact hole in a phosphosilicate glass layer includes the steps of forming a phosphosilicate glass layer, reflowing the phosphosilicate glass layer, removing a surface portion of the phosphosilicate glass layer, and forming the contact hole in the phosphosilicate glass layer. In particular, the surface portion of the phosphosilicate glass layer can be on the order of about 1000 .ANG. thick, and the step of removing the surface portion can include etching the surface portion. Furthermore, the step of forming the contact hole can include the step of selectively wet etching the phosphosilicate glass layer followed by the step of selectively dry etching the phosphosilicate glass layer.

Abstract: Fabrication of atomic step-free regions on a substrate surface is achieved by first forming a two-dimensional pattern on the substrate. The pattern is preferably a grating comprising an array of troughs or mesas which are separated from one another by a plurality of ridges or trenches. Any atomic steps on the flat top surfaces of the troughs or mesas are moved into barrier regions formed by the ridge or trench sidewalls during a high temperature annealing or deposition step, thereby leaving the flat surfaces of the troughs and mesas free of atomic steps. Structures having step-free regions large enough to accommodate micron sized devices having nanometer sized features are thereby formed.

Abstract: A method for forming an interlayer insulating film of semiconductor device is disclosed. A first interlayer insulating film is deposited on the entire top surface of a semiconductor device comprising a high step cell area and lower step periphery area, followed by the thermal treatment thereof. A second interlayer insulating film which is more resistant to etch than the first interlayer insulating film is deposited. Again, a third interlayer insulating film is deposited over the second interlayer insulating film, followed by the heat treatment thereof. These interlayer insulating films are planarized by a CMP process. Upon the CMP process, the first interlayer insulating film is rapidly etched out while the second interlayer insulating film is slowly removed and this difference in etching rate allows the polishing end point to be readily detected without an additional detector.

Abstract: A semiconductor manufacturing method for devices, such as a DRAM, having a plurality of circuit elements of at least two substantially different heights (such as memory-cells vs. peripheral circuits) on a common semiconductor substrate. A plurality of circuit elements of at least two substantially different heights are formed on a common semiconductor substrate. A common insulating layer, such as BPSG, whose top surface has substantial variation in height above the substrate, is deposited over the circuit elements. A resist mask layer is deposited over the insulating layer with openings over high portions of the insulating layer's top surface exceeding a first predetermined height. Then the insulating layer's high portions are etched down to a second predetermined height to make its overall top surface more even, and the resist mask layer removed. The enables a working layer that would be easily damaged by substantial height variation to be deposited on the evened insulating layer.

Abstract: A method of forming high contrast alignment marks on an integrated circuit wafer for patterning a layer of highly reflective electrode metal is described. A method of patterning a layer of highly reflective metal on an integrated circuit wafer using high contrast alignment marks is also described. Due to a difference in height of alignment marks and contact metal surrounding the alignment marks the alignment marks are transferred to the contour of the highly reflective electrode metal. A non reflective layer of bottom anti-reflection coating material is then used to provide high contrast at the location where the edges of the alignment marks are transferred to the highly reflective electrode metal.

Abstract: A semiconductor memory cell structure includes a semiconductor substrate, a plurality of field insulating layers on the semiconductor substrate along a first direction at a first interval, a plurality of floating gate electrodes on the semiconductor substrate between the field insulating layers, the floating gate electrodes being aligned with the field insulating layers, a plurality of control electrodes over the floating gate electrodes and the field insulating layer at a second interval along a second direction, and a plurality of impurity areas on the semiconductor substrate at both sides of the floating gate electrodes along the first direction between the field insulating layers.

Abstract: An article of manufacture having at least in part the surface appearance of brass includes a ceramic barrier coating applied to a base layer of Cu/Ni/Cr. The ceramic barrier coating includes an initial layer of ZrCn and an additional layer which is a nitrite, carbide or oxide of Zr, Ti, Si, Al or Hf.

Abstract: An improved structure and a process for forming an interlevel dielectric layer having a low capacitance between closely spaced metallurgy lines is provided. The method begins with a substrate surface having closely spaced metallurgy lines. A silicon oxide dielectric layer having a closed void between adjacent metallurgy lines is formed using electro cyclotron resonance techniques. The voids in the silicon dioxide dielectric layer are formed by controlling the ECR process parameters to achieve a proper etch to deposition ratio. The etch to deposition ratio of the silicon oxide layer is adjusted to the particular height and spacing between the metallurgy lines. Next, a spin-on-glass layer is formed over the silicon oxide dielectric layer. Portions of the SOG layer are etched back or chemically mechanically polished. The void (air) has a lower capacitance than the ECR silicon oxide layer.

Abstract: An improved method for forming a planar borophosphosilicate glass (BPSG) insulating layer having a reduced thermal budget was achieved. The method involves forming a multilayer BPSG comprised of four layers with different boron and phosphorus concentrations in each layer. The first layer deposited has the conventional doping range, and therefore would require higher reflow temperatures for leveling. By the method of this invention, a second low-doped BPSG buffer layer is deposited and then a heavily doped third BPSG layer is deposited having a lower reflow temperature, and therefore is planarized at a lower temperature. A low-doped fourth cap BPSG layer is used over the third BPSG layer to minimize moisture absorption and unstable crystal formation prior to the reflow anneal.

Abstract: A board of calcium silicate crystals, characterized in that the board is composed of a plurality of layers of laminated thin sheets, each of the thin sheets having a thickness of 2 mm or less, each layer comprising secondary particles of calcium silicate crystals, a fibrous material, a coagulant and preferably additionally a polymer adsorbed on the surface of the secondary particles of calcium silicate; wherein each layer contains secondary calcium silicate particles interconnected with one another, and wherein the superposed thin sheets are firmly united with one another into an integral body by the interlayer interconnection of secondary particles of calcium silicate crystals present on the surface of the sheets.