Abstract: A nonvolatile memory cell includes a storage element, the storage element comprising a carbon material, a steering element located in series with the storage element, and a metal silicide layer located adjacent to the carbon material. A method of making a device includes forming a metal silicide over a silicon layer, forming a carbon layer over the metal silicide layer, forming a barrier layer over the carbon layer, and patterning the carbon layer, the metal silicide layer, and the silicon layer to form an array of pillars.

Abstract: A method for fabricating a semiconductor device with a fuse element includes providing a semiconductor structure with a fuse element formed over a first device region thereof. A first interlayer dielectric layer, an etching stop layer and a second interlayer dielectric layer are sequentially formed. A bond pad is formed over the second interlayer dielectric layer in a second device region of the semiconductor structure. A passivation layer is formed over the bond pad and the second interlayer dielectric layer. A first etching process is performed to form a first opening in the first device region and a second opening in the second device region, wherein the first opening exposes a portion of the second interlayer dielectric layer over the fuse element and, and the second opening partially exposes a portion of the bond pad. A second etching process and a third etching process are performed to leave another passivation layer conformably covering the fuse element and the semiconductor structure adjacent thereto.

Abstract: Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.

Abstract: Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one embodiment, ends of the features are wider than middle regions of the features. During the pitch reduction process, spacer sidewalls formed between adjacent ends of the features come into substantial contact with one another, isolating the spaces between the features. In another embodiment, the features have a single width and an additional feature is located near ends of the features. Spacer sidewalls formed between adjacent features and the additional feature come into substantial contact with one another, isolating the spaces between the features.

Abstract: A method for fabricating a semiconductor device includes: providing a substrate structure in which a plurality of gate lines are already formed; forming a capping layer over the substrate structure; oxidizing the capping layer; and forming an insulation layer over the oxidized capping layer. The capping layer may include a nitride-based material. The insulation layer may include substantially the same material as the capping layer. The oxidizing of the capping layer may comprise performing a radical oxidation process.

Abstract: A method of formation of contacts with cobalt silicide since is disclosed. For example, after siliciding with the SOM solution, both unreacted sections of the deposition layer including, for example, cobalt as initial layer for the siliciding and an oxidation protection layer including titanium and deposited by means of cathode beam sputtering, for instance, may be removed rapidly and with high selectivity relative to the cobalt silicide and other, densified metal structures and metal layers.

Abstract: A semiconductor device is disclosed that includes multiple logic circuit cells having respective logic circuits formed therein; and multiple interconnects connected to the corresponding logic circuit cells. At least one of the interconnects has an opening formed therein so as to have an opening ratio different from one or more of the opening ratios of the remaining interconnects.

Abstract: A double processing technique for device manufacture includes performing a first patterning step to form apertures in a resist layer which apertures are filled before the first resist layer is stripped and replaced by a second resist layer to be used in the second exposure.

Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. In one embodiment, the method comprises forming metal plug contacts through a hard mask and a premetal dielectric to transistors in the semiconductor. The method also includes etching a hole for a through-hole via through the hard mask to the semiconductor using a patterned photoresist process, removing the patterned photoresist and using a hard mask process to etch the hole to an amount into the semiconductor. The method further includes depositing a dielectric liner to isolate the hole from the semiconductor, depositing a gapfill metal to fill the hole, and planarizing the surface of the substrate to the hard mask. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

Abstract: Methods are provided for etching during fabrication of a semiconductor device. The method includes initially etching to partially remove a portion of one or more lithographic-aiding layers overlying an oxide layer while etching a first portion of the oxide layer in accordance with a mask formed by the one or more lithographic-aiding layers, and thereafter additionally etching to remove remaining portions of the one or more lithographic-aiding layers while etching a remaining portion of the oxide layer.

Abstract: A memory cell includes a memory cell layer with a first dielectric layer over a bottom electrode layer, a second dielectric layer over the first dielectric layer, and a top electrode over the second dielectric layer. The dielectric layers define a via having a first part bounded by the first electrode layer and the bottom electrode and a second part bounded by the second dielectric layer and the top electrode. A memory element is within the via and is in electrical contact with the top and bottom electrodes. The first and second parts of the via may comprise a constricted, energy-concentrating region and an enlarged region respectively. The constricted region may have a width smaller than the minimum feature size of the process used to form the enlarged region of the via. A method for manufacturing a memory cell is also disclosed.

Abstract: Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a top surface and a width less than that of the base portion. A memory element is on the top surface of the pillar portion and comprises memory material having at least two solid phases. A top electrode is on the memory element.

Abstract: A method comprising: providing at least one first diamond film comprising polycrystalline diamond, e.g., nanocrystalline or ultrananocrystalline diamond, disposed on a substrate, wherein the first diamond film comprises a surface comprising diamond asperities and having a first diamond film thickness, removing asperities from the first diamond film to form a second diamond film having a second diamond film thickness, wherein the second thickness is either substantially the same as the first thickness, or the second thickness is about 100 nm or less thinner than the first diamond film thickness, optionally patterning the second diamond film to expose substrate regions and, optionally, depositing semiconductor material on the exposed substrate regions, and depositing a solid layer on the second diamond film to form a first layered structure.

Abstract: A method for fabricating sub-resolution features on an integrated circuit comprises depositing a hard mask layer on a dielectric layer of a semiconductor substrate, patterning the hard mask layer to form hard mask structures that define trenches, etching trenches in the dielectric layer through the hard mask structures, thereby forming a first set of dielectric structures on the substrate, depositing a conformal layer on the substrate and the first set of dielectric structures, etching the conformal layer to form spacers adjacent to the first set of dielectric structures, depositing a second dielectric layer within the trenches, thereby forming a second set of dielectric structures on the substrate, and etching the spacers to form sub-resolution trenches between the dielectric structures of the first and second set.

Abstract: The invention is directed to an alignment mark in a material layer in an alignment region of a wafer. The alignment mark comprises a plurality of sub-marks. Each of the sub-mark comprises a first element and a plurality of second elements. The second elements are embedded in the first element and a first top surface of the first element is at the same height as a second top surface of each of the second elements.

Abstract: A device includes a top layer having at least two opposing faces, and at least two epitaxially deposited layers, each of the at least two epitaxially deposited layers situated on a respective one of the at least two opposing faces, a combined thickness of the at least two epitaxially deposited layers tuning a gap between the at least two opposing faces.

Abstract: The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

Abstract: A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.

Abstract: CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.

Abstract: A surface-emitting type light-emitting diode includes a substrate, a p-n junction layer elevated on a portion of the substrate to emit light, and a first isolator layer formed on a sidewall of the p-n junction layer as well as a periphery portion of a top surface of the p-n junction layer except for a central region of the top surface.

Abstract: Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed.

Abstract: Method for manufacturing a hosting structure of nanometric elements comprising the steps of depositing on an upper surface of a substrate, of a first material, a block-seed having at least one side wall. Depositing on at least one portion of sad surface and on the block-seed a first layer, of predetermined thickness of a second material, and subsequently selectively and anisotropically etching it to form a spacer-seed adjacent to the side wall. The cycle of deposition and selective etching steps of a predetermined material are repeated n times (n?2), with at least one spacer formed in each cycle. This predetermined material is different for each pair of consecutive depositions. The above n steps provides at least one multilayer body. Further selective etching removes every other spacers to provide a plurality of nanometric hosting seats, which forms contact terminals for a plurality of molecular transistors hosted in said hosting seats.

Abstract: A liquid crystal display device, including: a gate line on a substrate; a data line crossing the gate line with a gate insulating film therebetween to define a pixel area; a thin film transistor connected to the gate line and the data line; a semiconductor pattern which forms a channel of the thin film transistor and overlaps along the data line; a passivation film covering the data line and the thin film transistor; and a pixel electrode on the gate insulating film in a pixel hole of the pixel area that penetrates the passivation film and connected to the thin film transistor, the pixel electrode on an inclined side surface of the passivation film to encompass the pixel hole, to form a border with the passivation film and having a thickness that decreases as it goes up the side surface of the passivation film.

Abstract: The present invention aims to improve the controllability of dimensions at the time when a silicon substrate or a film formed on top of the silicon substrate is etched. For this purpose, a SiN film is formed so as to be in contact with the top of an element-forming surface of a silicon substrate, and the SiN film is selectively removed to form an opening portion. Then, a plasma processing is carried out on the element-forming surface of the silicon substrate to remove deposits attached on sidewalls of the opening portion formed in the SiN film. After that, the silicon substrate is selectively removed by using the SiN film as a mask to form a concave portion in the silicon substrate.

Abstract: A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a metallic material formed within the via and on a surface of the insulator. The metallic material may be deposited on the surface and within the via. A hard mask of a flowable oxide is deposited over the metallic material in the via to protect the metallic material in the via. A subsequent dry sputter etch removes the metallic material from the surface of the insulator and a portion of the hard mask. After complete removal of the hard mask, a glass material is recessed over the metallic material in the via. Then, a layer of a metal-containing material is formed over the glass material. Finally, a second conductor is formed on the surface of the insulator.

Abstract: Methods are provided for fabricating memory devices. A method comprises fabricating charge-trapping stacks overlying a silicon substrate and forming bit line regions in the substrate between the charge trapping stacks. Insulating elements are formed overlying the bit line regions between the stacks. The charge-trapping stacks are etched to form two complementary charge storage nodes and to expose portions of the silicon substrate. Silicon is grown on the exposed silicon substrate by selective epitaxial growth and is oxidized. A control gate layer is formed overlying the complementary charge storage nodes and the oxidized epitaxially-grown silicon.

Abstract: A method for forming a structured tungsten layer and a method for forming a semiconductor device using the same. A first tungsten layer is formed with an atomic layer deposition (ALD) method. A second tungsten layer is formed on the first tungsten layer with a chemical vapor deposition (CVD) method. A third tungsten layer is formed on the second tungsten layer with the ALD method to complete the structured tungsten layer.

Abstract: A gap-filling method of a semiconductor device is realized without voids by providing the optimal deposition conditions based on DED conditions related to etching time, etching number and RF frequency. The method includes (a) depositing a first high-density plasma oxide film to fill some of a gap; (b) etching some of the first high-density plasma oxide film; (c) performing a gap-filling process by depositing a second high-density plasma oxide film on the first high-density plasma oxide film; and (d) repeating the sequential steps of (a), (b) and (c) three times.

Abstract: A method for forming a MEMS device using an amorphous silicon layer as a release layer includes etching superjacent films and using the amorphous silicon layer as an etch stop layer. The amorphous silicon layer is resistant to attack during the post-etch solvent stripping operation due to the oxidation of exposed portions of the amorphous silicon layer by use of an oxygen plasma.

Abstract: In one embodiment, a preliminary insulation layer is formed over a cell region and a peripheral circuit region of a semiconductor substrate. The preliminary insulation layer covers a capacitor formed over the cell region. The preliminary insulation layer over the cell region has a first height higher than a second height of the preliminary insulation layer over the peripheral circuit region. A preliminary node separate polymer layer is formed over the preliminary insulation layer. A portion of the preliminary node separate polymer layer is uniformly removed by a developing process to form a node separate polymer layer exposing the preliminary insulation layer over the cell region. A portion of the preliminary insulation layer over the cell region is removed to form an insulation layer.

Abstract: A memory cell includes a first electrode and a second electrode forming an opening. The opening is defined by a first sidewall, a second sidewall, and a surface extending between the first sidewall and the second sidewall. The memory cell includes phase change material contacting the first electrode and the first sidewall and the second sidewall. The memory cell includes isolation material electrically isolating the phase change material from the surface extending between the first sidewall and the second sidewall.

Abstract: This disclosure describes system(s) and/or method(s) enabling contacts for individual nanometer-scale-thickness layers of a multilayer film.

Abstract: Methods for improving within wafer and wafer to wafer yields during fabrication of notched trailing shield structures are disclosed. Ta/Rh CMP stop layers are deposited prior to planarization and notch formation to ensure a planar surface for trailing shield structures. These stop layers may be blanket deposited or patterened prior to CMP. Patterned stop layers produce the highest yields.

Abstract: A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist pattern over an etch target layer, forming a first hard mask layer over a substrate structure, planarizing the first hard mask layer to form a first hard mask pattern and expose the first photoresist pattern, removing the first photoresist pattern, forming a second photoresist pattern enclosing the first hard mask pattern, forming a second hard mask layer over the substrate structure, planarizing the second hard mask layer to form a second hard mask pattern and expose the first hard mask pattern, removing the second photoresist pattern, and etching the etch target layer using the first hard mask pattern and the second hard mask pattern.

Abstract: A method of fabricating a semiconductor device including at least one of the following steps: forming an oxide layer on and/or over a silicon substrate. Forming a first photoresist pattern on and/or over the oxide layer. Forming a trench by etching the oxide layer and the substrate using the first photoresist pattern as a mask. Removing the first photoresist pattern. Filling the trench with a trench oxide layer. Planarizing the trench oxide layer. Forming an etch stop layer on and/or over the trench oxide layer. Forming a second photoresist pattern on and/or over the etch stop layer. Etching the etch stop layer and the trench oxide layer using the second photoresist pattern as an etch mask. Removing the second photoresist pattern and the etch stop layer.

Abstract: By performing a planarization process, for instance based on a planarization layer, prior to forming a resist mask for selectively removing a portion of a stressed contact etch stop layer, the strain-inducing mechanism of a subsequently deposited further contact etch stop layer may be significantly improved.

Abstract: A method for forming a fine pattern of a semiconductor device overcomes resolution limits of exposure equipment. The method includes forming a first photoresist pattern over an underlying layer formed over a semiconductor substrate. An amorphous carbon film and a second photoresist film are sequentially deposited over the first photoresist pattern. The second photoresist film and the amorphous carbon film are planarized to expose the first photoresist pattern. A thick portion and a thin portion of the amorphous carbon film is formed. The first photoresist pattern and the second photoresist film are removed. Etching is performed on the thin portion of the amorphous carbon film and the underlying layer using the thick portion of the amorphous carbon film as an etch mask. The thick portion of the amorphous carbon film is removed to expose a fine pattern of the underlying layer.

Abstract: A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and forming a control gate over the second dielectric layer. The method further includes depositing an interlayer dielectric over the control gate at a high temperature.

Abstract: Embodiments of the present invention provide methods to reduce the copper line roughness for increased electrical conductivity in narrow interconnects having a width of less than 100 nm. These methods reduce the copper line roughness by first smoothing the surface on which the copper lines are formed by performing a short electrochemical etch of the surface. The electrical conductivity of the interconnects is increased by reducing the copper line roughness that in turn reduces the resistivity of the copper lines.

Abstract: The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a pad stack atop the SOI layer; forming a block mask having a channel via atop the pad stack; providing a localized oxide region in the SOI layer on top of the buried insulating layer thereby thinning a portion of the SOI layer, the localized oxide region being self-aligned with the channel via; forming a gate in the channel via; removing at least the block mask; and forming source/drain extensions in the SOI layer abutting the thinned portion of the SOI layer. Providing the localized oxide region further comprises implanting oxygen dopant through the channel via into a portion of the SOI layer; and annealing the dopant to create the localized oxide region.

Abstract: Processing problems associated with porous low-k dielectric materials are often severe. Exposure of low-k materials to plasma during feature etching, ashing, and priming steps has deleterious consequences. For porous, silicon-based low-k dielectric materials, the plasma depletes a surface organic group, raising the dielectric constant of the material. In the worst case, the damaged dielectric is destroyed during the wet etch removal of the antireflective coating in the via-first copper dual-damascene integration scheme. This issue is addressed by exposing the dielectric to silane coupling agents at various stages of etching and cleaning. Chemical reactions with the silane coupling agent both replenish the dielectric surface organic group and passivate the dielectric surface relative to the surface of the antireflective coating.

Abstract: A magnetic head according to one embodiment includes a pole piece made of a magnetic material; one or more magnetic pedestals formed over the pole piece; an insulator material formed over the pole piece adjacent the magnetic pedestals; and one or more polymer layers formed over tops of the insulator material to form a substantially planar top surface with the magnetic pedestals.

Abstract: An active layer of a P-type low temperature polysilicon thin film transistor and a bottom electrode of a storage capacitor are first formed. Then, a P-type source/drain is formed and the bottom electrode is doped with dopants. A gate insulator, a gate electrode, a capacitor dielectric, and a top electrode are thereafter formed. Finally, a source interconnect, a drain interconnect, and a pixel electrode of the liquid crystal display are formed.

Abstract: A system for dished metal redevelopment by providing a metal deposition solution at an interface between a moving semiconductor wafer and a moving polishing pad, which deposits metal onto dished metal in trenches in a layer of an interlayer dielectric; and by polishing the wafer with a relatively reduced polishing pressure to polish metal being deposited. A polishing fluid is disclosed for use in a CMP polishing system, the polishing fluid being a metal deposition solution for dished metal redevelopment.

Abstract: Plasma etch processes incorporating etch chemistries which include hydrogen. In particular, high density plasma chemical vapor deposition-etch-deposition processes incorporating etch chemistries which include hydrogen that can effectively fill high aspect ratio (typically at least 3:1, for example 6:1, and up to 10:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps while reducing or eliminating chamber loading and redeposition and improving wafer-to-wafer uniformity relative to conventional deposition-etch-deposition processes which do not incorporate hydrogen in their etch chemistries.

Abstract: Processes for fabricating a semiconductor device are described herein. In one aspect of the invention, an exemplary process includes forming an interface layer overlying the device substrate, forming a silver layer overlying the interface layer, annealing the substrate to form an intermetallic layer between the silver layer and the interface layer, the silver layer is in intimate contact with the intermetallic layer, and forming a protection layer overlying the silver layer. Other interconnect structures and processes are also described.

Abstract: A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator through which a via extends has a metallic material formed within the via and on a surface of the insulator. The metallic material may be deposited on the surface and within the via. A hard mask of a flowable oxide is deposited over the metallic material in the via to protect the metallic material in the via. A subsequent dry sputter etch removes the metallic material from the surface of the insulator and a portion of the hard mask. After complete removal of the hard mask, a glass material is recessed over the metallic material in the via. Then, a layer of a metal-containing material is formed over the glass material. Finally, a second conductor is formed on the surface of the insulator.

Abstract: Surface planarization processes for the fabrication of magnetic heads and semiconductor devices are described herein. In one illustrative example, magnetic structures are formed over a substrate and insulator materials are deposited over and around the magnetic structures. A chemical mechanical polishing (CMP) is performed to remove top portions of the insulator materials and to expose the tops of the magnetic structures, such that the tops of the magnetic and insulator materials form a top surface. Due to the different CMP removal rates of the materials, small surface “steps” are formed along the top surface between the materials. To eliminate or reduce these steps, polymer materials (e.g. polystyrene or PMMA) are formed to selectively bond with the tops of the insulator materials to a sufficient thickness so that a substantially planar top surface is formed with tops of the magnetic materials.

Abstract: A method of fabrication of a semiconductor integrated circuit device, including polishing the entire area of an edge of a wafer, for example, uses three polishing drums in which a polishing drum polishes the upper surface of the edge of the water, a polishing drum polishes the central portion of the edge of the wafer and a polishing drum polishes the lower surface of the edges of the wafer, thereby preventing occurrence of obstacles which cause defoliation of thin films on the edge of the wafer.

Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer for forming the opening.