Plural Coating Steps Patents (Class 438/699)
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Patent number: 6943118Abstract: In a method of fabricating a flash memory, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on a substrate to form a gate structure. Buried source/drain regions are then formed in the substrate between the strips. The strips are further patterned into floating gate structures. An insulation layer is formed sideways adjacent to the gate structure. The insulation layer has a top surface lower than a top surface of the first conductive layer of the gate structure. The mask layer is removed, and an additional conductive layer is formed on the first conductive layer in a manner to extend over the adjacent insulation layer. The first and additional conductive layers form a floating gate. A gate dielectric layer is formed on the floating gate, and a control gate is formed on the gate dielectric layer.Type: GrantFiled: September 18, 2003Date of Patent: September 13, 2005Assignee: Macronix International Co., Ltd.Inventors: Kuang-Chao Chen, Jui-Lin Lu, Ling-Wuu Yang
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Patent number: 6924238Abstract: A new method and structure is provided for the polishing of the surface of a layer of low-k dielectric material. Low-k dielectric material of low density and relatively high porosity is combined with low-k dielectric material of high density and low porosity whereby the latter high density layer is, prior to polishing of the combined layers, deposited over the former low density layer. Polishing of the combined layers removes flaking of the polished low-k layers of dielectric. This method can further be extended by forming conductive interconnects through the layers of dielectric, prior to the layer of dielectric.Type: GrantFiled: June 5, 2003Date of Patent: August 2, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Jen Chou, Syun-Ming Jang, Ying-Ho Chen, Shen-Nan Lee
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Patent number: 6921718Abstract: A semiconductor device includes a semiconductor substrate and an electrode disposed on a major surface of the semiconductor substrate. A via hole is formed on a center of the electrode so as to open from a surface of the electrode to a place under the surface of the semiconductor substrate. A via-hole foundation electrode for inhibiting diffusion from a metal layer is formed inside the via hole and on the surface of the electrode, a via-hole electrode is formed on the surface of the via-hole foundation electrode. A back via hole is formed on the back of the semiconductor substrate opposite to the major surface thereof, and opened from the back of the semiconductor substrate to the via-hole electrode. A back via-hole electrode is formed on the back of the semiconductor substrate including the inside of the back via hole.Type: GrantFiled: April 8, 2003Date of Patent: July 26, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Naoto Andoh, Takao Ishida, Kenji Hosogi
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Patent number: 6913993Abstract: A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 ? can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent.Type: GrantFiled: November 20, 2001Date of Patent: July 5, 2005Assignee: United Microelectronics Corp.Inventors: Kun-Lin Wu, Meng-Jin Tsai
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Patent number: 6905975Abstract: The invention includes methods by which the size and shape of photoresist-containing masking compositions can be selectively controlled after development of the photoresist. For instance, photoresist features can be formed over a substrate utilizing a photolithographic process. Subsequently, at least some of the photoresist features can be exposed to actinic radiation to cause release of a substance from the photoresist. A layer of material is formed over the photoresist features and over gaps between the features. The material has a solubility in a solvent which is reduced when the material interacts with the substance released from the photoresist. The solvent is utilized to remove portions of the material which are not sufficiently proximate to the photoresist to receive the substance, selectively relative to portions which are sufficiently proximate to the photoresist. The photoresist features can be exposed to the actinic radiation either before or after forming the layer of material.Type: GrantFiled: July 3, 2003Date of Patent: June 14, 2005Assignee: Micron Technology, Inc.Inventors: Ulrich C. Boettiger, Scott L. Light
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Patent number: 6884724Abstract: Methods and apparatus for planarizing a substrate surface are provided. In one aspect, a method is provided for planarizing a substrate surface including polishing a first conductive material to a barrier layer material, depositing a second conductive material on the first conductive material by an electrochemical deposition technique, and polishing the second conductive material and the barrier layer material to a dielectric layer. In another aspect, a processing system is provided for forming a planarized layer on a substrate, the processing system including a computer based controller configured to cause the system to polish a first conductive material to a barrier layer material, deposit a second conductive material on the first conductive material by an electrochemical deposition technique, and polish the second conductive material and the barrier layer material to a dielectric layer.Type: GrantFiled: August 24, 2001Date of Patent: April 26, 2005Assignee: Applied Materials, Inc.Inventors: Wei-Yung Hsu, Liang-Yuh Chen, Ratson Morad, Daniel A. Carl
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Patent number: 6872664Abstract: A method of manufacturing a semiconductor device includes providing a wafer substrate having a surface, forming a first nitride layer over the wafer substrate, providing a layer of photoresist over the first nitride layer, patterning and defining the photoresist layer, etching the first nitride layer unmasked by the photoresist to remove at least a portion of the first nitride layer to expose at least a portion of the substrate surface, removing the photoresist layer, and depositing a second nitride layer over the first nitride layer and the exposed substrate surface to form a nitride structure having a first thickness and a second thickness, wherein the first thickness includes a thickness of the first nitride layer.Type: GrantFiled: June 23, 2003Date of Patent: March 29, 2005Assignee: ProMOS Technologies, Inc.Inventor: Yung Hsien Wu
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Patent number: 6867139Abstract: A semiconductor device manufacturing method wherein a via-hole is formed in an second inter-layer insulating film covering a lower layer wiring, throughout a surface of which are then formed a barrier film made of Ta (tantalum) and a Cu (copper) film sequentially, after which, first an unnecessary part of the Cu film is removed by a CMP (Chemical Mechanical Polishing) method using such a polishing liquid to which hydrogen peroxide is added by 1.5 weight-percent or more (first polishing step) and then an unnecessary part of the barrier film is removed by a CMP method for using a polishing liquid to which hydrogen peroxide is added by 0.09-1.5 weight-percent and applying a pressure of 4-10 Psi (pounds per square inch) on the barrier film (second polishing step).Type: GrantFiled: June 5, 2002Date of Patent: March 15, 2005Assignee: NEC CorporationInventor: Tomoko Wake
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Patent number: 6864179Abstract: A fabrication method for forming a semiconductor device having COB (capacitor-over-bit line) structure is provided. A lower insulating film is formed on a substrate. Bit line patterns are formed on a portion of the lower insulating film. Each of the bit line patterns comprises a conductive bit line, a lower capping strip and an upper capping strip, which are sequentially stacked. Mask-defining layer is formed on the other portion of the lower insulating film. The upper capping strips are removed by wet etching technique to form a recess region. The lower capping strips and a portion of the mask-defining layer is etched isotropically to enlarge the recess region. An insulating mask is formed in the enlarged recess region. BC (buried contact) holes are formed substantially in self-aligned manner to the bit lines by using the mask as an etch mask. According to the present invention, the unfavorable electrical contact between the storage electrodes and the bit lines can be significantly relieved.Type: GrantFiled: July 17, 2002Date of Patent: March 8, 2005Assignee: Samsung Electronics Co., Ltd.Inventor: Byung-Jun Park
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Patent number: 6855634Abstract: A polishing method able to easily flatten unevenness formed on the surface of a film to be polished and able to efficiently polish the film flat while suppressing damage to an interlayer insulating film below the film, comprising, when polishing an object having a film such as an interconnection layer formed burying interconnection grooves formed in an insulating film of a substrate, supplying a polishing solution over the surface to be polished at least substantially parallel to the surface to preferentially remove by polishing the projecting portions of the film and flatten the surface by the shear stress of the processing solution or arranging a cathode member facing the surface and supplying an electrolytic solution containing a chelating agent between the surface and cathode member while supplying voltage between the film and the cathode member to preferentially remove by polishing the projecting portions of the film and flatten the surface by the shear stress of the electrolytic solution, and a polishinType: GrantFiled: September 26, 2001Date of Patent: February 15, 2005Assignee: Sony CorporationInventors: Shuzo Sato, Yuji Segawa, Akira Yoshio, Takeshi Nogami
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Patent number: 6833232Abstract: Disclosed is a micro-pattern forming method for a semiconductor device comprising: sequentially forming first and second insulation films on a semiconductor substrate; forming a photosensitive film on the second insulation film; dry etching the second insulation film; removing the photosensitive film; forming a third insulation film on the substrate; forming a fourth insulation film on a resultant structure; etching the third and fourth insulation films using a proper formal solution; etching the third insulation film using the fourth and second insulation films as masks to form a third insulation film pattern; and filling a conductive film into spaces between the second and third insulation films and second flattening the conductive film to form conductive lines.Type: GrantFiled: January 8, 2003Date of Patent: December 21, 2004Assignee: Dongbu Electronics Co., Ltd.Inventor: Cheol Soo Park
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Patent number: 6821872Abstract: A method for making a bit line contact on a substrate is provided. Two gate conductor stacks are formed on a main surface of the substrate in close proximity to each other. A bit line contact forming area is defined above the area between the two gate conductor stacks. A silicon dioxide lining film is deposited on a top surface and sidewalls of the gate conductor stacks. A sacrificing layer is deposited on the silicon dioxide lining film. The sacrificing layer is then polished to expose the top surface of the gate conductor stacks. A spin-on-glass (SOG) film is then coated on the sacrificing layer. A resist pattern masking the bit line contact forming area is formed on the SOG film. The un-masked SOG film, sacrificing layer and silicon dioxide lining film are etched away. A silicon nitride thin film is deposited on the remaining SOG film. A BPSG layer is deposited on the silicon nitride thin film and is then polished to expose the SOG layer.Type: GrantFiled: June 2, 2004Date of Patent: November 23, 2004Assignee: Nanya Technology Corp.Inventors: Chien-Mao Liao, Shing-Yih Shih, Chang-Rong Wu
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Patent number: 6812115Abstract: The filling of sub-0.25 &mgr;m trenches with dielectric material may lead to the formation of a void. Typically, the void may be closed by oxidation. When the trench includes non-oxidizable sidewall portions, insufficient closure may result. Therefore, an oxidizable spacer layer is conformally deposited prior to depositing the bulk dielectric, so that the sidewalls of the trench may be oxidized along the entire depth of the trench, thereby allowing the complete closure of the void.Type: GrantFiled: March 31, 2003Date of Patent: November 2, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Karsten Wieczorek, Stephan Kruegel, Michael Raab
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Patent number: 6809032Abstract: In another aspect of the present invention, a system for detecting an endpoint in a polishing process is provided. The system comprises a polishing tool, a controllable light source, a sensor, and a controller. The polishing tool is capable of polishing a surface of a semiconductor device, wherein the semiconductor device includes a first layer comprised of a first material and a second layer comprised of a second material. The first layer is positioned above the second layer. The controllable light source is capable of delivering light having one of a plurality of a preselected frequencies to the surface of the semiconductor device. The sensor is capable of detecting the light reflected from the surface of the semiconductor device.Type: GrantFiled: May 1, 2002Date of Patent: October 26, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Frank Mauersberger, Peter J. Beckage, Paul R. Besser, Frederick N. Hause, Errol Todd Ryan, William S. Brennan, John A. Iacoponi
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Patent number: 6784077Abstract: A method of forming a silicon oxide, shallow trench isolation (STI) region, featuring a silicon rich, silicon oxide layer used to protect the STI region from a subsequent wet etch procedure, has been developed. The method features depositing a silicon oxide layer via PECVD procedures, without RF bias, using a high silane to oxygen ratio, resulting in a silicon rich, silicon oxide layer, located surrounding the STI region. The low etch rate of the silicon rich, silicon oxide layer, protect the silicon oxide STI region from buffered hydrofluoric wet etch procedures, used for removal of a dioxide pad layer.Type: GrantFiled: October 15, 2002Date of Patent: August 31, 2004Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Shih-Chi Lin, Chih Chung Lee, Guey Bao Huang, Szu-An Wu, Ying Lang Wang, Chun Chun Yeh
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Patent number: 6780774Abstract: Disclosed herein is a method of semiconductor device isolation, which forms a device isolation film on an isolation region of a substrate using a trench process. The method comprises the steps of providing a semiconductor substrate where a device isolation region was defined; forming a mask on the substrate in such a manner that the device isolation region is exposed through the mask; etching the substrate using the mask to form a trench; thermally treating an inner wall of the trench using the mask under a hydrogen atmosphere; forming a first insulating layer covering the resulting inner wall of the trench; forming a second insulating layer on the mask in such a manner that the second insulating film covers the first insulating film; firstly etching the second insulating layer to expose a surface of the mask; removing the mask; secondly etching the remaining second insulating layer until a surface of the substrate is exposed, thereby forming a device isolation film.Type: GrantFiled: December 21, 2001Date of Patent: August 24, 2004Assignee: Hynix Semiconductor Inc.Inventor: Jae Soon Kwon
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Patent number: 6774045Abstract: This invention relates to a method for reducing halogen gasses and byproducts in post-etch applications. The method consists of exposing the substrate to O2/N2 plasma and water vapor in a process chamber.Type: GrantFiled: July 2, 2002Date of Patent: August 10, 2004Assignee: Lam Research CorporationInventors: Shenjian Liu, Gregory James Goldspring
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Patent number: 6774042Abstract: A method of planarizing wafers using shallow trench isolation is described. The method uses a very hard polishing pad and chemical mechanical polishing with no additional etching required. Trenches are formed in a substrate and filled with a trench dielectric, such as silicon dioxide deposited using high density plasma chemical vapor deposition. A layer of resist is then formed on the layer of trench dielectric. The wafer is then planarized using chemical mechanical polishing and a polishing pad having a hardness of at least Shore “D” 52. The hard polishing pad avoids scratch marks on the trench dielectric, the substrate surface, or any other materials deposited on the substrate surface.Type: GrantFiled: February 26, 2002Date of Patent: August 10, 2004Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chia-Der Chang, Yi-Tung Yen
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Patent number: 6759319Abstract: A new method of fabricating solder bumps in the manufacture of an integrated circuit device has been achieved. Contact pads are provided overlying a semiconductor substrate. A passivation layer is provided overlying the contact pads. The passivation layer has openings that expose a top surface of the contact pads. A sacrificial layer is deposited overlying the passivation layer and the exposed top surface of the contact pads. The sacrificial layer is not wettable to solder. Under bump metallurgy (UBM) caps may be formed either by deposition and patterning of a UBM layer stack or by selective electroless deposition of a material such as nickel and gold. An aperture mask is formed overlying the sacrificial layer. The aperture mask has openings that expose a part of the sacrificial layer overlying the contact pads. A solder layer is printed into the openings in the aperture mask. The solder layer is reflowed to form solder bumps overlying the contact pads. The aperture mask is stripped away.Type: GrantFiled: May 17, 2001Date of Patent: July 6, 2004Assignee: Institute of MicroelectronicsInventors: Gautham Viswanadam, Chee Chong Wong
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Patent number: 6750148Abstract: A method of manufacturing a wireless suspension blank wherein three-layered laminate formed of a metallic layer having a spring property and a conductive layer laminated on the metallic layer through an electrically insulating layer are used. The laminate used is a laminate in which an insulating layer is formed of a core-insulating layer and adhesive layers laminated on both sides of the core-insulating layer, and the ratio of higher etching rate to lower etching rate of the respective layers of the insulating layer is between 6:1 and 1:1. The metallic layer and the conductive layer are processed by the photo etching method. The insulating layer is processed by the wet etching method.Type: GrantFiled: July 6, 2001Date of Patent: June 15, 2004Assignee: Dainippon Printing Co., Ltd.Inventors: Katsuya Sakayori, Shigeki Kawano, Hiroko Amasaki, Kazuo Umeda, Satoshi Sasaki, Hiroshi Yagi
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Patent number: 6746888Abstract: A transmission type display includes a thin film transistor for driving a pixel electrode, which transistor is provided on a substrate, and a conductive shield layer provided at a position over the thin film transistor and under the pixel electrode. A first planarization film is formed to bury an irregular contour of the thin film transistor and the shield layer is disposed on the planarized surface of the first planarization film, and a second planarization film is formed to bury steps of the shield layer, and the pixel electrode is disposed on the planarized surface of the second planarization film. Since the transmission type display has the structure in which the conductive shield layer is put between the upper second planarization film and the lower first planarization film each of which is made from an insulating material, the shielding performance and the alignment characteristic of the display can be improved.Type: GrantFiled: September 30, 2002Date of Patent: June 8, 2004Assignee: Sony CorporationInventors: Makoto Hashimoto, Hisashi Kadota, Hirohide Fukumoto, Takusei Sato
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Patent number: 6746960Abstract: Techniques are used to detect and identify analytes. Techniques are used to fabricate and manufacture sensors to detect analytes. An analyte (1810) is sensed by sensors (1820) that output electrical signals in response to the analyte. The electrical signals are preprocessed (1830) by filtering and amplification. In an embodiment, this preprocessing includes adapting the sensor and electronics to the environment in which the analyte exists. The electrical signals are further processed (1840) to classify and identify the analyte, which may be by a neural network.Type: GrantFiled: January 18, 2002Date of Patent: June 8, 2004Assignee: California Institute of TechnologyInventor: Rodney M. Goodman
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Patent number: 6734105Abstract: A method for forming silicon quantum dots and a method for fabricating a nonvolatile memory device using the same, suitable for high speed and high packing density. The method for forming silicon quantum dots includes the steps of forming a first insulating film on a semiconductor substrate, forming a plurality of nano-crystalline silicons on the first insulating film, forming a second insulating film on the first insulating film including the nano-crystalline silicons, partially etching the second insulating film and the nano-crystalline silicons, and oxidizing surfaces of the nano-crystalline silicons.Type: GrantFiled: November 15, 2001Date of Patent: May 11, 2004Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Il Gweon Kim
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Patent number: 6730603Abstract: The present invention provides a polishing endpoint detection system, for use with a polishing apparatus, a method of determining a polishing endpoint of a surface located on a semiconductor wafer, and a method of manufacturing an integrated circuit on a semiconductor wafer. In one embodiment, the polishing endpoint detection system includes a carrier head having a polishing platen associated therewith. Also, the detection system includes a signal emitter located adjacent one of the carrier head or polishing platen. The signal emitter is configured to generate an emitted signal capable of traveling through an object to be polished. In addition, the detection system includes a signal receiver located adjacent another of the carrier head or polishing platen. The signal receiver is configured to receive the emitted signal from which a change in a signal intensity of the emitted signal can be determined.Type: GrantFiled: October 25, 2001Date of Patent: May 4, 2004Assignee: Agere Systems Inc.Inventors: Annette M. Crevasse, William G. Easter, Frank Miceli, Yifeng Winston Yang
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Patent number: 6716769Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.Type: GrantFiled: December 22, 1999Date of Patent: April 6, 2004Assignee: Micron Technology, Inc.Inventors: Thomas A. Figura, Kevin G. Donohoe, Thomas Dunbar
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Patent number: 6706635Abstract: The present invention relates to a method for forming an anlog capacitor on a semiconductor substrate. The method comprises forming a field oxide over a portion of the substrate, and forming a polysilicon layer over the field oxide layer, and subsequently forming a silicide over the polysilicon layer. A first interlayer dielectric layer is formed over the substrate, and a capacitor masking pattern is formed. The first interlayer dielectric is etched using the capacitor masking pattern as a mask and the silicide layer as an etch stop, and a thin dielectric is formed over the substrate. A contact masking pattern is formed over the substrate, and a subsequent etch is performed on the thin dielectric and the first interlayer dielectric using the silicide and substrate as an etch stop. A metal layer is deposited over the substrate, and is subsequently planarized, thereby defining an analog capacitor.Type: GrantFiled: June 5, 2002Date of Patent: March 16, 2004Assignee: Texas Instruments IncorporatedInventors: Imran M. Khan, William E. Nehrer, James Todd, Weidong Tian, Louis N. Hutter
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Patent number: 6703314Abstract: Provided is a method for forming a self aligned contact (SAC) of a semiconductor device that can minimize the loss of gate electrodes and hard mask. The method includes the steps of: providing a semiconductor substrate on which a plurality of conductive patterns are formed; forming a first insulation layer along the profile of the conductive patterns on the substrate; forming a second insulation layer on the substrate and simultaneously forming voids between the conductive patterns; forming a third insulation layer on the first insulation layer; and forming contact holes that expose the surface of the substrate between the conductive patterns by etching the third insulation layer and the second insulation layer covering the voids.Type: GrantFiled: December 3, 2002Date of Patent: March 9, 2004Assignee: Hynix Semiconductor Inc.Inventors: Sung-Kwon Lee, Sang-Ik Kim, Chang-Youn Hwang, Weon-Joon Suh, Min-Suk Lee
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Patent number: 6682820Abstract: A recession resistant coated ceramic part. The ceramic part has a ceramic substrate and a recession resistant coating disposed on the substrate. The coating includes a plurality of layers diffusion bonded to each other and to the substrate respectively. The top most layer is characterized by a greater resistance to recession due to oxidation than that of the substrate.Type: GrantFiled: October 31, 2002Date of Patent: January 27, 2004Assignee: Saint-Gobain Ceramics & Plastics, Inc.Inventor: Vimal K. Pujari
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Patent number: 6677227Abstract: A metalization process forms metal contacts having defined profiles for contact between microelectromechanical (MEMS) devices or chemical sensors with semiconductor devices. Gold contacts may be used for connecting the MEMS devices or chemical sensors to integrated CMOS devices. Gold contacts are deposited over a photoresist via having sidewalls for forming upwardly extending flanges. The metal contacts to the underlying semiconductor device, are formed using a polymethylmethacrylate (PMMA) etch back process for exposing and dissolving the gold metalization layer save the metal contact under a surviving portion of the etched back PMMA layer in a dimple of the gold layer over the photoresist via. The photoresist layer serves to form deep well gold contacts having upwardly extending flanges for connection to the MEMS devices or chemical sensors and to the integrated semiconductor devices.Type: GrantFiled: May 21, 2001Date of Patent: January 13, 2004Assignee: The Aerospace CorporationInventors: James S. Swenson, Robert C. Cole
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Patent number: 6670274Abstract: A method of forming a planarized final copper structure including the following steps. A structure is provided having a patterned dielectric layer formed thereover. The patterned dielectric layer having an opening formed therein. A barrier layer is formed over the patterned dielectric layer, lining the opening. An initial planarized copper structure is formed within the barrier layer lined opening, and is planar with the barrier layer overlying the patterned dielectric layer. The initial planarized copper structure is recessed below the barrier layer overlying the patterned dielectric layer a distance to form a recessed copper structure. Any copper oxide formed upon the recessed copper structure is removed. A conductor film is formed over the recessed, copper oxide-free initial copper structure and the barrier layer.Type: GrantFiled: October 1, 2002Date of Patent: December 30, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chi-Wen Liu, Ying-Lang Wang
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Patent number: 6660641Abstract: Within a method for forming a planarizing layer within a microelectronic fabrication, there is employed formed upon a partially photoexposed planarizing layer formed of a partially photoexposed negative photoresist material a sacrificial layer. Within the method, when sequentially: (1) stripping from the partially photoexposed planarizing layer the sacrificial layer; and (2) developing the partially photoexposed planarizing layer to form a developed planarizing layer, the developed planarizing layer is formed with enhanced planarity and diminished thickness.Type: GrantFiled: July 5, 2002Date of Patent: December 9, 2003Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin Chen Kuo, Sheng Liang Pan, Yu-Kung Hsiao, Chih-Kung Chang, Fu-Tien Wong, Chung Sheng Hsiung
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Patent number: 6660618Abstract: Excessive variation in vertical (i.e., inter-level) capacitance of multi-level metallization semiconductor devices resulting in racing of clock skew circuitry of finished devices, and over-etching of borderless vias leading to inter-level short-circuits, are simultaneously eliminated, or substantially reduced, by selectively providing an etch-resistant masking material at thinner, i.e., recessed, portions of a first, low k gap fill material blanket-deposited over spaced-apart features of a metallization pattern and in the spaces therebetween. The surfaces of thicker, non-recessed portions thereof are etched so as to be substantially co-planar with the feature surfaces and the recessed portions. The etch-resistant mask is then removed, and second, oxide-based and third, low k dielectric layers deposited over the planarized surface.Type: GrantFiled: August 17, 2000Date of Patent: December 9, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Susan H. Chen, Paul R. Besser
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Publication number: 20030203515Abstract: A method for reducing preferential chemical mechanical polishing (CMP) of a silicon oxide filled shallow trench isolation (STI) feature during an STI formation process including providing a semiconductor wafer having a process surface including active areas for forming semiconductor devices thereon; forming a silicon oxynitride layer over the process surface for photolithographically patterning STI trenches around the active areas; photolithographically patterning STI trenches around the active areas for anisotropic etching; anisotropically etching the STI trenches extending through the silicon oxynitride layer into the semiconductor wafer; depositing a silicon oxide layer over the silicon oxynitride layer to include filling the STI trenches; and, performing a CMP process to remove the silicon oxide layer overlying the silicon oxynitride layer to reveal an upper surface of the silicon oxynitride layer.Type: ApplicationFiled: April 29, 2002Publication date: October 30, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Keng-Chu Lin, Chih-Ta Wu
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Patent number: 6627551Abstract: This invention discloses a method for avoiding microscratch in interlevel dielectric layer chemical mechanical polishing process. There is step height difference on surface of the interlevel dielectric layer between the memory array and the logic device, so, the interlevel dielectric layer over the memory array is etched to form a sidewall and a corner. As a key step of this invention, a dielectric layer is capped over the interlevel dielectric layer to smooth the corner and avoid microscratch thereon when performing chemical mechanical polishing process.Type: GrantFiled: June 6, 2001Date of Patent: September 30, 2003Assignee: United Microelectronics Corp.Inventor: Wei-Wu Liao
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Publication number: 20030180669Abstract: Disclosed is a micro-pattern forming method for a semiconductor device comprising: sequentially forming first and second insulation films on a semiconductor substrate; forming a photosensitive film on the second insulation film; dry etching the second insulation film; removing the photosensitive film; forming a third insulation film on the substrate; forming a fourth insulation film on a resultant structure; etching the third and fourth insulation films using a proper formal solution; etching the third insulation film using the fourth and second insulation films as masks to form a third insulation film pattern; and filling a conductive film into spaces between the second and third insulation films and second flattening the conductive film to form conductive lines.Type: ApplicationFiled: January 8, 2003Publication date: September 25, 2003Inventor: Cheol Soo Park
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Patent number: 6617241Abstract: Planarization of the top surfaces of layers that are more than about a micron thick is beset with problems not encountered in thinner layers. These problems have been overcome by means of a process that, initially allows the formation of ‘horns’ in the surface that is to be planarized. Said horns are then selectively etched away while other parts of the surface are protected, following which CMP is initiated and the surface gets planarized. A total of four embodiments are disclosed.Type: GrantFiled: January 15, 2003Date of Patent: September 9, 2003Assignee: Institute of MicroelectronicsInventor: My The Doan
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Publication number: 20030157808Abstract: Photoresist reflow for an enhanced process window for non-dense contacts is disclosed. A corrective bias is determined for application to each of a number of contacts at different pitches, to achieve a substantially identical critical dimension for each contact. The corrective bias is determined based on a first and a second critical dimension for each contact, where the first critical dimension is before photoresist reflow, and potentially inclusive of optical proximity effects, and the second critical dimension is after photoresist reflow. A photomask is then constructed for a semiconductor design that incorporates the corrective bias that has been determined for the contacts of the design. Lithographical processing of the semiconductor design on a semiconductor wafer using thus photomask, and subsequent photoresist reflow, thus achieves a substantially identical critical dimension for each of the contacts of the semiconductor design.Type: ApplicationFiled: February 16, 2002Publication date: August 21, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huan-Tai Lin, Shinn-Sheng Yu, Anthony Yen
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Patent number: 6596639Abstract: The present invention provides a method of manufacturing an integrated circuit including planarizing a semiconductor wafer surface. In one embodiment, the method comprises forming a dielectric layer over a first level having an irregular topography, depositing a sacrificial material over the dielectric layer, and then planarizing the semiconductor wafer surface to a planar surface. More specifically, the dielectric layer forms such that it substantially conforms to the irregular topography of the first level. The sacrificial material is formed to a substantially planar surface over the dielectric layer. Thus, the sacrificial material provides a substantially uniform chemical/mechanical planarization (CMP) process removal rate across the semiconductor wafer surface. In the ensuing step, planarizing the semiconductor wafer surface to a planar surface removes the sacrificial material and a portion of the dielectric layer with a CMP process.Type: GrantFiled: October 8, 1999Date of Patent: July 22, 2003Assignee: Agere Systems Inc.Inventors: William G. Easter, Sudhanshu Misra, Vivek Saxena
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Patent number: 6596608Abstract: To provide a method for producing a non-volatile semiconductor memory device that can form trenches having different depths in a reduced number of processes.Type: GrantFiled: June 21, 2002Date of Patent: July 22, 2003Assignee: NEC Electronics CorporationInventor: Kenji Saito
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Publication number: 20030104700Abstract: A new class of processes suited to the fabrication of layered material compositions is disclosed. Layered material compositions are typically three-dimensional structures which can be decomposed into a stack of structured layers. The best known examples are the photonic lattices. The present invention combines the characteristic features of photolithography and chemical-mechanical polishing to permit the direct and facile fabrication of, e.g., photonic lattices having photonic bandgaps in the 0.1-20 &mgr; spectral range.Type: ApplicationFiled: August 28, 2001Publication date: June 5, 2003Inventors: James G. Fleming, Shawn-Yu Lin
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Patent number: 6573187Abstract: A new method is provided for creating a dual damascene structure. Two layers of dielectric are deposited in sequence. The lower layer of dielectric is the via dielectric and is selected such that it has a low etching rate (when compared with the upper layer of dielectric) and results in different volatile gas during the etch of the via. A first photoresist is patterned for the via, the etch for the via etches through both layers of dielectric. A second layer of photoresist is patterned for the trench etch, due to the difference in etch rate between the two layers of dielectric, the trench of the dual damascene structure is etched without further affecting the via etch in the lower layer of dielectric.Type: GrantFiled: August 20, 1999Date of Patent: June 3, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Sheng-Hsiung Chen, Ming-Hsing Tsai
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Patent number: 6528410Abstract: A semiconductor device is manufactured by forming a first fluorine doped plasma silicon oxide film having a high fluorine concentration on first metallic interconnections formed on a semiconductor substrate surface, forming a second fluorine doped plasma silicon oxide film having a low fluorine concentration on the first film, and carrying out chemical machine polishing (CMP) only on the second fluorine doped plasma silicon oxide film.Type: GrantFiled: September 25, 2000Date of Patent: March 4, 2003Assignee: NEC CorporationInventors: Tatsuya Usami, Hiraku Ishikawa
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Patent number: 6524946Abstract: An insulating film for embedding conductive portions therein is formed so as to represent convex configurations corresponding to each top of convex conductive portions. The insulating film is covered with an etching stopper film having an etching rate which is smaller than that of the insulating film. Convex portions of the etching stopper film corresponding to each top of the conductive portions are removed partially, thereby forming a contact hole that reaches each top of the conductive portions through the removal portions of the silicon nitride film by an etching treatment. A plug conductive portion connected to each top of the conductive portions is formed in the contact hole.Type: GrantFiled: September 8, 2000Date of Patent: February 25, 2003Assignee: Oki Electric Industry Co., Ltd.Inventor: Satoshi Tanaka
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Patent number: 6521536Abstract: A series of evaluation steps is described for the planarization of a semiconductor substrate, such as a semiconductor wafer, using a linear track polisher having a continuous polishing surface. In the series of evaluation steps, there is determined a first pressure and a first continuous polishing surface speed at which an optimum material removal rate can be achieved and wherein the continuous polishing surface does not accumulate glaze as is possible when planarizing doped oxides such as PSG and BPSG.Type: GrantFiled: January 11, 1999Date of Patent: February 18, 2003Assignee: Micron Technology, Inc.Inventor: Karl M. Robinson
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Publication number: 20030027425Abstract: To provide a manufacturing method for simultaneously forming machined patterns different in dept in a small number of steps and a machined pattern having a U-shaped sectional form in which depths and widths are smoothly changed. Mask patterns 62 respectively having a semicircular sectional form and mask patterns 65 respectively having a V-shaped sectional form are formed at different opening widths 63 and 64 respectively to perform sandblasting by using the mask patterns 62 and 65 as masks. Though a deep groove is formed between the semicircular-sectional-form mask patterns 62, a shallow groove is formed between the V-shaped-sectional-form mask patterns 65.Type: ApplicationFiled: July 12, 2002Publication date: February 6, 2003Inventor: Yoshitaka Kawanishi
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Publication number: 20030008243Abstract: A process and structure for copper damascene interconnects including a tungsten-nitride (WN2) barrier layer formed by atomic layer deposition is disclosed. The process method includes of forming a copper damascene structure by forming a first opening through a first insulating layer. A second opening is formed through a second insulating layer which is provided over the first insulating layer. The first opening being in communication with the second opening. A tungsten-nitride (WN2) layer is formed in contact with the first and second openings. And, a copper layer is provided in the first and second openings. Copper is selectively deposited using a selective electroless deposition technique at low temperature to provide improved interconnects having lower electrical resistivity and more electro/stress-migration resistance than conventional interconnects. Additionally, metal adhesion to the underlying substrate materials is improved and the amount of associated waste disposal problems is reduced.Type: ApplicationFiled: July 9, 2001Publication date: January 9, 2003Applicant: Micron Technology, Inc.Inventors: kie Y. Ahn, Leonard Forbes
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Publication number: 20030005880Abstract: A method for making of an optoelectronic device and the device therefor comprising confinement layers, waveguides and active layers, all of which comprise a superlattice of binary III-V compounds.Type: ApplicationFiled: May 28, 2002Publication date: January 9, 2003Inventor: Manijeh Razeghi
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Patent number: 6503840Abstract: A composite layer of dielectric material is first formed over the integrated circuit structure, comprising a thin barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a thin capping layer of dielectric material over the layer of low k dielectric material. A photoresist mask, formed over the capping layer, is baked in the presence of UV light to cross-link the mask material. The composite layer is then etched through the resist mask using an etchant gas mixture including CO, but not oxygen. Newly exposed surfaces of low k dielectric material are then optionally densified to harden them. The resist mask is then removed using a plasma of a neutral or reducing gas. Exposed surfaces of low k dielectric material are then passivated by a low power oxygen plasma. Preferably, optional densification, mask removal, and passivation are all done in the same vacuum apparatus.Type: GrantFiled: May 2, 2001Date of Patent: January 7, 2003Assignee: LSI Logic CorporationInventors: Wilbur G. Catabay, Wei-Jen Hsia, Hong-Qiang Lu, Yong-Bae Kim, Kiran Kumar, Kai Zhang, Richard Schinella, Philippe Schoenborn
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Patent number: 6503848Abstract: A method is disclosed for smoothing the top surface of a layer of polysilicon which, as deposited, has a rough top surface due to the formation of polysilicon grains. A polymer, such as CxFyBrz, is deposited using chemical vapor deposition. The polymer layer has a thickness large enough so that the top surface of the polymer is at least a critical distance above the peaks of the grains on the top surface of the layer of polysilicon. The layer of polymer and part of the layer of polysilicon are then etched away using an etch back method which etches the polymer and polysilicon at the same etch rate. This results in a layer of polysilicon having a smooth top surface and the same thickness over the entire layer of polysilicon.Type: GrantFiled: November 20, 2001Date of Patent: January 7, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Bor-Wen Chan, Yuan-Hung Chiu, Huan-Just Lin, Hun-Jan Tao
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Patent number: 6486064Abstract: A method of forming junctions in a semiconductor substrate, where a gate dielectric layer is grown on the semiconductor substrate, a gate electrode layer is deposited on the gate dielectric layer, and a sacrificial layer is formed on the gate electrode layer. The sacrificial layer is patterned with a material to cover portions of the sacrificial layer and expose portions of the sacrificial layer. The exposed portions of the sacrificial layer are etched to remove the exposed portions of the sacrificial layer and expose portions of the gate electrode layer. The exposed portions of the gate electrode layer are etched to expose portions of the gate dielectric layer and form a gate electrode having exposed vertical faces. The sacrificial layer and the exposed portions of the gate dielectric layer are impregnated with a first species that inhibits diffusion of oxygen through the sacrificial layer and the exposed portions of the gate dielectric layer.Type: GrantFiled: September 26, 2000Date of Patent: November 26, 2002Assignee: LSI Logic CorporationInventor: Helmut Puchner