Abstract: A cleaning apparatus for cleaning a substrate includes a lamp for emitting ultraviolet radiation in an irradiation region; a housing that houses the lamp; a water deflector spaced below the housing, the water deflector having a water inlet for receiving a supply of ozonated water and a water outlet for discharging ozonated water irradiated by the lamp into a substrate processing region beneath the water deflector, and defining a water flow path between the water inlet and the water outlet, the water flow path extending in the irradiation region; an upper reflector extending along and above the lamp; and a lower reflector extending along and below the water deflector, wherein the upper reflector and the lower reflector at least partially define the irradiation region and reflect ultraviolet radiation toward the water flow path, and wherein the lower reflector shields the substrate from ultraviolet radiation emitted by the lamp.

Abstract: A photovoltaic device and a method of making the photovoltaic device are disclosed. The photovoltaic device may include a semiconductor layer epitaxially grown using a compound semiconductor material, such as a group III-V semiconductor material, wherein a surface of the semiconductor layer is textured via one or more laser pulses of a laser. The photovoltaic device may also include a dielectric layer deposited over the textured surface of the semiconductor layer, and a back metal reflector provided on the dielectric layer. The textured surface extends a path of light traveling through the photovoltaic device to increase absorption of the light within the photovoltaic device.

Abstract: A photovoltaic device and a method of making the photovoltaic device are disclosed. The photovoltaic device may include a semiconductor layer epitaxially grown using a compound semiconductor material, such as a group III-V semiconductor material, wherein a surface of the semiconductor layer is textured via one or more laser pulses of a laser. The photovoltaic device may also include a dielectric layer deposited over the textured surface of the semiconductor layer, and a back metal reflector provided on the dielectric layer. The textured surface extends a path of light traveling through the photovoltaic device to increase absorption of the light within the photovoltaic device.

Abstract: The current disclosure describes semiconductor devices, e.g., transistors, including a substrate, a semiconductor region including, at the surface, monolayer MoS2 and/or other monolayer material over the substrate, and a terminal structure over the semiconductor region, which includes a different monolayer material grown directly over the semiconductor region.

Abstract: Systems and methods are disclosed that provide a support system in the Z direction for patterning devices that can function under high acceleration and deceleration with minimal effect on travel and hysteresis in the X and Y directions. A reticle clamping system includes a support device and a holding device. The holding device is configured to releasably couple a reticle to the support device. The holding device includes a plurality of burls. The reticle clamping system further includes a metallic support system coupled to the support device. The metallic support system provides a vacuum path from a vacuum channel to the holding device.

Abstract: A sterilizing apparatus is disclosed. A sterilizing apparatus according to one embodiment comprises: a cover main body unit having an accommodation space formed therein so as to accommodate a device to be sterilized, wherein the accommodation space is open toward a bottom surface on which the device to be sterilized is disposed; an ultraviolet light emitting diode provided on a surface facing the bottom surface of the cover main body unit, and turned on so as to emit ultraviolet rays toward the accommodation space; a power supply unit for supplying power to the ultraviolet light emitting diode so as to turn on the ultraviolet light emitting diode; and a control unit for controlling an operation of the power supply unit.

Abstract: A method performed at least partially by a processor includes performing an air gap insertion process. The air gap insertion process includes sorting a plurality of nets of a layout of an integrated circuit in an order, and inserting, in accordance with the sorted order of the plurality of nets, air gap patterns adjacent to the plurality of nets. The method further includes generating a modified layout of the integrated circuit. The modified layout includes the plurality of nets and the inserted air gap patterns.

Abstract: A pattern forming method, includes: (i) a step of forming a film from an actinic ray-sensitive or radiation-sensitive resin composition containing (P) a resin having (a1) a repeating unit capable of decomposing by an action of an acid to produce a carboxyl group, represented by the following formula (I) as defined in the specification and (B) a compound capable of generating an acid upon irradiation with an actinic ray or radiation; (ii) a step of exposing the film; and (iii) a step of performing a development by using a developer containing an organic solvent to form a negative pattern.

Abstract: An apparatus for generating ultraviolet light and irradiating a 450 mm diameter semi-conductor wafer. The apparatus includes a plenum and an array of nine RF irradiator units coupled with the plenum. Each irradiator unit includes a plasma lamp bulb and an RF generator operable to generate a radiation energy field to excite the plasma lamp bulb and emit the ultraviolet light. The nine irradiator units are arranged in three rows with three of the irradiator units in each row.

Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.

Abstract: A method of radiatively scribing a substantially planar semiconductor substrate using a laser scribing apparatus, uses a laser scribing head configured and arranged to produce a two-dimensional array of laser beam spots to effect the scribing. In an embodiment, the spots of the array extend substantially parallel to X and Y directions in the plane of the substrate. In an embodiment, spots at a periphery in one or both directions of the array have a lower intensity than laser beams in a central portion of the array.

Abstract: An apparatus and method for characterizing a particle beam provides receiving a particle beam in a central region of a reduced pressure enclosure; impacting the received beam against a beam strike that is thermally isolated from the enclosure; measuring a temperature change of the beam strike due to the impacting beam; measuring a pressure change in the enclosure due to receiving the beam; and processing the measured temperature change and the measured pressure change to determine beam characteristics.

Abstract: The present disclosure provides a method that includes forming a first resist layer on a substrate; forming a second resist layer over the first resist layer; and performing an electron-beam (e-beam) lithography exposure process to the first resist layer and the second resist layer, thereby forming a first latent feature in the first resist layer and a second latent feature in the second resist layer.

Abstract: Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.

Abstract: Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.

Abstract: A lithography apparatus includes: a shield including a shield member having an aperture formed therein and having a first edge and a second edge defining the aperture; a driving mechanism including a rotation mechanism configured to rotate the shield member and a translation mechanism configured to translate the shield member; and a controller configured to control the driving mechanism so as to sequentially perform patterning.

Abstract: A metal contact of a solar cell is formed by electroplating copper using an electroplating seed that is formed on a dielectric layer. The electroplating seed includes an aluminum layer that connects to a diffusion region of the solar cell through a contact hole in the dielectric layer. A nickel layer is formed on the aluminum layer, with the nickel layer-aluminum layer stack forming the electroplating seed. The copper is electroplated in a copper plating bath that has methanesulfonic acid instead of sulfuric acid as the supporting electrolyte.

Abstract: A method of patterning a substrate comprises providing an array of resist features defined by a first pitch and a first gap width between adjacent resist features. Particles are introduced into the array of resist features, wherein the array of resist features becomes hardened. The introduction of particles may cause a reduction in critical dimension of the resist features. Sidewalls are provided on side portions of hardened resist features. Subsequent to the formation of the sidewalls, the hardened resist features are removed, leaving an array of isolated sidewalls disposed on the substrate. The sidewall array provides a mask for double patterning of features in the substrate layers disposed below the sidewalls, wherein an array of features formed in the substrate has a second pitch equal to half that of the first pitch.

Abstract: There is provided a flexible semiconductor device. The flexible semiconductor device of the present invention comprising a support layer, a semiconductor structure portion formed on the support layer, and a resin film formed on the semiconductor structure portion. The resin film comprises an opening formed by a laser irradiation therein, and also an electroconductive member which is in contact with the surface of the semiconductor structure portion is disposed within the opening of the resin film.

Abstract: A technique of forming an asymmetric pattern by using a phase shift mask, and further, techniques of manufacturing a diffraction grating and a semiconductor device, capable of improving accuracy of a product and capable of shortening manufacturing time. In a method of manufacturing a diffraction grating by using a phase shift mask (in which a light shield part and a light transmission part are periodically arranged), light emitted from an illumination light source is transmitted through the phase shift mask, and a photoresist on a surface of a Si wafer is exposed by providing interference between zero diffraction order light and positive first diffraction order light which are generated by the transmission through this phase shift mask onto the surface of the Si wafer, and a diffraction grating which has a blazed cross-sectional shape is formed on the Si wafer.

Abstract: A semiconductor structure including a double patterned structure and a method for forming the semiconductor structure are provided. A positive photoresist layer is formed on a negative photoresist layer, which is formed over a substrate. An exposure process is performed to form a first exposure region in the positive photoresist layer and to form a second exposure region in the negative photoresist layer in response to a first and a second intensity thresholds of the exposure energy. A positive-tone development process is performed to remove the first exposure region from the positive photoresist layer to form first opening(s). The second exposure region in the negative photoresist layer is then etched along the first opening(s) to form second opening(s) therein. A negative-tone development process is performed to remove portions of the negative photoresist layer outside of remaining second exposure region to form a double patterned negative photoresist layer.

Abstract: Systems for and methods of laser-enhanced plasma processing of semiconductor materials are disclosed. The method includes supporting a semiconductor material in a processing chamber interior and subjecting the semiconductor material to a plasma process. The method also includes simultaneously heating the wafer surface with a laser beam through a window in the processing chamber to increase the reaction rate of the plasma process. Other methods include performing laser heating of the semiconductor material before or after the plasma process but while the semiconductor material resides in the same chamber interior.

Abstract: The present disclosure provides a method that includes forming a first photoresist layer on a substrate; forming a second photoresist layer over the first photoresist layer; and performing a lithography exposure process to the first photoresist layer and the second photoresist layer, thereby forming a first latent feature in the first photoresist layer and a second latent feature in the second photoresist layer.

Abstract: A gas switching system for a gas distribution system for supplying different gas compositions to a chamber, such as a plasma processing chamber of a plasma processing apparatus, is provided. The chamber can include multiple zones, and the gas switching section can supply different gases to the multiple zones. The switching section can switch the flows of one or more gases, such that one gas can be supplied to the chamber while another gas can be supplied to a by-pass line, and then switch the gas flows.

Abstract: Methods and systems for measuring a characteristic of a substrate or preparing a substrate for analysis are provided. One method for measuring a characteristic of a substrate includes removing a portion of a feature on the substrate using an electron beam to expose a cross-sectional profile of a remaining portion of the feature. The feature may be a photoresist feature. The method also includes measuring a characteristic of the cross-sectional profile. A method for preparing a substrate for analysis includes removing a portion of a material on the substrate proximate to a defect using chemical etching in combination with an electron beam. The defect may be a subsurface defect or a partially subsurface defect. Another method for preparing a substrate for analysis includes removing a portion of a material on a substrate proximate to a defect using chemical etching in combination with an electron beam and a light beam.

Abstract: A method for the removal of copper oxide from a copper and dielectric containing structure of a semiconductor chip is provided. The copper and dielectric containing structure may be planarized by chemical mechanical planarization (CMP) and treated by the method to remove copper oxide and CMP residues. Annealing in a hydrogen (H2) gas and ultraviolet (UV) environment removes copper oxide, and a pulsed ammonia plasma removes CMP residues.

Abstract: A method for fabricating an anti-fuse memory cell having a semiconductor structure with a minimized area. The method includes providing a reference pattern for the semiconductor structure, and applying a reverse OPC technique that includes inverting selected corners of the reference pattern. The reverse OPC technique uses photolithographic distortions to provide a resulting fabricated pattern that is intentionally distorted relative to the reference pattern. By inverting corners of a geometric reference pattern, the resulting distorted pattern will have an area that is reduced relative to the original reference pattern. This technique is advantageous for reducing the area of a selected region of a semiconductor structure which may otherwise not be possible through normal design parameters.

Abstract: The present invention provides, in a plasma etching method for plasma-etching a magnetic film, a plasma etching method that allows a desired etching depth to be obtained regardless of the opening size of a mask. The present invention is, in a plasma etching method for plasma-etching a magnetic film by using a tantalum film as a mask, characterized by including: a first process to plasma-etch the magnetic film to a desired depth by using a mixed gas of an ammonia gas and a helium gas; and a second process, after the first process, to plasma-etch the magnetic film etched to the prescribed depth by using a mixed gas of an ammonia gas and a gas containing the oxygen element or a mixed gas of an ammonia gas and a gas containing a hydroxyl group.

Abstract: The invention relates to a method for the laser marking of a support having a body and a cover sheet. A laser beam is used to etch the body of the support through the thickness of the cover sheet. The support is laminated either during or after the laser marking in order to reduce or prevent deformations in the cover sheet resulting from etching.

Abstract: The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer.

Abstract: A III-nitride trench device has a vertical conduction region with an interrupted conduction channel when the device is not on, providing an enhancement mode device. The trench structure may be used in a vertical conduction or horizontal conduction device. A gate dielectric provides improved performance for the device by being capable of withstanding higher electric field or manipulating the charge in the conduction channel. A passivation of the III-nitride material decouples the dielectric from the device to permit lower dielectric constant materials to be used in high power applications.

Abstract: A method for forming a silicon layer according to inventive concept comprises: preparing an SOI substrate; applying an etchant or vapor of the etchant to the SOI substrate; and irradiating a light to the SOI substrate.

Abstract: A controlled method of releasing a microstructure comprising a silicon oxide layer located between a substrate layer and a layer to be released from the silicon oxide layer is described. The method comprises the step of exposing the silicon oxide layer to a hydrogen fluoride vapor in a process chamber having controlled temperature and pressure conditions. A by-product of this reaction is water which also acts as a catalyst for the etching process. It is controlled employment of this inherent water source that results in a condensed fluid layer forming, and hence etching taking place, only on the exposed surfaces of the oxide layer. The described method therefore reduces the risk of the effects of capillary induced stiction within the etched microstructure and/or corrosion within the microstructure and the process chamber itself.

Abstract: There is provided a plasma processing apparatus capable of optimizing a plasma process in response to various requirements of a micro processing by effectively controlling a RF bias function. In this plasma processing apparatus, a high frequency power RFH suitable for generating plasma of a capacitively coupling type is applied to an upper electrode 48 (or lower electrode 16) from a third high frequency power supply 66, and two high frequency powers RFL1 (0.8 MHz) and RFL2 (13 MHz) suitable for attracting ions are applied to the susceptor 16 from first and second high frequency power supplies 36 and 38, respectively, in order to control energy of ions incident onto a semiconductor wafer W from the plasma. A control unit 88 controls a total power and a power ratio of the first and second high frequency powers RFL1 and RFL2 depending on specifications, conditions or recipes of an etching process.

Abstract: A system for surface patterning using a three dimensional holographic mask includes a light source configured to emit a light beam toward the holographic mask. The holographic mask can be formed as a topographical pattern on a transparent mask substrate. A semiconductor substrate can be positioned on an opposite site of the holographic mask as the light source and can be spaced apart from the holographic mask. The system can also include a base for supporting the semiconductor substrate.

Abstract: Provided are methods of etching a substrate using atomic layer deposition apparatus. Atomic layer deposition apparatus including a gas distribution plate with a thermal element are discussed. The thermal element is capable of locally changing the temperature of a portion of the surface of the substrate to vaporize an etch layer deposited on the substrate.

Abstract: A method for etching a conductive layer through a mask with wider and narrower features is provided. A steady state etch gas is flowed. A steady state RF power is provided to form a plasma from the etch gas. A pulsed bias voltage is provided during the steady state etch gas flow, wherein the pulsed bias voltage has a frequency between 1 to 10,000 Hz. Wider and narrower features are etched into the conductive layer using the plasma formed from the etch gas.

Abstract: A method and system for fabricating a substrate is disclosed. First, a plurality of process chambers are provided, at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate and at least one of the plurality of process chambers containing a plasma filtering plate library. A plasma filtering plate is selected and removed from the plasma filtering plate library. Then, the plasma filtering plate is inserted into at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate. Subsequently, an etching process is performed in the substrate.

Abstract: A method and system for performing gas cluster ion beam (GCIB) etch processing of various materials is described. In particular, the GCIB etch processing includes setting one or more GCIB properties of a GCIB process condition for the GCIB to achieve one or more target etch process metrics.

Abstract: An integrated circuit may be formed by a process of forming a first interconnect pattern in a plurality of parallel route tracks, and forming a second interconnect pattern in the plurality of parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point in an instance of the first plurality of parallel route tracks, and the second interconnect pattern includes a second lead pattern which extends to a second point in the same instance of the plurality of parallel route tracks, such that the second point is laterally separated from the first point by a distance one to one and one-half times a space between adjacent parallel lead patterns in the plurality of parallel route tracks. A metal interconnect formation process is performed which forms metal interconnect lines in an interconnect level defined by the first interconnect pattern and the second interconnect pattern.

Abstract: In a manufacturing process of a semiconductor device, a manufacturing technique for reducing the number of lithography processes using a photoresist and simplifying the process is provided, and the throughput is improved. An etching mask for forming a pattern of a layer to be processed such as a conductive layer or a semiconductor layer is manufactured without using a lithography technique that uses a photoresist. The etching mask is formed of a stacked layer structure of a light absorption layer and an insulating layer utilizing laser ablation by laser beam irradiation through a photomask.

Abstract: The invention relates to a method (3) of fabricating a mold (39, 39?) including the following steps: (a) depositing (9) an electrically conductive layer on the top (20) and bottom (22) of a wafer (21) made of silicon-based material; (b) securing (13) the wafer to a substrate (23) using an adhesive layer; (c) removing (15) one part (26) of the conductive layer from the top of the wafer (21); and (d) etching (17) the wafer as far as the bottom conductive layer (22) thereof in the shape (26) of the one part removed from the top conductive layer (22) to form at least one cavity (25) in the mold. The invention concerns the field of micromechanical parts, particularly, for timepiece movements.

Abstract: An anisotropically conductive member has an insulating base material, and conductive paths composed of a conductive material which pass in a mutually insulated state through the insulating base material in a thickness direction thereof and which are provided in such a way that a first end of each conductive path is exposed on a first side of the insulating base material and a second end of each conductive path is exposed on a second side of the insulating base material. The conductive paths have a density of at least 2 million paths/mm2 and the insulating base material is a structure composed of an anodized aluminum film having micropores therein.

Abstract: One or more techniques or systems for forming a pattern during semiconductor fabrication are provided herein. In some embodiments, a photo resist (PR) region is patterned and a spacer region is formed above or surrounding at least a portion of the patterned PR region. Additionally, at least some of the spacer region and the patterned PR region are removed to form one or more spacers. Additionally, a block co-polymer (BCP) is filled between the spacers. In some embodiments, the BCP comprises a first polymer and a second polymer. In some embodiments, the second polymer is removed, thus forming a pattern comprising the first polymer and the spacers. In this manner, a method for forming a pattern during semiconductor fabrication is provided, such that a width of the spacer or the first polymer is controlled.

Abstract: A method of forming a nanopore array includes patterning a front layer of a substrate to form front trenches, the substrate including a buried layer disposed between the front layer and a back layer; depositing a membrane layer over the patterned front layer and in the front trenches; patterning the back layer and the buried layer to form back trenches, the back trenches being aligned with the front trenches; forming a plurality of nanopores through the membrane layer; depositing a sacrificial material in the front trenches and the back trenches; depositing front and back insulating layers over the sacrificial material; and heating the sacrificial material to a decomposition temperature of the sacrificial material to remove the sacrificial material and form pairs of front and back channels, wherein the front channel of each channel pair is connected to the back channel of its respective channel pair by an individual nanopore.

Abstract: A photoresist removal method is described. A substrate having thereon a positive photoresist layer to be removed is provided. The positive photoresist layer is UV-exposed without using a photomask. A development liquid is used to remove the UV-exposed positive photoresist layer. The substrate as provided may further have thereon a sacrificial masking layer under the positive photoresist layer. The sacrificial masking layer is removed after the UV-exposed positive photoresist layer is removed.

Abstract: A method and system for fabricating a read sensor on a substrate for a read transducer is described. A read sensor stack is deposited on the substrate. A mask is provided on the on the read sensor stack. The mask has a pattern that covers a first portion of the read sensor stack corresponding to the read sensor, covers a second portion of the read sensor stack distal from the read sensor, and exposes a third portion of the read sensor stack between the first and second portions. The read sensor is defined from the read sensor stack. A hard bias layer is deposited. An aperture free mask layer including multiple thicknesses is provided. A focused ion beam scan (FIBS) polishing step is performed on the mask and hard bias layers to remove a portion of the mask and hard bias layers based on the thicknesses.

Abstract: A method of etching silicon-containing material is described and includes a SiConi™ etch having a greater or lesser flow ratio of hydrogen compared to fluorine than that found in the prior art. Modifying the flow rate ratios in this way has been found to reduce roughness of the post-etch surface and to reduce the difference in etch-rate between densely and sparsely patterned areas. Alternative means of reducing post-etch surface roughness include pulsing the flows of the precursors and/or the plasma power, maintaining a relatively high substrate temperature and performing the SiConi™ in multiple steps. Each of these approaches, either alone or in combination, serve to reduce the roughness of the etched surface by limiting solid residue grain size.

Abstract: A structure and a method of manufacturing a Pb-free Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure for semiconductor chip packaging that reduce chip-level cracking during the Back End of Line (BEOL) processes of chip-join cool-down. An edge of the BLM structure that is subject to tensile stress during chip-join cool down is protected from undercut of a metal seed layer, caused by wet etch of the chip to remove metal layers from the chip's surface and solder reflow, by an electroplated barrier layer, which covers a corresponding edge of the metal seed layer.

Abstract: A process of cleaning wire bond pads associated with OLED devices, including the steps of depositing on the wire bond pads one or more layers of ablatable material, and ablating the one or more layers with a laser, thereby exposing a clean wire bond pad.