Abstract: In a process for forming trenches having M different widths in a substrate, a passivation step and an etching step are alternately performed. The passivation step includes depositing a passivation layer on a bottom of the trenches by converting gas introduced in a chamber into plasma. The etching step includes removing the passivation layer on the bottom of the trenches and applying reactive ion etching to the bottom to increase a depth of the trenches. The etching step further includes setting energy for the reactive ion etching to a predetermined value when the passivation layer on the bottom of the trench having the Nth smallest width is removed. The value allows the etching amount of the trench having the Nth smallest width to be equal to or greater than the etching amount of the trench having the (N+1)th smallest width.

Abstract: An integrated circuit is formed by forming a first interconnect pattern in parallel route tracks, and forming a second interconnect pattern in alternating parallel route tracks. The first interconnect pattern includes a first lead pattern in the parallel route tracks, and the second interconnect pattern includes a second lead pattern in an immediately adjacent route track. The first interconnect pattern includes a crossover pattern which extends from the first lead pattern to the second lead pattern. An exclusion zone in the route track immediately adjacent to the crossover pattern is free of a lead pattern for a lateral distance of two to three times the width of the crossover pattern. Metal interconnect lines are form in the first interconnect pattern and the second interconnect pattern areas, including a continuous metal crossover line through the crossover pattern area. The exclusion zone is free of the metal interconnect lines.

Abstract: A method and system for performing gas cluster ion beam (GCIB) etch processing of various materials is described. In particular, the GCIB etch processing includes setting one or more GCIB properties of a GCIB process condition for the GCIB to achieve one or more target etch process metrics.

Abstract: An integrated circuit may be formed by a process of forming a three interconnect patterns in a plurality of parallel route tracks, using photolithography processes which have illumination sources capable of a pitch distance twice the pitch distance of the parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point. The second interconnect pattern includes a second lead pattern which is parallel to and immediately adjacent to the first lead pattern. The third interconnect pattern includes a third lead pattern which is parallel to and immediately adjacent to the second pattern and which extends to a second point in the first instance of the parallel route tracks, laterally separated from the first point by a distance less than one and one-half times a space between adjacent patterns in the parallel route tracks.

Abstract: Methods for removing a masking material, for example, a photoresist, and electronic devices formed by removing a masking material are presented. For example, a method for removing a masking material includes contacting the masking material with a solution comprising cerium. The cerium may be comprised in a salt. The salt may be cerium ammonium nitrate.

Abstract: Using developed photo-resist materials as insulator materials for through-hole connections, the preferred embodiments of the present invention improve the area efficiency of electrical devices manufactured on silicon substrates. The area efficiency is further improved by opening holes from both sides of silicon substrate to form through-holes. Besides area efficiency, these methods also provide better control in parasitic impedance of through-hole connection.

Abstract: A method for fabrication of features of an integrated circuit and device thereof include patterning a first structure on a surface of a semiconductor device and forming spacers about a periphery of the first structure. An angled ion implantation is applied to the device such that the spacers have protected portions and unprotected portions from the angled ion implantation wherein the unprotected portions have an etch rate greater than an etch rate of the protected portions. The unprotected portions and the first structure are selectively removed with respect to the protected portions. A layer below the protected portions of the spacer is patterned to form integrated circuit features.

Abstract: An interconnect structure is provided which comprises a semiconductor substrate; a patterned and cured photoresist wherein the photoresist contains a low k dielectric substitutent and contains a fortification layer on its top and sidewall surfaces forming vias or trenches; and a conductive fill material in the vias or trenches. Also provided is a method for fabricating an interconnect structure which comprises depositing a photoresist onto a semiconductor substrate, wherein the photoresist contains a low k dielectric constituent; imagewise exposing the photoresist to actinic radiation; then forming a pattern of vias or trenches in the photoresist; surface fortifying the pattern of vias or trenches proving a fortification layer on the top and sidewalls of the vias or trenches; curing the pattern of vias or trenches thereby converting the photoresist into a dielectric; and filling the vias and trenches with a conductive fill material.

Abstract: A method for manufacturing a thin film transistor (TFT) through a process including back exposure, in which oxide semiconductor is used for a channel layer; using an electrode over a substrate as a mask, negative resist is exposed to light from the back of the substrate; the negative resist except its exposed part is removed; and an electrode is shaped by etching a conductive film using the exposed part as an etching mask.

Abstract: A method for the removal of copper oxide from a copper and dielectric containing structure of a semiconductor chip is provided. The copper and dielectric containing structure may be planarized by chemical mechanical planarization (CMP) and treated by the method to remove copper oxide and CMP residues. Annealing in a hydrogen (H2) gas and ultraviolet (UV) environment removes copper oxide, and a pulsed ammonia plasma removes CMP residues.

Abstract: A method for fabricating a fine pattern includes forming a first photomask including first light transmission regions set in a line shape over a first phase shift mask (PSM) region and a first binary mask (BM) region adjacent to the first phase shift mask region. A second photomask may be formed to include second light transmission regions set in a line shape over a second phase shift mask region and a second binary mask region adjacent to the second phase shift mask region, wherein the second light transmission regions intersect the first light transmission regions. A resist layer may first be exposed using the first photomask and secondly exposed using the second photomask. The first and secondly exposed resist layer may be developed to form resist patterns with open regions corresponding to portions where the first light transmission regions intersect the second light transmission regions.

Abstract: This invention relates to a process for selective removal of materials, such as: silicon, molybdenum, tungsten, titanium, zirconium, hafnium, vanadium, tantalum, niobium, boron, phosphorus, germanium, arsenic, and mixtures thereof, from silicon dioxide, silicon nitride, nickel, aluminum, TiNi alloy, photoresist, phosphosilicate glass, boron phosphosilicate glass, polyimides, gold, copper, platinum, chromium, aluminum oxide, silicon carbide and mixtures thereof. The process is related to the important applications in the cleaning or etching process for semiconductor deposition chambers and semiconductor tools, devices in a micro electro mechanical system (MEMS), and ion implantation systems. Methods of forming XeF2 by reacting Xe with a fluorine containing chemical are also provided, where the fluorine containing chemical is selected from the group consisting of F2, NF3, C2F6, CF4, C3F8, SF6, a plasma containing F atoms generated from an upstream plasma generator and mixtures thereof.

Abstract: A method for fabricating a semiconductor laser device, by etching facets using a photoelectrochemical (PEC) etch, so that the facets are sufficiently smooth to support optical modes within a cavity bounded by the facets.

Abstract: A plasma etching method includes disposing first electrode and second electrodes; preparing a part in a processing chamber; supporting a substrate by the second electrode to face the first electrode; vacuum-evacuating the processing chamber; supplying a first processing gas containing an etchant gas into a processing space between the first electrode and the second electrode; generating a plasma of the first processing gas in the processing space by applying a radio frequency power to the first electrode or the second electrode; and etching a film on the substrate by using the plasma. Further, a resist modification process includes vacuum-evacuating the processing chamber; supplying a second processing gas into the processing space; generating a plasma; and applying a negative DC voltage to the part, the part being disposed away from the substrate in the processing chamber and injecting electrons discharged from the part into the resist pattern on the substrate.

Abstract: A method of disposing alignment keys may include preparing a substrate including a shot group which includes a plurality of chip regions, and each of chip regions includes a key region. The method further includes forming at least one alignment key in each of the key regions of the substrate. Each of the alignment keys may be adapted to be used for at least one of a plurality of exposure processes which may be different from each other, and center points of the key regions may be located at points shifted from center points of the chip regions by the same distance along the same direction.

Abstract: In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the preliminary hole. An etching gas including hydrogen fluoride (HF) or fluorine (F2) is then provided onto the photosensitive layer pattern to etch the insulation layer so that width of the preliminary hole is increased.

Abstract: A surface component film (2) is etched using a resist (3) as a mask, and the surface component film (2) is patterned according to the shape of an aperture (3a). This results in a step portion (4) having the same shape as the aperture (3a), with the sidewall (4a) of the step portion (4) exposed through the aperture (3a). The aperture (3a) is spin-coated with a shrink agent, reacted at a first temperature, and developed to shrink the aperture (3a). To control the shrinkage with high accuracy, in the first round of reaction, the aperture is shrunk by, for example, about half of the desired shrinkage. The aperture (3a) is further spin-coated with a shrink agent, reacted at a second temperature, and developed to shrink the aperture (3a). In this embodiment, the second-round shrink process will result in the desired aperture length. The second temperature is adjusted based on the shrinkage in the first round.

Abstract: A plasma processing apparatus in which consumption of expensive krypton and xenon gases is suppressed as much as possible while reducing damage on a workpiece during plasma processing. In plasma processing of a substrate using a rare gas, two or more kinds of different rare gases are employed, and an inexpensive argon gas is used as one rare gas and any one or both of krypton and xenon gases having a larger collision cross-sectional area against electron than that of the argon gas is used as the other gas. Consequently, consumption of expensive krypton and xenon gases is suppressed as much as possible and damage on a workpiece is reduced during plasma processing.

Abstract: The plasma etching method includes: an etching step of placing, on a stage in a chamber, a substrate in which a prescribed mask pattern is formed by a protective film on a surface of a material to be etched, generating a plasma in the chamber while supplying processing gas to the chamber, and etching a portion of the material corresponding to an opening portion in the mask pattern; a voltage measurement step of, during the etching in the etching step, measuring a voltage at the surface of the material on a side where the mask pattern is formed, through a conductive member that is placed in contact with the surface of the material on the side where the mask pattern is formed; and a control step of controlling an etching condition in the etching step in accordance with a measurement result obtained in the voltage measurement step.

Abstract: A method and apparatus are provided to form spacer materials adjacent substrate structures. In one embodiment, a method is provided for processing a substrate including placing a substrate having a substrate structure adjacent a substrate surface in a deposition chamber, depositing a spacer layer on the substrate structure and substrate surface, and etching the spacer layer to expose the substrate structure and a portion of the substrate surface, wherein the spacer layer is disposed adjacent the substrate structure. The spacer layer may comprise a boron nitride material. The spacer layer may comprise a base spacer layer and a liner layer, and the spacer layer may be etched in a two-step etching process.

Abstract: The invention concerns a process for the production of a multi-layer body, wherein the multi-layer body includes at least two functional layers on a top side of a carrier substrate, which are structured in register relationship with each other, by a procedure whereby an underside of the carrier substrate is prepared in such a way that in a first region there results a transparency for a first exposure radiation and in at least one second region there results a transparency for at least one second exposure radiation different therefrom in register relationship with the first region, the underside is successively exposed with the first and the at least one second exposure radiation and the first exposure radiation is used for structuring a first functional layer and the at least one second exposure radiation is used for structuring at least one second functional layer on the top side of the carrier substrate.

Abstract: In an active matrix substrate (29), a part of the drain electrode (15) of a TFT (10), which corresponds to an auxiliary capacitor electrode (26), is overlapped with a capacitor signal line (25). The auxiliary capacitor electrode (26) includes a notch (27).

Abstract: To provide a method for manufacturing a semiconductor device, which the method is capable of efficient mass production of high-performance semiconductor devices by, upon manufacture of a semiconductor device, eliminating unwanted features (e.g., side lobes) created together with a resist pattern by thickening the resist pattern, to reduce the burden in designing photomasks and to increase depth of focus. The method of the present invention for manufacturing a semiconductor device includes at least: forming a resist pattern on a work surface and applying over a surface of the resist pattern a resist pattern thickening material to thereby thicken the resist pattern to eliminate an unwanted feature created together with the resist pattern.

Abstract: The semiconductor device manufacturing method comprises the step of transferring patterns formed on a reticle to a semiconductor substrate by an exposure with oblique incidence illumination. In the step of making the exposure with oblique incidence illumination, the exposure is made with an aperture stop 16 including a first ring-shaped aperture 22, and a plurality of second apertures 24a1-24a4 formed around the first ring-shaped aperture 22. The exposure is made with an aperture stop 16 having the first ring-shaped aperture 22 which can transfer patterns arranged at a medium pitch to a relatively large pitch with a relatively high resolution and the second aperture 24a1-24a4 which can transfer patterns arranged at a relatively small pitch with a relatively high resolution, whereby even when the patterns are arranged at various pitch values, the DOF can be surely sufficient, and the patterns can be stably transferred.

Abstract: A quartz window with an interior plenum is operable as a shutter or UV filter in a degas chamber by supplying the plenum with an ozone-containing gas. Pressure in the plenum can be adjusted to block UV light transmission into the degas chamber or adjust transmittance of UV light through the window. When the plenum is evacuated, the plenum allows maximum transmission of UV light into the degas chamber.

Abstract: A method and apparatus that may comprise an EUV light producing mechanism utilizing an EUV plasma source material comprising a material that will form an etching compound, which plasma source material produces EUV light in a band around a selected center wavelength comprising: an EUV plasma generation chamber; an EUV light collector contained within the chamber having a reflective surface containing at least one layer comprising a material that does not form an etching compound and/or forms a compound layer that does not significantly reduce the reflectivity of the reflective surface in the band; an etchant source gas contained within the chamber comprising an etchant source material with which the plasma source material forms an etching compound, which etching compound has a vapor pressure that will allow etching of the etching compound from the reflective surface. The etchant source material may comprises a halogen or halogen compound.

Abstract: Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.

Abstract: The present invention relates to a method for manufacturing a flat panel display. Herein, the same mask is used to form contact holes and pixel electrodes in the display substrate. Hence, the number of masks needed for manufacturing the flat panel display can be reduced to decrease the manufacturing cost.

Abstract: A multichamber-type processing apparatus and processing method using same, in which a substrate is reliably neutralized without being damaged, thereby ensuring excellent accuracy and throughput. The processing apparatus includes a transfer chamber, etching chambers selectively communicating with the transfer chamber and providing a space to etch a first substrate therein, and ashing chambers selectively communicating with the transfer chamber and providing a space to ash a second substrate therein. A transfer mechanism is installed in the transfer chamber to sequentially transfer the substrate from the transfer chamber into the etching and ashing chambers. The substrate is electrostatically adsorbed to electrostatic chucks in the etching and ashing chambers. An monatomic nitrogen atom supply unit supplies dissociated monatomic nitrogen atoms into the etching and ashing chambers.

Abstract: A method for fabricating a semiconductor device includes stacking a spin on carbon (SOC) layer and an multifunction hard mask (MFHM) layer on a substrate, forming a photoresist pattern over the MFHM layer, first etching the MFHM layer using a first amount of a fluorine-based gas, second etching the MFHM layer using a second amount of a fluorine-based gas, wherein the second amount is less than the first amount, etching the SOC layer using the MFHM layer as an etch barrier, and etching the substrate using the SOC layer and the MFHM layer as an etch barrier.

Abstract: A method for etching a substrate having a silicon layer in a plasma processing chamber having a bottom electrode on which the substrate is disposed on during etching. The method includes performing a main etch step. The method also includes terminating main etch step when a predefined etch depth of at least 70 percent of thickness into silicon layer is achieved. The method further includes performing an overetch step. The overetch step including a first process step and a second process step. First process step is performed using a first bottom power level applied to bottom electrode. Second process step is performed using a second bottom power level applied to bottom electrode that is lower than first bottom power level. First process and second process steps are alternately performed a plurality of times. The method yet also includes terminating overetch step after silicon layer is etched through.

Abstract: Devices having voids are producible by employing an electrochemical corrosion process. For example, an electrically conductive region is formed to have a surrounding chemically distinct region. Such formation is possible through conventional semiconductor processing techniques such as a copper damascene process. The surrounded conducting material is configured to be in electrical communication with a charge separation structure. The electrically conducting region is contacted with a fluid electrolyte and electromagnetic radiation is made to illuminate the charge separation region to induce separation of electrons and holes. The resulting separated charges are used to drive an electrochemical corrosion process at the conductive material/electrolyte interface resulting in the removal of at least a portion of the electrically conducting material.

Abstract: A method for shaping a surface of a workpiece, comprises positioning at least one of a workpiece and an inductively-coupled plasma (ICP) torch including three concentrically arranged tubes. A plasma gas is introduced to an outer tube of the ICP torch and energy is transferred from a radio frequency (RF) power source to the plasma gas to generate an excitation zone at least partially downstream of the ICP torch. A reactive reactive precursor is introduced to the excitation zone, and an auxiliary gas is introduced to the intermediate tube to control a position of the excitation zone relative to the ICP torch so that a controlled distribution of reactive species is formed. The surface is shaped by removing material from the surface of the workpiece with at least a portion of the reactive species and adding material to the surface of the workpiece with at least a portion of the reactive species.

Abstract: Using developed photo-resist materials as insulator materials for through-hole connections, the preferred embodiments of the present invention improve the area efficiency of electrical devices manufactured on silicon substrates. The area efficiency is further improved by opening holes from both sides of silicon substrate to form through-holes. Besides area efficiency, these methods also provide better control in parasitic impedance of through-hole connection.

Abstract: A method of etching a semiconductor substrate. The method includes the steps of applying a photoresist etch mask layer to a device surface of the substrate. A select first area of the photoresist etch mask is masked, imaged and developed. A select second area of the photoresist etch mask layer is irradiated to assist in post etch stripping of the etch mask layer from the select second area. The substrate is etched to form fluid supply slots through a thickness of the substrate. At least the select second area of the etch mask layer is removed from the substrate, whereby mask layer residue formed from the select second area of the etch mask layer is significantly reduced.

Abstract: A manufacturing method includes forming a semi-cured insulation layer made of a photosensitive material on a supporting body; forming an opening part in the insulation layer by a photolithography method, the opening part being configured to expose the supporting body; arranging a semiconductor chip on the insulation layer so that a position of an electrode of the semiconductor chip is consistent with a position of the opening part, and curing the insulation layer; forming sealing resin on a surface of the insulation layer at the semiconductor chip side, the sealing resin being configured to seal the semiconductor chip; removing the supporting body; and providing a wiring layer on a surface of the insulation layer opposite to the semiconductor chip side, the wiring layer being electrically connected to the electrode exposed in the opening part, so that a wiring structural body including the insulation layer and the wiring layer is formed.

Abstract: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device, which may increase a coupling coefficient between a control gate and a floating gate by increasing a surface area of floating gate. In embodiments, a flash memory device may be formed by forming a photoresist pattern for forming a floating gate on a semiconductor substrate including an oxide film, a floating gate poly film, and a BARC (Bottom AntiReflect Coating), performing a first etching process using the photoresist pattern as a mask, to etch the floating gate poly film to a predetermined depth, depositing and forming a polymer to cover the photoresist pattern, forming spacers of the polymer at both sidewalls of the photoresist pattern, forming a second etching process using the spacers as a mask, to expose the oxide film, and removing the BARC, the photoresist pattern and the spacers by ashing and stripping.

Abstract: A compound semiconductor is placed in a reaction vessel (12) of which the inner gas is subjected to replacement with a low-vapor-pressure gas (2) whose equilibrium vapor pressure at the melting point of the compound semiconductor is 1 atm or lower. The low-vapor-pressure gas is urged to flow along the surface of the compound semiconductor while keeping the internal pressure of the reaction vessel at a value not lower than that equilibrium vapor pressure. The surface of the compound semiconductor is irradiated with a pulsed-laser light (3) whose photon energy is higher than the band gap of the compound semiconductor. Thus, only that part of the compound semiconductor which is located at the pulsed-laser light irradiation position is instantly heated and melted while keeping the atmospheric temperature of the low-vapor-pressure gas at a room temperature or a temperature equal to or lower than the decomposition temperature.

Abstract: An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, one or more wavelength lights are directed on the integrated circuit and based upon the detection of interference fringes and characteristics of the same, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection and/or characteristics of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Resulting fringes will be a function, in part, of the thickness and/or profile of the trench floor. Milling may be controlled as a function of the detected fringe patterns.

Abstract: A stepper is combined with hardware that deposits a layer of material in the course of forming an integrated circuit, thus performing the deposition, patterning and cleaning without exposing the wafer to a transfer between tools and combining the function of three tools in a composite tool. The pattern-defining material is removed by the application of UV light through the mask of the stepper, thereby eliminating the bake and development steps of the prior art method. Similarly, a flood exposure of UV eliminates the cleaning steps of the prior art method.

Abstract: A method of manufacturing semiconductor structures is disclosed. In one embodiment, a first mask is provided above a substrate. The first mask includes first mask lines extending along a first axis. A second mask is provided above the first mask. The second mask includes second mask lines extending along a second axis that intersects the first axis. At least one of the first and second masks is formed by a pitch fragmentation method. Structures may be formed in the substrate, wherein the first and the second mask are effective as a combined mask. The structures may be equally spaced at a pitch in the range of a minimum lithographic feature size for repetitive line structures.

Abstract: A lift off process is used to separate a layer of material from a substrate by irradiating an interface between the layer of material and the substrate. According to one exemplary process, the layer is separated into a plurality of sections corresponding to dies on the substrate and a homogeneous beam spot is shaped to cover an integer number of the sections.

Abstract: In a method of vapor etching, a sample that includes a first layer atop of and in contact with a second layer which is atop of and in contact with a third layer, wherein at least the first and second layers are comprised of different materials. The sample is etched by a vapor etchant under first process conditions that cause at least a part of the first layer to be fully removed while leaving the third layer and the second layer underlying the removed part of the first layer substantially unetched. The sample is then etched by the same or a different vapor etchant under second process conditions that cause at least the part of the second layer exposed by the removal of the at least part of the first layer to be fully removed while leaving the third layer underlying the removed part of the second layer substantially unetched.

Abstract: The present invention relates to a method for manufacturing a flat panel display. Herein, the same mask is used to form contact holes and pixel electrodes in the display substrate. Hence, the number of masks needed for manufacturing the flat panel display can be reduced to decrease the manufacturing cost.

Abstract: A process of cleaning wire bond pads associated with OLED devices, including the steps of depositing on the wire bond pads one or more layers of ablatable material, and ablating the one or more layers with a laser, thereby exposing a clean wire bond pad.

Abstract: A surface component film (2) is etched using a resist (3) as a mask, and the surface component film (2) is patterned according to the shape of an aperture (3a). This results in a step portion (4) having the same shape as the aperture (3a), with the sidewall (4a) of the step portion (4) exposed through the aperture (3a). The aperture (3a) is spin-coated with a shrink agent, reacted at a first temperature, and developed to shrink the aperture (3a). To control the shrinkage with high accuracy, in the first round of reaction, the aperture is shrunk by, for example, about half of the desired shrinkage. The aperture (3a) is further spin-coated with a shrink agent, reacted at a second temperature, and developed to shrink the aperture (3a). In this embodiment, the second-round shrink process will result in the desired aperture length. The second temperature is adjusted based on the shrinkage in the first round.

Abstract: A method for forming a via in a sapphire substrate with a laser machining system that includes an ultrafast pulsed laser source. The sapphire substrate is provided. Pulses of laser light are substantially focused to a beam spot on the first surface of the sapphire substrate such that each focused pulse of laser light ablates a volume of the sapphire substrate having a depth less than the substrate thickness. The beam spot of the focused laser light pulses is scanned over a via portion of the first surface of the sapphire substrate. The sapphire substrate is moved in a direction substantially normal to the first surface to control the volume of the sapphire substrate ablated by each pulse of laser light to be substantially constant. The pulsing and scanning steps are repeated until the via is formed extending from the first surface to the second surface of the sapphire substrate.

Abstract: A method and apparatus for local beam processing using a beam activated gas to etch material are described. Compounds are disclosed that are suitable for beam-induced etching. The invention is particularly suitable for electron beam induced etching of chromium materials on lithography masks. In one embodiment, a polar compound, such as ClNO2 gas, is activated by the electron beam to selectively etch a chromium material on a quartz substrate. By using an electron beam in place of an ion beam, many problems associated with ion beam mask repair, such as staining and riverbedding, are eliminated. Endpoint detection is not critical because the electron beam and gas will not etch significantly the substrate.

Abstract: Methods for monitoring and detecting optical emissions while performing photoresist stripping and removal of residues from a substrate or a film stack on a substrate are provided herein. In one embodiment, a method is provided that includes positioning a substrate comprising a photoresist layer into a processing chamber; processing the photoresist layer using a multiple step plasma process; and monitoring the plasma for a hydrogen optical emission during the multiple step plasma process; wherein the multiple step plasma process includes removing a bulk of the photoresist layer using a bulk removal step; and switching to an overetch step in response to the monitored hydrogen optical emission.