Abstract: A method of forming fine patterns in a semiconductor device through a double photo lithography process. A layer to be etched and a hard mask layer are sequentially formed on a semiconductor substrate. A first photo resist pattern is formed on the hard mask layer. A first hard mask layer pattern is formed by etching the hard mask layer using the first photo resist pattern. After the first photo resist pattern is removed, a second photo resist pattern is formed on the resultant structure. A second hard mask layer pattern is formed by etching the first hard mask layer pattern using the second photo resist pattern. The layer to be etched is then etched using the second hard mask layer pattern after the second photo resist pattern has been removed, resulting in patterns have line edges without rounding.

Abstract: A method of exposing a substrate to a pattern of a reticle by synchronously scanning the reticle and the substrate in a direction relative to a slit-shaped illumination area which is formed on the reticle. The method includes steps of providing a reticle on which first and second patterns are formed along the direction, with a space therebetween, exposing a substrate to the first and second patterns of the reticle under different exposure conditions in one scanning process and changing over the exposure conditions when the illumination area exists in the space on the reticle during the one scanning process.

Abstract: The surface of a substrate having a transmission index is irradiated with a beam of atoms having a slow enough velocity to be adsorbed on the substrate. A laser beam whose frequency is detuned by 1 to 10 gigahertz from the resonant frequency of the atoms is projected onto the substrate at an angle, producing total reflection. The atom beam is reflected at regions at which an intensity of an evanescent wave emitted at this time from the substrate surface is high, and adsorbed at regions where the intensity is low, thereby achieving atomic fabrication patterns on a substrate. By using a hologram image to create the pattern, it is possible to form an atomic fabrication patterns in which the size of features correspond to the diameter of the laser beam, enabling the size to be reduced to the diffraction limit of the laser light.

Abstract: There is provided a patterning method which makes it possible to form a desired preferable pattern having no reduction in the pattern thickness in a boundary portion where a group of patterns are joined using a plurality of exposure masks. There is provided a patterning method for forming a group of patterns in which first patterns to serve as basic units are repetitively arranged using a plurality of exposure masks. When a third region sandwiched by a first region exposed with a first exposure mask and a second region exposed with a second exposure mask is exposed with the first and second exposure masks in a complementary manner, repetitive unit patterns for exposing the third region are different from the first patterns.

Abstract: A new method of forming a damascene interconnect in the manufacture of an integrated circuit device has been achieved. The damascene interconnect may be a single damascene or a dual damascene. Copper conductors are provided overlying a semiconductor substrate. A first passivation layer is provided overlying the copper conductors. A low dielectric constant layer is deposited overlying the first passivation layer. An optional capping layer is deposited overlying the low dielectric constant layer. A photoresist layer is deposited overlying the capping layer. The capping layer and the low dielectric constant layer are etched through to form via openings. The photoresist layer is simultaneously stripped away while forming a sidewall passivation layer on the sidewalls of the via openings using a sulfur-containing gas. Sidewall bowing and via poisoning are thereby prevented. The first passivation layer is etched through to expose the underlying copper conductors.

Abstract: A method for capping active areas of a semiconductor wafer uses photolithography to define areas of sealant on the cap wafer to thereby reduce the amount of space required for attaching the cap wafer to the semiconductor wafer carrying active areas to be capped. Using photolithography in this manner increases the amount of space on the semiconductor wafer that can be used to form active areas which, in turn, improves the density of active area on the semiconductor wafer. In one embodiment, the method includes the steps of applying a photoimageable layer, photoimaging the photoimageable layer to define a pattern including remaining regions of the photoimageable layer and removed regions of the photoimageable layer, and using the pattern to define the sealant regions on the semiconductor wafer.

Abstract: Densely disposed patterns constituting a semiconductor integrated circuit device are divided into a first mask pattern and a second mask pattern 28B such that a phase shifter S can be disposed, and a predetermined pattern is transferred on a semiconductor substrate by multiple-exposure thereof. The second mask pattern 28B has a main light transferring pattern 26c1, a plurality of auxiliary light transferring patterns 26c2 disposed thereabout, and a phase shifter S disposed in the main light transferring pattern 26c1. The auxiliary light transferring patterns 26c2 are disposed such that respective distances from a center of each thereof to a center of the main light transferring pattern 26c1 are substantially equal. With this arrangement, a densely disposed pattern is transferred with sufficient process transfer margin.

Abstract: For the purpose of a sufficient exposure tolerance and a sufficient lithographic process tolerance like the depth of focus while reducing the line width difference due to the patter density of a resist pattern without applying a load to fabrication of a mask, correction is made to the overlapping width a1 of a translucent region of a phase shift mask and a shading region of a binary mask used upon high-resolution exposure (isolated pattern), the overlapping width a2 (L/S pattern), line width b1 in a phase shift mask (isolated pattern) and the line width b2 (L/S pattern) toward decreasing the line width difference among resist patterns when a resist pattern having patterns like an isolated pattern and an L/S pattern that are different in pattern density.

Abstract: An improved vacuum plasma etching device for plasma etching semiconductor wafers that have a photo-resist pattern. The improved plasma etching device has a reaction chamber in which the plasma etching is performed during a process cycle, an entrance vacuum loadlock for holding the next semiconductor wafer to be plasma etched, an exit vacuum loadlock for transporting the semiconductor wafers out of the reaction chamber after the plasma etching process, and a source of ultraviolet light. Exposing the semiconductor wafer to the ultraviolet light cures the photo-resist patterns, thereby improving CD dispersion, enhancing pattern transfer, and preventing photo-resist reticulation. Curing the photo-resist patterns while the semiconductor wafer is being held during the process cycle in the entrance vacuum loadlock, increases efficiency and productivity.

Abstract: A highly reliable semiconductor device having an underlying film with a trench and a conducting material film formed in the trench, a method of manufacturing the same and a method of forming a resist pattern used therein are obtained. The underlying film having an upper surface and the trench is formed. The conducting material film is formed on the upper surface and in the trench. A photo resist film is formed on the conducting material film located on the upper surface of the underlying film and in the trench. The photo resist film is left in the trench whereas the photo resist film is developed and removed outside the trench. The conducting material film located on the upper surface of the underlying film is etched and removed with the photo resist film left in the trench used as a mask.

Abstract: The prevention of the formation of undesired defects formed during the etching of etched metal interconnect lines on an integrated circuit during an integrated circuit manufacturing process that involves laying down on a semiconductor wafer a thin film such as an anti-reflective coating (ARC) on a layer of metal to be patterned into the metal interconnects of the individual integrated circuits. To do this the anti-reflective coating layer is covered with an oxide layer prior to applying and patterning subsequent photoresist. The specific metalization layer disclosed can be of aluminum, copper or copper-aluminum alloy. The ARC as disclosed is a nitride layer, such as titanium nitride. The oxide may be formed on the ARC in a number of known ways and may be etched subsequently alone or in combination with the underlying ARC and metal after subsequent photoresist deposit upon the oxide layer.

Abstract: The invention includes methods of making lithography photomask blanks. The invention also includes lithography photomask blanks and preforms for producing lithography photomask. The method of making a lithography photomask blank includes providing a soot deposition surface, producing SiO2 soot particles and projecting the SiO2 soot particles toward the soot deposition surface. The method includes successively depositing layers of the SiO2 soot particle on the deposition surface to form a coherent SiO2 porous glass preform body comprised of successive layers of the SiO2 soot particles and dehydrating the coherent SiO2 glass preform body to remove OH from the preform body. The SiO2 is exposed to and reacted with a fluorine containing compound and consolidated into a nonporous silicon oxyfluoride glass body with parallel layers of striae.

Abstract: A production method for forming contact structures on a planar surface of a substrate and removing therefrom to mount the contact structures on a contact substrate. The contact structure is formed of a base beam which is attached to a surface of the contact substrate in a vertical direction, a horizontal beam which is connected to the base beam at one end, and a top beam formed on another end of the horizontal beam and is oriented in the vertical direction. The production method includes the steps of forming a sacrificial layer on a silicon substrate, forming, exposing and developing a photoresist layer, depositing conductive material on the photoresist layer to form the contact structures, and removing the photoresist layer and the sacrificial layer to separate the contact structures from the silicon substrate.

Abstract: A process is revealed whereby resistors can be manufactured integral with the printed circuit board by plating the resistors onto the insulative substrate. Uniformization of the insulative substrate through etching and oxidation of the plated resistor are revealed as techniques for improving the uniformity and consistency of the plated resistors.

Abstract: It is an object of the present invention to provide a cleaning method of and a cleaning apparatus for removing organic matters such as phthalates that have deposited on the surface of a semiconductor substrate while restraining the growth of a natural oxide film. The present invention provides a method of cleaning a semiconductor substrate, which comprises irradiating a semiconductor substrate contaminated by organic matters such as phthalic acid, phthalate and derivatives thereof with vacuum ultraviolet light having a wavelength within a range from 165 to 179 nm in an atmosphere of oxygen or air that is introduced from an O2 or air intake port, thereby decomposing and removing the contaminant.

Abstract: For allowing processing of a material into an intended three-dimensional configuration having different processed depths while suppressing an influence exerted on a processed configuration by a configuration of a transparent portion, a processing device includes an SR light source 1 for emitting SR light, an X-ray mask having a transparent portion of a predetermined configuration for passing the X-rays emitted from the SR light source 1, and exposure stage 3 for oscillating the X-ray mask and the material relatively to each other in accordance with a movement pattern determined based on the processing configuration of the processing material for moving the X-ray mask and the material relatively to each other and thereby oscillating the region where the material is irradiated with the X-ray passed through the transparent opening.

Abstract: Provided is a method for producing regularly ordered narrow pores excellent in linearity, and a structure with such narrow pores. A method for producing a narrow pore comprises a step of radiating a particle beam onto a workpiece, and a step of carrying out anodic oxidation of the workpiece having been irradiated with the particle beam, to form a narrow pore in the workpiece.

Abstract: A method for simultaneously stripping a photoresist mask employed for etching, in a low pressure, high density plasma processing chamber, a contact hole through an oxide layer to a silicon layer of a substrate and soft etching a surface of the silicon layer at a bottom of the contact hole. The technique of simultaneously stripping and soft etching is configured to substantially remove the photoresist mask and reducing a contact resistance at the bottom of the contact hole simultaneously. The method includes flowing an etchant source gas comprising a fluorocarbon and O2into the plasma processing chamber after the contact hole is formed but prior to filling the contact hole with a substantially conductive material. There is also included forming a plasma from the etchant source gas.

Abstract: A method for forming high frequency connections between a fragile chip and a substrate is described, wherein metal is selectively deposited on a surface of a chip and a surface of a substrate, and corresponding patterns of electrically conductive bumps are selectively evaporated on the surface of the chip and the surface of the substrate over the metal layers, to form a pattern of electrically conductive bumps having spongy and dendritic properties, placing the chip in aligned contact with the substrate where each electrically conductive chip bump mates with each corresponding electrically conductive substrate bump, and selectively applying heat and pressure to the chip and substrate causing each chip bump to fuse together with each corresponding substrate bump to form an electromechanical bond.

Abstract: Stepped photoresist profiles provide various methods of forming profiles in an underlying substrate. The stepped photoresist profiles are formed in two layers of photoresist that are disposed over the substrate. The substrate is then etched twice using a respective opening in each photoresist layer to create a stepped profile in the substrate.

Abstract: In one aspect, the invention includes a semiconductor processing method comprising: a) forming a layer comprising boron and nitrogen over a substrate; b) forming a photoresist over the layer comprising boron and nitrogen; and c) exposing one or more portions of the photoresist to light to pattern the photoresist. In another aspect, the invention includes a semiconductor processing method comprising: a) forming a layer comprising boron nitride over a substrate; b) forming a layer of photoresist over the layer comprising boron nitride; c) exposing portions of the photoresist to light while leaving other portions of the photoresist unexposed, some light passing through the photoresist during the exposing; d) absorbing light passing through the photoresist with the layer comprising boron nitride; and e) selectively removing either the exposed or unexposed portions of the photoresist while leaving the other of the exposed and unexposed portions over the substrate to pattern the photoresist.

Abstract: A method and an apparatus for editing an integrated circuit. In one embodiment, an integrated circuit substrate is placed into a laser chemical vapor deposition (LCVD) tool and a conductive metal film is deposited onto the integrated circuit substrate over an area of interest. The integrated circuit substrate is subsequently placed into a focused ion beam (FIB) tool where an optional FIB cleaning step is performed on the conductive element deposited by the LCVD tool to help ensure that a good electrical contact can be made. The FIB tool is also used to introduce any desired cuts into signal lines of the integrated circuit to complete edits. The FIB is also used to remove passivation over integrated circuit nodes of interest to expose buried metal lines for subsequent coupling to the conductive element deposited with the LCVD tool.

Abstract: The specification describes a trilevel resist technique for defining metallization patterns by lift-off. The trilevel resist comprises two standard photoresist levels separated by a thin silicon oxide layer with approximate composition SiO.sub.2.

Abstract: The present invention provides a plasma processing system comprising a remote plasma activation region for formation of active gas species, a transparent transfer tube coupled between the remote activation region and a semiconductor processing chamber, and a source of photo energy for maintaining activation of the active species during transfer from the remote plasma activation region to the processing chamber. The source of photo energy preferably includes an array of UV lamps. Additional UV lamps may also be used to further sustain active species and assist plasma processes by providing additional in-situ energy through a transparent window of the processing chamber.

Abstract: Semiconductor fabrication methods for processing materials on a semiconductor wafer are disclosed. An exemplary method the semiconductor fabrication apparatus comprises processing a material on a semiconductor assembly during semiconductor fabrication, by the steps of: precleaning a semiconductor assembly in ultraviolet radiation, the step of precleaning performed prior to the step of forming; forming a film in ultraviolet radiation and infrared radiation; annealing the film ultraviolet light radiation and infrared radiation.

Abstract: A method for manufacturing a self-aligned stacked storage node DRAM cell on a substrate for a capacitor over bit line (COB) process is disclosed.

Abstract: A photo-resist mask is removed from an inter-level insulating structure by using plasma produced from N.sub.x H.sub.y gas, and the plasma does not make an organic insulating layer forming part of the inter-level insulating structure hygroscopic, because SiCH.sub.3 bond is never replaced with Si--OH bond during the removal of the photo-resist mask.

Abstract: A method for removing native oxides and other contaminants from a wafer surface while minimizing the loss of a desired film on the wafer surface. The method is carried out in a hermetically sealed reactor. A fluorine-containing gas or gas mixture is passed over the wafer during simultaneous exposure to ultraviolet radiation in the absence of added water, hydrogen, hydrogen fluoride or hydrogen containing organics, thereby avoiding the production of water as a reaction product. The addition of ultraviolet radiation and the elimination of water, hydrogen, hydrogen fluoride and hydrogen containing organics provides for the nearly equivalent (non-selective) removal of various forms of oxide and also provides for improved process control.

Abstract: The invention provides generally a method and an apparatus for in situ cleaning of a surface in a semiconductor substrate processing chamber which operates quickly and reduces the downtime for chamber cleaning. The apparatus comprises an ultraviolet (UV) radiation plate moveable between a cleaning position and a storage position and at least one UV radiation source disposed on the UV radiation plate. Preferably, the apparatus includes a reflector disposed adjacent the UV radiation source to focus emitted UV radiation and a rotary actuator pivotally attached to a transport arm to move the UV radiation plate between the cleaning position and the storage position. The method comprises: providing a UV radiation plate having at least one UV radiation source disposed thereon, moving the UV radiation plate into a cleaning position, introducing a cleaning gas into the processing chamber and exposing the surface to UV radiation.

Abstract: A method for forming a plurality of self-aligned via holes applied to a semiconductor device is disclosed. The method includes steps of (a) providing a substrate forming thereon a conducting layer forming thereon a sacrificial layer; (b) partially removing the sacrificial layer while retaining a plurality of sacrificial via pillars, and removing portions of the conducting layer under the removed sacrificial layer; (c) forming a first insulating layer between the plurality of the sacrificial via pillars, and then planarizing the first insulating layer to expose tops of the plurality of sacrificial via pillars; and (d) removing the plurality of the sacrificial via pillars while retaining the first insulating layer to form the plurality of the self-aligned via holes. By the above-described method, the formed via holes are self-aligned to the underlying metal lines and pads and less photolithography equipment requirement is needed to define fine via holes.

Abstract: A method for stripping photoresist used as an etch mask in carbon based reactive ion etching includes flood exposing a patterned photoresist with a light and cyclically exposing the photoresist with an oxygen plasma in between the carbon based plasma. The step of cyclically exposing occurs after the step of flood exposing. The step of flood exposing includes the step of decomposing photosensitive compounds in the photoresist, while the step of cyclically exposing includes the step of cyclically removing layers of the photoresist.

Abstract: A method of fabricating a semiconductor component, the method including at least one step of etching an upper layer formed on a substrate. In the method, prior to forming the upper layer, at least one set made up of marker layers separated by intermediate layers of predetermined thicknesses is caused to be grown, where the marker layers and adjacent intermediate layers have different refractive indices, and then during etching of the upper layer refractive index discontinuities are detected optically and etching is stopped when the sequence of the optically detected discontinuities corresponds to a reference sequence representative of the thicknesses of the intermediate layers.

Abstract: The gate oxide film is prevented from being thinned partially. The semiconductor substrate (wafer) can be etched (processed) under excellent conditions. The impurities on the wafer surface can be analyzed and further reduced. In the first aspect, the substrate is irradiated with ultraviolet rays in contact with an F-containing aqueous solution, so that the oxide film and the substrate can be etched at roughly the same etching speed under excellent controllability without deteriorating the planarization of the substrate. In the second aspect, the substrate is etched by irradiating ultraviolet rays during exposure to an acid aqueous solution, so that surface metallic contamination and particles can be removed without deteriorating the wafer surface roughness. Further, the impurity elements in the outermost surface layer of the wafer can be analyzed at high precision by analyzing elements contained in the acid aqueous solution used for the etching.

Abstract: Deposition rates of undoped silicate glass dielectric layers on thermal oxide are increased by pre-treating the thermal oxide layer with electromagnetic radiation in the ultraviolet (UV) and/or vacuum ultraviolet (VUV) wavelengths. The surface smoothness of the resulting films are also increased by pre-treating films with UV and/or VUV radiation. Furthermore, the gap filling abilities of the undoped silicate glass films are increased by pre-treating the thermal oxide with UV and/or VUV radiation. New equipment and methods are presented for exposing semiconductor devices to UV and/or VUV radiation, and for enhancing the deposition rates and film quality for semiconductor manufacture. Semiconductor devices incorporating the new methods are also described.

Abstract: The present invention discloses a method for forming a DRAM capacitor that has improved charge storage capacity by utilizing a deposition process wherein alternating layers of doped and undoped dielectric materials are first deposited, a deep UV type photoresist layer is then deposited on top of the oxide layers such that during a high density plasma etching process for the cell opening, acidic reaction product is generated by the photoresist layer when exposed to UV emission in an etch chamber such that the sidewall of the cell opening is etched laterally in an uneven manner, i.e., the doped dielectric layer being etched more severely than the undoped dielectric layer thus forming additional surface area and an improved charge storage capacity for the capacitor formed.

Abstract: Apparatus and process for conditioning a generally planar substrate, contained in a chamber isolatable from the ambient environment and fed with a conditioning gas which includes a reactive gas. The apparatus includes a support for supporting the substrate in the chamber, the substrate being in a lower pressure reaction region of the chamber. A gas inlet is provided for feeding conditioning gas into a gas inlet region of the chamber which is at a higher pressure than the lower pressure reaction region so that the pressure differential causes the conditioning gas to flow toward the surface of the substrate wherein the conditioning gas component will chemically react with and condition the substrate surface, both said higher and lower pressure regions operating in a viscous flow regime.

Abstract: A method for processing semiconductor materials such as a crystalline ingot or a wafer and an apparatus employed therein. An etching gas is supplied on the surface of a semiconductor material, while laser irradiation or light quantum irradiation is applied on a predetermined part of the semiconductor material surface, whereby a component of the etching gas is excited, reacted with a component of the semiconductor material and evaporated for elimination. Thereby, semiconductor materials can be processed hygienically, easily and with high precision.

Abstract: Disclosed is a method for selectively etching an opening in order to reduce cusping on and thereby widen the opening. The opening in one embodiment comprises a contact opening with a diffusion barrier liner layer deposited thereover that has formed cusps at the mouth of the contact opening. The contact opening is exposed to an etching agent at a low temperature and pressure such that the etching agent adheres to the contact opening. Photons are then directed towards the contact opening at an acute angle to the surface of the contact opening. The acute angle causes the surface of the contact opening to block the photons from contacting the bottom of the contact opening with a high flux density. The photons impart an energy to activate the etching agent, causing substantial etching of an upper portion of the contact opening, while a lower portion does not receive a significant flux density and is not substantially etched.

Abstract: A method for staining a wafer containing a semiconductor device is disclosed which properly delineates the various layers of the semiconductor device and provides good contrast for proper testing and diagnosis of problems using a scanning electron microscope. After grinding, lapping and polishing a surface of the semiconductor device, the surface is ion beam etched, reactive ion etched and stained. The staining solution is made from 1 part by volume hydrofluoric acid, 3 parts by volume nitric acid, and 6 parts by volume acetic acid. The staining solution is cooled and subjected to a light to slow the reaction of the staining solution with the semiconductor device. This prevents structure collapse and under or over etching, and provides an easily controllable staining process.

Abstract: The invention relates to a method for cleaning vias in electronic component substrates prior to metallization thereof.

Abstract: The present invention is directed to a process for fabricating a semiconductor integrated circuit device, and specifically, a process for cleaning a silicon substrate before gate silicon dioxide is formed on the silicon substrate. The gate silicon dioxide is used to form transistor gates. The process of the present invention provides a silicon/silicon dioxide interface and the bulk silicon dioxide with advantageous electrical properties. In the present process, the silicon substrate is first subjected to a stream of hydrofluoric acid (HF) vapor. The vapor HF stream is a mixture of anhydrous HF, methanol, and nitrogen. Following this, the substrate is subjected to gaseous chlorine that has been irradiated with broad band UV radiation. After the substrate has been cleaned according to the present process, a layer of silicon dioxide is grown thereon using conventional techniques such as rapid thermal oxidation (RTO).

Abstract: A method for dry etching of transition metals. The method for dry etching of a transition metal (or a transition metal alloy such as a silicide) on a substrate comprises providing at least one nitrogen- or phosphorous-containing .pi.-acceptor ligand in proximity to the transition metal, and etching the transition metal to form a volatile transition metal/.pi.-acceptor ligand complex. The dry etching may be performed in a plasma etching system such as a reactive ion etching (RIE) system, a downstream plasma etching system (i.e. a plasma afterglow), a chemically-assisted ion beam etching (CAIBE) system or the like. The dry etching may also be performed by generating the .pi.-acceptor ligands directly from a ligand source gas (e.g. nitrosyl ligands generated from nitric oxide), or from contact with energized particles such as photons, electrons, ions, atoms, or molecules.

Abstract: A photoelectric transfer device having a light receiving element and a signal processing circuit are formed in a semiconductor substrate, a silicon oxide film is formed on the light receiving element, a first aluminum thin film is deposited on the silicon substrate, and the first aluminum thin film is patterned to make a wire connected with the signal processing circuit and a protective film placed on the silicon oxide film. Thereafter, an inter-layer insulating film is deposited on the silicon substrate while covering the protective film, a portion of the inter-layer insulating film placed on the protective film is etched and removed, a second aluminum thin film is deposited on the inter-layer insulating film and the protective film, and a portion of the second aluminum thin film placed on the protective film and the protective film are successively etched and removed.

Abstract: According to the present invention, the surface of the sample is cleaned with water immediately after ashing of the resist the quality of which has been changed through ion implantation by ozone-containing gas, or ozone-containing gas and ultraviolet ray, or the sample is cleaned with water without being exposed to the atmosphere after ashing, thereby allowing the number of residues to be reduced to 1/100, decreasing the load in cleaning process by solution, cutting down the semiconductor device production cost and improving the semiconductor device productivity.

Abstract: Effective etching of several materials, including gallium nitride and gallium arsenide, without post etch surface damage has been achieved by using a mix of equal proportions of chlorine and methane. A sample is first cooled to a temperature of around 140.degree. K and is then irradiated by a series of pulses from a UV laser (for example a 193 nm ArF excimer laser). Using fluences of about 400 mJ/cm.sup.2 per pulse at repetition rates of about 10 pulses/second, an etch rate for gallium nitride of about 0.7 Angstroms per pulse was achieved. Typical pressure for the chlorine methane mix was about 2 mtorr. To achieve selective etching a number of approaches are possible including contact masking, projection printing, raster scanning, and moveable shadow masking with collimated laser light.

Abstract: A native oxide film is formed on the surface of a silicon substrate. The native oxide film has at least island-shaped imperfect SiO.sub.2 regions not formed with a perfect SiO.sub.2 film. Before the native oxide film is formed, a mask layer having a necessary opening is formed over the silicon substrate, according to necessity. The silicon substrate is etched in a vapor phase via the imperfect SiO.sub.2 regions of the native oxide film to form a hollow under the native oxide film at least at a partial region thereof. An upper film is formed on the native oxide film to cover and close the imperfect SiO.sub.2 regions. In this manner, a minute hollow can be formed in the silicon substrate with good controllability.

Abstract: An apparatus for processing substrates, the apparatus including a plurality of molecular dissociation furnaces. Each dissociation furnace produces a directed beam of neutral dissociated reactive species. Each reactive beam is directed at a surface of the semiconductor substrate. A photon source is also directed at the surface of the semiconductor substrate. The intensity and wavelength of the photon source are selected to enhance the reaction rate over that of the reactive beam acting alone on the surface.

Abstract: The invention relates to a method and to apparatus for processing a specimen, particularly an integrated circuit, in which an area of the specimen to be processed is scanned with a corpuscular beam and at least one gas is supplied above the area to be processed so that with the aid of the corpuscular beam a chemical reaction takes place on the area to be processed. The processing speed can be markedly increased by the use of a magnetic field in the region of the probe.