With Substrate Heating Or Cooling Patents (Class 438/715)
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Publication number: 20140295671Abstract: A plasma processing apparatus is provided which includes a processing chamber disposed in a vacuum container, in a decompressed inside of which plasma is formed, a sample stage disposed in a lower part of the processing chamber, on a top surface of which a sample is mounted, a dielectric film made of a dielectric that forms a mounting surface on which the sample is mounted, and electrodes arranged inside the dielectric film and supplied with power for chucking and holding the sample onto the dielectric film, and when the sample is mounted on the sample stage, the sample is kept mounted on the sample stage until a sample temperature becomes a predetermined temperature or until a predetermined time elapses, and power is then supplied to the electrodes to chuck the sample to the sample stage and then start processing on the sample using the plasma.Type: ApplicationFiled: February 19, 2014Publication date: October 2, 2014Inventors: Kohei Sato, Yuya Mizobe, Tomohiro Ohashi
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Patent number: 8841152Abstract: Method for making a patterned thin film of an organic semiconductor. The method includes condensing a resist gas into a solid film onto a substrate cooled to a temperature below the condensation point of the resist gas. The condensed solid film is heated selectively with a patterned stamp to cause local direct sublimation from solid to vapor of selected portions of the solid film thereby creating a patterned resist film. An organic semiconductor film is coated on the patterned resist film and the patterned resist film is heated to cause it to sublime away and to lift off because of the phase change.Type: GrantFiled: May 7, 2012Date of Patent: September 23, 2014Assignee: Massachusetts Institute of TechnologyInventors: Matthias Erhard Bahlke, Marc A. Baldo, Hiroshi Antonio Mendoza
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Publication number: 20140273488Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.Type: ApplicationFiled: April 7, 2014Publication date: September 18, 2014Applicant: APPLIED MATERIALS, INC.Inventors: Anchuan Wang, Xinglong Chen, Zihui Li, Hiroshi Hamana, Zhijun Chen, Ching-Mei Hsu, Jiayin Huang, Nitin K. Ingle, Dmitry Lubomirsky, Shankar Venkataraman, Randhir Thakur
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Patent number: 8835327Abstract: A method of manufacturing a semiconductor device disclosed herein includes: mounting a substrate on an electrostatic chuck placed inside a chamber, the electrostatic chuck having a first temperature and the substrate being retained in advance in an atmosphere having a second temperature lower than the first temperature; fixing the substrate onto the electrostatic chuck by applying a voltage to the electrostatic chuck; heating the electrostatic chuck to a third temperature higher than the first temperature and the second temperature after mounting the substrate; and processing the substrate after the heating.Type: GrantFiled: January 22, 2013Date of Patent: September 16, 2014Assignee: Fujitsu LimitedInventors: Masanori Terahara, Hikaru Kokura, Akihiro Hasegawa, Atsuo Fushida, Fumihiko Akaboshi
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Patent number: 8828881Abstract: The invention discloses an etch-back method for planarization at the position-near-interface of an interlayer dielectric (ILD), comprising: depositing or growing a thick layer of SiO2 by the chemical vapor deposition or oxidation method on a surface of a wafer; spin-coating a layer of SOG and then performing a heat treatment to obtain a relatively uniform stack structure; perform an etch-back on the SOG using a plasma etching, and stopping when approaching the position-near-interface of SiO2; performing a plasma etch-back on the remaining SOG/SiO2 structure at the position-near-interface until achieving a desired thickness. Since a two-step etching at the position-near-interface is employed, an extremely good smooth surface of the ILD is obtained. That is, a planar and tidy surface of the ILD is obtained not only in the center region, but also even at the edge of the wafer.Type: GrantFiled: August 10, 2011Date of Patent: September 9, 2014Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Lingkkuan Meng, Huaxiang Yin
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Patent number: 8828776Abstract: Multi-zone, solar cell diffusion furnaces having a plurality of radiant element (SiC) or/and high intensity IR lamp heated process zones, including baffle, ramp-up, firing, soaking and cooling zone(s). The transport of solar cell wafers, e.g., silicon, selenium, germanium or gallium-based solar cell wafers, through the furnace is implemented by use of an ultra low-mass, wafer transport system comprising laterally spaced shielded, synchronously driven, metal bands or chains carrying non-rotating alumina tubes suspended on wires between them. The wafers rest on raised circumferential standoffs spaced laterally along the alumina tubes, which reduces contamination. The high intensity IR flux rapidly photo-radiation conditions the wafers so that diffusion occurs >3× faster than conventional high-mass thermal furnaces. Longitudinal side wall heaters comprising coil heaters in Inconel sheaths inserted in carrier tubes are employed to insure even heating of wafer edges adjacent the side walls.Type: GrantFiled: July 2, 2012Date of Patent: September 9, 2014Assignee: TP Solar, Inc.Inventors: Richard W. Parks, Luis Alejandro Rey Garcia, Peter G. Ragay
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Patent number: 8822877Abstract: Rapid thermal processing systems and associated methods are disclosed herein. In one embodiment, a method for heating a microelectronic substrate include generating a plasma, applying the generated plasma to a surface of the microelectronic substrate, and raising a temperature of the microelectronic substrate with the generated plasma applied to the surface of the microelectronic substrate. The method further includes continuing to apply the generated plasma until the microelectronic substrate reaches a desired temperature.Type: GrantFiled: April 23, 2013Date of Patent: September 2, 2014Assignee: Micron Technology, Inc.Inventor: Shu Qin
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Publication number: 20140242802Abstract: A semiconductor process includes the following steps. A wafer on a pedestal is provided. The pedestal is lifted to approach a heating source and an etching process is performed on the wafer. An annealing process is performed on the wafer by the heating source. In another way, a wafer on a pedestal, and a heating source on a same side of the wafer as the pedestal are provided. An etching process is performed on the wafer by setting the temperature difference between the heating source and the pedestal larger than 180° C.Type: ApplicationFiled: February 25, 2013Publication date: August 28, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia Chang Hsu, Kuo-Chih Lai, Chun-Ling Lin, Bor-Shyang Liao, Pin-Hong Chen, Shu Min Huang, Min-Chung Cheng, Chi-Mao Hsu
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Patent number: 8809197Abstract: In a control method, a first processing is performed on an object to be processed by controlling a temperature of a base to a first temperature and controlling a temperature of an electrostatic chuck that is disposed on a mounting surface of the base so as to mount thereon the object to be processed and has a heater installed therein to a second temperature. A second processing is performed on the object by controlling a temperature of the base to a third temperature and controlling a temperature of the electrostatic chuck to a fourth temperature by a heater. In the control method, a difference between the first temperature and the second temperature and a difference between the third temperature and the fourth temperature are within a tolerable temperature of the junction layer for bonding the base and the electrostatic chuck.Type: GrantFiled: August 29, 2013Date of Patent: August 19, 2014Assignee: Tokyo Electron LimitedInventor: Atsuhiko Tabuchi
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Patent number: 8796153Abstract: An electrode assembly for a plasma reaction chamber used in semiconductor substrate processing. The assembly includes an upper showerhead electrode which is mechanically attached to a backing plate by a series of spaced apart cam locks. A guard ring surrounds the backing plate and is movable to positions at which openings in the guard ring align with openings in the backing plate so that the cam locks can be rotated with a tool to release locking pins extending from the upper face of the electrode.Type: GrantFiled: March 11, 2013Date of Patent: August 5, 2014Assignee: Lam Research CorporationInventors: Roger Patrick, Gregory R. Bettencourt, Michael C. Kellogg
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Patent number: 8791025Abstract: The method of producing a GaN-based microstructure includes a step of preparing a semiconductor structure provided with a trench formed in a main surface of the nitride semiconductor and a heat-treating mask covering a main surface of the nitride semiconductor excluding the trench, a first heat-treatment step of heat-treating the semiconductor structure under an atmosphere containing nitrogen element to form a crystallographic face of the nitride semiconductor on at least a part of a sidewall of the trench, a step of removing the heat-treating mask after the first heat-treatment step and a second heat-treatment step of heat-treating the semiconductor structure under an atmosphere containing nitrogen element to close an upper portion of the trench on the sidewall of which the crystallographic face is formed with a nitride semiconductor.Type: GrantFiled: July 27, 2010Date of Patent: July 29, 2014Assignee: Canon Kabushiki KaishaInventors: Shoichi Kawashima, Takeshi Kawashima, Yasuhiro Nagatomo, Katsuyuki Hoshino
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Publication number: 20140206198Abstract: One embodiment of the deposit removal method includes: preparing a substrate having a pattern on which a deposit is deposited, the pattern being formed by etching; exposing the substrate to a first atmosphere containing hydrogen fluoride gas; exposing the substrate to oxygen plasma while heating after the step of exposing the substrate to the first atmosphere; and exposing the substrate to a second atmosphere containing hydrogen fluoride gas to remove the deposit on the substrate after the step of exposing the substrate to the oxygen plasma.Type: ApplicationFiled: March 24, 2014Publication date: July 24, 2014Applicants: KABUSHIKI KAISHA TOSHIBA, TOKYO ELECTRON LIMITEDInventors: Shigeru TAHARA, Eiichi NISHIMURA, Takanori MATSUMOTO
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Patent number: 8778806Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.Type: GrantFiled: April 17, 2012Date of Patent: July 15, 2014Assignee: Plasma-Therm LLCInventors: Chris Johnson, David Johnson, David Pays-Volard, Linnell Martinez, Russell Westerman, Gordon M. Grivna
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Publication number: 20140179110Abstract: Methods and apparatus for processing a germanium containing material, a III-V compound containing material, or a II-VI compound containing material disposed on a substrate using a hot wire source are provided herein. In some embodiments, a method for processing a material disposed on a substrate, wherein the material is at least one of a germanium containing material, a III-V compound containing material, or a II-VI compound containing material, includes providing a hydrogen containing gas to a first process chamber having a plurality of filaments; flowing a current through the plurality of filaments to raise a temperature of the plurality of filaments to a first temperature sufficient to decompose at least a portion of the hydrogen containing gas to form hydrogen atoms; and treating a surface of an exposed material on a substrate by exposing the material to hydrogen atoms formed by the decomposition of the hydrogen containing gas.Type: ApplicationFiled: December 16, 2013Publication date: June 26, 2014Applicant: APPLIED MATERIALS, INC.Inventors: JEONGWON PARK, JOE GRIFFITH CRUZ, PRAVIN K. NARWANKAR
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Publication number: 20140175567Abstract: Conducting materials having narrow impurity conduction bands can reduce the number of high energy excitations, and can be prepared by a sequence of plasma treatments. For example, a dielectric layer can be exposed to a first plasma ambient to form vacancy sites, and the vacancy-formed dielectric layer can be subsequently exposed to a second plasma ambient to fill the vacancy sites with substitutional impurities.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: INTERMOLECULAR, INC.Inventors: Sergey Barabash, Dipankar Pramanik
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Publication number: 20140154888Abstract: Showerhead electrode assemblies are disclosed, which include a showerhead electrode adapted to be mounted in an interior of a vacuum chamber; an optional backing plate attached to the showerhead electrode; a thermal control plate attached to the backing plate or to the showerhead electrode at multiple contact regions across the backing plate; and at least one interface member separating the backing plate and the thermal control plate, or the thermal control plate and showerhead electrode, at the contact regions, the interface member having a thermally and electrically conductive gasket portion and a particle mitigating seal portion. Methods of processing semiconductor substrates using the showerhead electrode assemblies are also disclosed.Type: ApplicationFiled: February 3, 2014Publication date: June 5, 2014Applicant: Lam Research CorporationInventors: Tom Stevenson, Rajinder Dhindsa
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Publication number: 20140154819Abstract: A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate, the thermal control elements defining heater zones each of which is powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones. A power distribution circuit is mated to a baseplate of the substrate support, the power distribution circuit being connected to each power supply line and power return line of the heater array. A switching device is connected to the power distribution circuit to independently provide time-averaged power to each of the heater zones by time divisional multiplexing of a plurality of switches.Type: ApplicationFiled: November 30, 2012Publication date: June 5, 2014Applicant: LAM RESEARCH CORPORATIONInventors: Keith William Gaff, Tom Anderson, Keith Comendant, Ralph Jan-Pin Lu, Paul Robertson, Eric A. Pape, Neil Benjamin
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Patent number: 8722547Abstract: Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.Type: GrantFiled: April 17, 2007Date of Patent: May 13, 2014Assignee: Applied Materials, Inc.Inventors: Radhika Mani, Nicolas Gani, Wei Liu, Meihua Shen, Shashank C. Deshmukh
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Patent number: 8709952Abstract: Provided is an etching method capable of etching even a silicon film that is included in a multi-layered structure by using a resist film or an organic film as a mask, and also capable of integrally etching the silicon film and a silicon oxide film disposed under the silicon film. The etching method which etches the multi-layered structure including the silicon oxide film and the silicon film formed on the silicon oxide film, includes: integrally etching the silicon film and the silicon oxide film included in the multi-layered structure by using a resist film or an organic film as an etching mask and using an etching gas containing a CH2F2 gas as an etching gas, when the silicon film and the silicon oxide film in the multi-layered structure are etched.Type: GrantFiled: March 14, 2012Date of Patent: April 29, 2014Assignee: Tokyo Electron LimitedInventor: Aki Akiba
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Patent number: 8709953Abstract: Ultrathin material layers are plasma etched with an etch system configured for cryogenic cooling of a substrate to reduce the diffusion coefficients of foreign and intrinsic stop layer atoms (e.g., of the bombarded crystal lattice), and further configured for plasma pulsing to reduce the energy of the impinging ions with cryogenic wafer temperatures. Substrate temperatures of ?50° C. or more are employed to reduce the susceptibility of a stop layer material to damage associated with ion impact. Ion energy is reduced to below the threshold where stop layer lattice atoms are displaced or ions are implanted into the bulk lattice. In embodiments, a plasma of an etchant gas having ion energies less than 10 eV are achieved through plasma pulsing, which when directed at the low temperature substrate may controllably etch ultra-thin material layers.Type: GrantFiled: October 17, 2012Date of Patent: April 29, 2014Assignee: Applied Materials, Inc.Inventors: Thorsten Lill, Klaus Schuegraf, Dmitry Lubomirsky
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Patent number: 8709848Abstract: MEMS devices (40) using etched cavities (42) are desirably formed using multiple etching steps. Preliminary cavities (20) formed by locally anisotropic etching to nearly the final depth have irregular (46) sidewalls (44) and steep and/or inconsistent sidewall (44) to bottom (54) intersection angles (48). This leads to less than desired cavity diaphragm (26) burst strengths. Final cavities (42) with smooth sidewalls (50), smaller and consistent sidewall (50) to bottom (54) intersection angles (58), and having more than doubled cavity diaphragm (26) burst strengths are obtained by treating the preliminary cavities (20) with TMAH etchant, preferably relatively dilute TMAH etchant. In a preferred embodiment, a cleaning step is performed between the etching step and the TMAH treatment step to remove any anisotropic etching by-products present on the preliminary cavities' (20) initial sidewalls (44).Type: GrantFiled: April 15, 2011Date of Patent: April 29, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Srivatsa G. Kundalgurki, Scott Dye
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Patent number: 8697534Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.Type: GrantFiled: September 12, 2012Date of Patent: April 15, 2014Assignee: NGK Spark Plug Co., Ltd.Inventors: Motohiko Sato, Kazuhiro Hayashi, Kenji Murakami, Motonobu Kurahashi, Yusuke Kaieda, Jun Otsuka, Manabu Sato
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Publication number: 20140099795Abstract: Methods and apparatus for processing a substrate are provided. In some embodiments, a method of processing a substrate having a first layer may include disposing a substrate atop a substrate support in a lower processing volume of a process chamber beneath an ion shield having a bias power applied thereto, the ion shield comprising a substantially flat member supported parallel to the substrate support, and a plurality of apertures formed through the flat member, wherein the ratio of the aperture diameter to the thickness flat member ranges from about 10:1-1:10; flowing a process gas into an upper processing volume above the ion shield; forming a plasma from the process gas within the upper processing volume; treating the first layer with neutral radicals that pass through the ion shield; and heating the substrate to a temperature of up to about 550 degrees Celsius while treating the first layer.Type: ApplicationFiled: October 2, 2013Publication date: April 10, 2014Applicant: APPLIED MATERIALS, INC.Inventors: JEFFREY TOBIN, BERNARD L. HWANG, CANFENG LAI, LARA HAWRYLCHAK, WEI LIU, JOHANES SWENBERG
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Publication number: 20140094036Abstract: Methods for processing a substrate are described herein. Methods can include positioning a substrate comprising silicon in a processing chamber, delivering a plasma to the surface of the substrate while biasing the substrate, exposing the surface of the substrate to ammonium fluoride (NH4F), and annealing the substrate to a first temperature to sublimate one or more volatile byproducts.Type: ApplicationFiled: September 19, 2013Publication date: April 3, 2014Inventors: David T. OR, Joshua COLLINS, Mei CHANG
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Patent number: 8679359Abstract: The present invention is directed to a method and apparatus for etching various metals that may be used in semiconductor or integrated circuit processing through the use of non-halogen gases such as hydrogen, helium, or combinations of hydrogen and helium with other gases such as argon. In one exemplary embodiment of the present invention, in a reaction chamber, a substrate having a metal interconnect layer deposited thereon is exposed to a plasma formed of non-halogen gas. The plasma generated is maintained for a certain period of time to provide for a desired or expected etching of the metal. In some embodiments, the metal interconnect layer may be copper, gold or silver.Type: GrantFiled: May 10, 2011Date of Patent: March 25, 2014Assignee: Georgia Tech Research CorporationInventors: Fangyu Wu, Dennis W. Hess, Galit Levitin
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Patent number: 8668837Abstract: A method for etching a substrate includes etching at least one first layer of the substrate with a non-uniform substrate temperature and etching at least one second layer of the substrate with uniform substrate temperatures.Type: GrantFiled: April 25, 2012Date of Patent: March 11, 2014Assignee: Applied Materials, Inc.Inventors: Kenny Linh Doan, Jong Mun Kim
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Patent number: 8657961Abstract: Embodiments of the invention generally provide methods for cleaning a UV processing chamber. In one embodiment, the method includes flowing an oxygen-containing gas through a plurality of passages formed in a UV transparent gas distribution showerhead and into a processing region located between the UV transparent gas distribution showerhead and a substrate support disposed within the thermal processing chamber, exposing the oxygen-containing gas to UV radiation under a pressure scheme comprising a low pressure stage and a high pressure stage to generate reactive oxygen radicals, and removing unwanted residues or deposition build-up from exposed surfaces of chamber components presented in the thermal processing chamber using the reactive oxygen radicals.Type: GrantFiled: April 4, 2013Date of Patent: February 25, 2014Assignee: Applied Materials, Inc.Inventors: Bo Xie, Alexandros T. Demos, Scott A. Hendrickson, Sanjeev Baluja, Juan Carlos Rocha-Alvarez
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Patent number: 8658048Abstract: The present invention aims to prevent decreases in etching rate due to adhesion of an etched film to a substrate holder. A method of manufacturing a magnetic recording medium includes: forming a first film on a substrate holder not yet having a substrate mounted thereon; mounting a substrate on the substrate holder having the first film formed thereon, the substrate having a resist layer formed on a multilayer film including a magnetic film layer, the resist layer having a predetermined pattern; and processing the magnetic film layer into a shape based on the predetermined pattern by performing dry etching on the substrate. The first film is a film that is not etched as easily as the films in the multilayer film to be removed by the dry etching.Type: GrantFiled: October 31, 2011Date of Patent: February 25, 2014Assignee: Canon Anelva CorporationInventors: Kazuto Yamanaka, Shogo Hiramatsu
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Patent number: 8652970Abstract: A processing gas is introduced to remove an oxide film on the surface of a silicon substrate 5. F radicals are allowed to act on the surface of the silicon substrate to etch a silicon layer. Then, NH3 gas, N2 gas and NF3 gas are introduced, allowing NHxFy to act on the oxidized surface of the silicon substrate 5, thereby forming (NH4)2SiF6. The resulting (NH4)2SiF6 is sublimated to remove by-products (SiOF, SiOH) on the surface of the silicon substrate 5.Type: GrantFiled: March 24, 2010Date of Patent: February 18, 2014Assignee: Ulvac, Inc.Inventors: Yoshiyasu Tajima, Seiichi Takahashi, Kyuzo Nakamura
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Patent number: 8647980Abstract: Disclosed is a method of forming wiring. The method includes the steps of: depositing a metal thin film (12) of copper (Cu) on a glass substrate (11) serving as a base; forming an insulating film or a metal insulating film (131) containing no Cu on the metal thin film (12); patterning a photoresist (14) by photolithography on the insulating film (131); etching a liner film (13) by isotropic dry etching using the photoresist (14) as an etching mask; and after the etching of the liner film (13), removing the photoresist (14), and then removing part of the metal thin film (12) by isotropic wet etching using the liner film (13) as an etching mask, thereby forming metal wiring (12a).Type: GrantFiled: February 17, 2011Date of Patent: February 11, 2014Assignee: Sharp Kabushiki KaishaInventor: Shinya Ohhira
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Patent number: 8642480Abstract: A plasma etching system having a substrate support assembly with multiple independently controllable heater zones. The plasma etching system is configured to control etching temperature of predetermined locations so that pre-etch and/or post-etch non-uniformity of critical device parameters can be compensated for.Type: GrantFiled: December 13, 2010Date of Patent: February 4, 2014Assignee: Lam Research CorporationInventors: Keith William Gaff, Harmeet Singh, Keith Comendant, Vahid Vahedi
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Patent number: 8633115Abstract: Provided are methods of etching a substrate using atomic layer deposition apparatus. Atomic layer deposition apparatus including a gas distribution plate with a thermal element are discussed. The thermal element is capable of locally changing the temperature of a portion of the surface of the substrate to vaporize an etch layer deposited on the substrate.Type: GrantFiled: November 30, 2011Date of Patent: January 21, 2014Assignee: Applied Materials, Inc.Inventors: Mei Chang, Joseph Yudovsky
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Publication number: 20140011339Abstract: Native oxides and residue are removed from surfaces of a substrate by performing a hydrogen remote plasma process on the substrate. In one embodiment, the method for removing native oxides from a substrate includes transferring a substrate containing native oxide disposed on a material layer into a processing chamber, wherein the material layer includes a Ge containing layer or a III-V compound containing layer, supplying a gas mixture including a hydrogen containing gas from a remote plasma source into the processing chamber, and activating the native oxide by the hydrogen containing gas to remove the oxide layer from the substrate.Type: ApplicationFiled: June 27, 2013Publication date: January 9, 2014Applicant: APPLIED MATERIALS, INC.Inventors: Bo ZHENG, Avgerinos V. GELATOS, Ahmed KHALED
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Publication number: 20130344701Abstract: Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.Type: ApplicationFiled: June 28, 2013Publication date: December 26, 2013Inventors: Wei LIU, Eiichi MATSUSUE, Meihua SHEN, Shashank C. DESHMUKH, Anh-Kiet Quang PHAN, David PALAGASHVILI, Michael D. WILLWERTH, Jong I. SHIN, Barrett FINCH, Yohei KAWASE
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Publication number: 20130337654Abstract: An electrode assembly for a plasma reaction chamber used in semiconductor substrate processing. The assembly includes an upper showerhead electrode which is mechanically attached to a backing plate by a series of spaced apart cam locks. A guard ring surrounds the backing plate and is movable to positions at which openings in the guard ring align with openings in the backing plate so that the cam locks can be rotated with a tool to release locking pins extending from the upper face of the electrode.Type: ApplicationFiled: March 11, 2013Publication date: December 19, 2013Applicant: LAM RESEARCH CORPORATIONInventors: Roger Patrick, Gregory R. Bettencourt, Michael C. Kellogg
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Publication number: 20130337655Abstract: Embodiments of the present invention provide a dual load lock chamber capable of processing a substrate. In one embodiment, the dual load lock chamber includes a chamber body defining a first chamber volume and a second chamber volume isolated from one another. Each of the lower and second chamber volumes is selectively connectable to two processing environments through two openings configured for substrate transferring. The dual load lock chamber also includes a heated substrate support assembly disposed in the second chamber volume. The heated substrate support assembly is configured to support and heat a substrate thereon. The dual load lock chamber also includes a remote plasma source connected to the second chamber volume for supplying a plasma to the second chamber volume.Type: ApplicationFiled: February 29, 2012Publication date: December 19, 2013Applicant: APPLIED MATERIALS, INC.Inventors: Jared Ahmad Lee, Martin Jeffrey Salinas, Paul B. Reuter, Imad Yousif, Aniruddha Pal
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Patent number: 8598040Abstract: A method for etching features in a plurality of silicon based bilayers forming a stack on a wafer in a plasma processing chamber is provided. A main etch gas is flowed into the plasma processing chamber. The main etch gas is formed into a plasma, while providing a first pressure. A wafer temperature of less than 20° C. is maintained. The pressure is ramped to a second pressure less than the first pressure as the plasma etches through a plurality of the plurality of silicon based bilayers. The flow of the main etch gas is stopped after a first plurality of the plurality of bilayers is etched.Type: GrantFiled: September 6, 2011Date of Patent: December 3, 2013Assignee: Lam Research CorporationInventors: Anne Le Gouil, Jeffrey R. Lindain, Yasushi Ishikawa, Yoko Yamaguchi-Adams
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Publication number: 20130316540Abstract: A method for removing oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A removing oxide process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.Type: ApplicationFiled: August 13, 2013Publication date: November 28, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yen-Chu Chen, Teng-Chun Tsai, Chien-Chung Huang, Keng-Jen Liu
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Patent number: 8591755Abstract: A time-dependent substrate temperature to be applied during a plasma process is determined. The time-dependent substrate temperature at any given time is determined based on control of a sticking coefficient of a plasma constituent at the given time. A time-dependent temperature differential between an upper plasma boundary and a substrate to be applied during the plasma process is also determined. The time-dependent temperature differential at any given time is determined based on control of a flux of the plasma constituent directed toward the substrate at the given time. The time-dependent substrate temperature and time-dependent temperature differential are stored in a digital format suitable for use by a temperature control device defined and connected to direct temperature control of the upper plasma boundary and the substrate. A system is also provided for implementing upper plasma boundary and substrate temperature control during the plasma process.Type: GrantFiled: September 15, 2010Date of Patent: November 26, 2013Assignee: Lam Research CorporationInventor: Rajinder Dhindsa
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Patent number: 8580693Abstract: Methods and systems for temperature enhanced chucking and dechucking of resistive substrates in a plasma processing apparatus are described herein. In certain embodiments, methods and systems incorporate modulating a glass carrier substrate temperature during a plasma etch process to chuck and dechuck the carrier at first temperatures elevated relative to second temperatures utilized during plasma etching. In embodiments, one or more of plasma heat, lamp heat, resistive heat, and fluid heat transfer are controlled to modulate the carrier substrate temperature between chucking temperatures and process temperatures with each run of the plasma etch process.Type: GrantFiled: April 5, 2011Date of Patent: November 12, 2013Assignee: Applied Materials, Inc.Inventors: Sergey G. Belostotskiy, Michael G. Chafin, Jingbao Liu, David Palagashvili
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Patent number: 8580689Abstract: The present invention provides a dry etching method capable of readily providing rounded top edge portions, called top rounds, at trenches and vias formed by removal of a dummy material. The method of the present invention is a dry etching method for forming trenches or vias by removing a dummy material with its periphery surrounded by an interlayer oxide film, which method includes the steps of etching the dummy material to a predetermined depth, performing isotropic etching after the dummy material etching, and removing remaining part of the dummy material after the isotropic etching.Type: GrantFiled: August 16, 2011Date of Patent: November 12, 2013Assignee: Hitachi High-Technologies CorporationInventors: Tomoyoshi Ichimaru, Kenichi Kuwabara, Go Saito
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Publication number: 20130295774Abstract: A plasma etching method performs a plasma etching on a substrate W by irradiating plasma containing charged particles and neutral particles to the substrate W. The method includes controlling a distribution of reaction amounts between the substrate W and the neutral particles in a surface of the substrate W by adjusting a temperature distribution in the surface of the substrate W supported by a support, and controlling a distribution of irradiation amounts of the charged particles in the surface of the substrate W by adjusting a gap between the substrate W supported by the support and an electrode provided so as to face the support.Type: ApplicationFiled: March 22, 2013Publication date: November 7, 2013Inventors: Akitaka Shimizu, Masanobu Honda
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Patent number: 8546267Abstract: A method of controlling wafer temperature in a plasma reactor by obtaining the next scheduled change in RF heat load on the workpiece, and using thermal modeling to estimate respective changes in wafer backside gas pressure and in coolant flow through a wafer support pedestal that would compensate for the next scheduled change in RF heat load, and making the respective changes in the backside gas pressure or in the coolant flow prior to the time of the next scheduled change.Type: GrantFiled: November 24, 2010Date of Patent: October 1, 2013Assignees: B/E Aerospace, Inc., Applied Materials, Inc.Inventors: Paul Lukas Brillhart, Richard Fovell, Douglas A. Buchberger, Jr., Douglas H. Burns, Kallol Bera, Daniel J. Hoffman, Kenneth W. Cowans, William W. Cowans, Glenn W. Zubillaga, Isaac Millan
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Patent number: 8529783Abstract: A method for preventing the formation of contaminating polymeric films on the backsides of semiconductor substrates includes providing an oxygen-impregnated focus ring and/or an oxygen-impregnated chuck that releases oxygen during etching operations. The method further provides delivering oxygen gas to the substrate by mixing oxygen in the cooling gas mixture, maintaining the focus ring at a temperature no greater than the substrate temperature during etching and cleaning the substrate using a two step plasma cleaning sequence that includes suspending the substrate above the chuck.Type: GrantFiled: March 30, 2010Date of Patent: September 10, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Ming Chen, Chun-Li Chou, Chao-Cheng Chen, Hun-Jan Tao
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Patent number: 8529729Abstract: An assembly comprises a component of a plasma process chamber, a thermal source and a polymer composite therebetween exhibiting a phase transition between a high-thermal conductivity phase and a low-thermal conductivity phase. The temperature-induced phase change polymer can be used to maintain the temperature of the component at a high or low temperature during multi-step plasma etching processes.Type: GrantFiled: June 7, 2010Date of Patent: September 10, 2013Assignee: Lam Research CorporationInventors: Tom Stevenson, Michael Dickens
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Patent number: 8501629Abstract: A method of etching silicon-containing material is described and includes a SiConi™ etch having a greater or lesser flow ratio of hydrogen compared to fluorine than that found in the prior art. Modifying the flow rate ratios in this way has been found to reduce roughness of the post-etch surface and to reduce the difference in etch-rate between densely and sparsely patterned areas. Alternative means of reducing post-etch surface roughness include pulsing the flows of the precursors and/or the plasma power, maintaining a relatively high substrate temperature and performing the SiConi™ in multiple steps. Each of these approaches, either alone or in combination, serve to reduce the roughness of the etched surface by limiting solid residue grain size.Type: GrantFiled: December 23, 2009Date of Patent: August 6, 2013Assignee: Applied Materials, Inc.Inventors: Jing Tang, Nitin Ingle, Dongqing Yang
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Patent number: 8501630Abstract: A method for selectively etching a substrate is described. The method includes preparing a substrate comprising a silicon nitride layer overlying a silicon-containing contact region, and patterning the silicon nitride layer to expose the silicon-containing contact region using a plasma etching process in a plasma etching system. The plasma etching process uses a process composition having as incipient ingredients a process gas containing C, H and F, and a non-oxygen-containing additive gas, wherein the non-oxygen-containing additive gas includes H, or C, or both H and C, and excludes a halogen atom.Type: GrantFiled: September 28, 2010Date of Patent: August 6, 2013Assignee: Tokyo Electron LimitedInventors: Andrew W. Metz, Hongyun Cottle
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Patent number: 8497213Abstract: The invention provides a method for subjecting laminated thin films disposed below a photoresist mask pattern to plasma processing, wherein the roughness on the side walls of the formed pattern is reduced, and the LER and LWR are reduced. When etching a material to be processed to form a gate electrode including thin films such as a gate insulating film 205, a conducting layer 204, a mask layer 203 and an antireflection film 202 laminated on a semiconductor substrate 206 and a photoresist mask pattern 201 disposed on the antireflection film, prior to etching the mask pattern 201, plasma is generated from nitrogen gas or a mixed gas including nitrogen gas and deposition gas to subject the mask pattern 201 to a plasma curing process so as to reduce the roughness on the surface and side walls of the mask pattern 201, and then the laminated thin films 202, 203 and 204 disposed below the mask pattern 201 are subjected to a plasma etching process.Type: GrantFiled: January 14, 2008Date of Patent: July 30, 2013Assignee: Hitachi High-Technologies CorporationInventors: Naoki Yasui, Seiichi Watanabe
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Patent number: 8492287Abstract: A silicon-containing film on a substrate is subjected to a plasma process using a process gas containing fluorine and carbon, and is thereafter subjected to plasma process using an ammonia gas, whereby ammonium silicofluoride having toxicity and hygroscopic property is adhered to the substrate. The harmful ammonium silicofluoride is removed by the inventive method. After conducting the plasma process using an ammonia gas, the substrate is heated to a temperature not lower than the decomposition temperature of the ammonium silicofluoride to decompose the ammonium silicofluoride in a process container in which the plasma process was conducted, or in a process container connected with the processing vessel which the plasma process was conducted therein and is isolated from a clean room atmosphere.Type: GrantFiled: May 2, 2011Date of Patent: July 23, 2013Assignee: Tokyo Electron LimitedInventor: Shigeru Tahara
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Patent number: RE44292Abstract: There are included steps of forming a silicon nitride layer on a silicon layer or a silicon oxide layer, loading the silicon layer or the silicon oxide layer and the silicon nitride layer in a dry etching atmosphere, and selectively etching the silicon nitride layer with respect to the silicon layer or the silicon oxide layer by flowing a fluorine gas consisting of any one of CH2F2, CH3F, or CHF3 and an inert gas to the dry etching atmosphere. Hence, in the etching process of the silicon nitride layer, the etching selectivity of the silicon nitride layer to Si or SiO2 can be enhanced and also etching anisotropy can be enhanced.Type: GrantFiled: April 23, 2004Date of Patent: June 11, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Tadashi Oshima