By Creating Electric Field (e.g., Plasma, Glow Discharge, Etc.) Patents (Class 438/710)
  • Patent number: 11854770
    Abstract: Embodiments of the present disclosure generally relate to inductively coupled plasma sources, plasma processing apparatus, and independent temperature control of plasma processing. In at least one embodiment, a method includes introducing a process gas into a gas injection channel and generating an inductively coupled plasma within the gas injection channel. The plasma includes at least one radical species selected from oxygen, nitrogen, hydrogen, NH and helium. The method includes delivering the plasma from the plasma source to a process chamber coupled therewith by flowing the plasma through a separation grid between the plasma source and a substrate. The method includes processing the substrate. Processing the substrate includes contacting the plasma including the at least one radical species with a first side of the substrate facing the separation grid and heating the substrate using a plurality of lamps located on a second side of the substrate opposite the separation grid.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: December 26, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Wei Liu, Vladimir Nagorny, Rene George
  • Patent number: 11769675
    Abstract: An apparatus is for plasma dicing a semiconductor substrate of the type forming part of a workpiece, the workpiece further including a carrier sheet on a frame member, where the carrier sheet carries the semiconductor substrate. The apparatus includes a chamber, a plasma production device configured to produce a plasma within the chamber suitable for dicing the semiconductor substrate, a workpiece support located in the chamber for supporting the workpiece through contact with the carrier sheet, and a frame cover element configured to, in use, contact the frame member thereby clamping the carrier sheet against an auxiliary element disposed in the chamber.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: September 26, 2023
    Inventors: Gautham Ragunathan, David Tossell, Oliver Ansell
  • Patent number: 11682560
    Abstract: Exemplary etching methods may include flowing a halogen-containing precursor into a substrate processing region of a semiconductor processing chamber. The halogen-containing precursor may be characterized by a gas density greater than or about 5 g/L. The methods may include contacting a substrate housed in the substrate processing region with the halogen-containing precursor. The substrate may define an exposed region of a hafnium-containing material. The methods may also include removing the hafnium-containing material.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: June 20, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Zhenjiang Cui, Hanshen Zhang, Daniella Holm
  • Patent number: 11605546
    Abstract: A substrate processing system includes a processing chamber. A pedestal is arranged in the processing chamber. An edge coupling ring is arranged adjacent to the pedestal and around a radially outer edge of the substrate. An actuator is configured to selectively move a first portion of the edge coupling ring relative to the substrate to alter an edge coupling profile of the edge coupling ring.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: March 14, 2023
    Assignee: Lam Research Corporation
    Inventors: Jon McChesney, Alex Paterson
  • Patent number: 11600492
    Abstract: Electrostatic chucks with reduced current leakage and methods of dicing semiconductor wafers are described. In an example, an etch apparatus includes a chamber, and a plasma source within or coupled to the chamber. An electrostatic chuck is within the chamber. The electrostatic chuck includes a conductive pedestal having a plurality of notches at a circumferential edge thereof. The electrostatic chuck also includes a plurality of lift pins corresponding to ones of the plurality of notches.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: March 7, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Sai Abhinand, Michael Sorensen, Karthik Elumalai, Dimantha Rajapaksa, Cheng Sun, James S. Papanu, Gaurav Mehta, Eng Sheng Peh, Sri Thirunavukarasu, Onkara Korasiddaramaiah
  • Patent number: 11600713
    Abstract: A method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material over the semiconductor fin and over the substrate, forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using multiple etching processes to form a dummy gate stack, wherein each etching process of the multiple etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Teng Liao, Chia-Cheng Tai, Tzu-Chan Weng, Yi-Wei Chiu, Chih Hsuan Cheng
  • Patent number: 11600647
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed within a substrate. The substrate has a front-side surface and a back-side surface. An absorption enhancement structure is disposed along the back-side surface of the substrate and overlies the photodetector. The absorption enhancement structure includes a plurality of protrusions that extend outwardly from the back-side surface of the substrate. Each protrusion comprises opposing curved sidewalls.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: March 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsun-Kai Tsao, Cheng-Hsien Chou, Jiech-Fun Lu
  • Patent number: 11462416
    Abstract: Provided is a plasma processing method for plasma etching an etching target film formed on a sample. The method includes a protective film forming step of selectively forming a protective film on an upper portion of a pattern formed on the sample and adjusting a width of the formed protective film such that a distribution of the width of the formed protective film in a surface of the sample becomes a desired distribution, and a step of plasma etching the etching target film after the protective film forming step.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: October 4, 2022
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Miyako Matsui, Kenichi Kuwahara, Tatehito Usui, Hiroyuki Kobayashi
  • Patent number: 11456183
    Abstract: Provided is a plasma processing method for selectively removing, after plasma etching using a mask having an amorphous carbon film containing boron, the amorphous carbon film using plasma from a silicon nitride film, a silicon oxide film or a tungsten film. The plasma processing method includes a removing step of removing the amorphous carbon film using plasma generated by mixed gas of O2 gas and CH3F gas, or CH2F2 gas.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: September 27, 2022
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Toru Ito, Masahito Mori, Tadamitsu Kanekiyo
  • Patent number: 11443923
    Abstract: The present disclosure provides an apparatus for fabricating a semiconductor structure, including a chuck, an edge ring surrounding the chuck, wherein the edge ring comprises a cavity, a focus ring adjacent to an edge of the chuck and over the edge ring, and a first actuator in the cavity of the edge ring and engaging with the focus ring.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Keith Kuang-Kuo Koai, Shih-Kuo Liu, Wen-Chih Wang, Hsin-Liang Chen
  • Patent number: 11424120
    Abstract: In certain embodiments, a method of processing a semiconductor substrate includes positioning a semiconductor substrate in a plasma chamber of a plasma tool. The semiconductor substrate includes a film stack that includes silicon layers and germanium-containing layers in an alternating stacked arrangement, with at least two silicon layers and at least two germanium-containing layers. The method includes exposing, in a first plasma step executed in the plasma chamber, the film stack to a first plasma. The first plasma is generated from first gases that include nitrogen gas, hydrogen gas, and fluorine gas. The method includes exposing, in a second plasma step executed in the plasma chamber, the film stack to a second plasma. The second plasma is generated from second gases comprising fluorine gas and oxygen gas. The second plasma selectively etches the silicon layers.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: August 23, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Pingshan Luan, Christopher Catano, Aelan Mosden
  • Patent number: 11417535
    Abstract: A technique protects a mask in plasma etching of a silicon-containing film. An etching method includes providing a substrate in a chamber included in a plasma processing apparatus. The substrate includes a silicon-containing film and a mask. The mask contains carbon. The etching method further includes etching the silicon-containing film with a chemical species in plasma generated from a process gas in the chamber. The process gas contains a halogen and phosphorus. The etching includes forming a carbon-phosphorus bond on a surface of the mask.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: August 16, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takahiro Yokoyama, Maju Tomura, Yoshihide Kihara, Satoshi Ohuchida
  • Patent number: 11404281
    Abstract: First and second silicon containing films can be etched selectively against each other with high efficiency. A method includes preparing a processing target object within a chamber; etching the first silicon containing film of the processing target object by generating plasma of a processing gas within the chamber in a state that a temperature of the processing target object is set to a first temperature; and etching the second silicon containing film of the processing target object by generating the plasma of the processing gas within the chamber in a state that the temperature of the processing target object is set to a second temperature higher than the first temperature.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: August 2, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Taku Gohira, Sho Tominaga
  • Patent number: 11372332
    Abstract: A patterned photo resist layer (for example an EUV photo resist layer), which may exhibit line width roughness (LWR) and line edge roughness (LER) or scum is treated with a plasma treatment before subsequent etching processes. The plasma treatment reduces LWR, LER, and/or photo resist scum. In one exemplary embodiment, the plasma treatment may include a plasma formed using a gas having a boron and halogen compound. In one embodiment, the gas compound may be a boron and chlorine compound, for example boron trichloride (BCl3) gas. In another embodiment, the gas compound may be a boron and fluorine compound, for example BxFy gases. The plasma treatment process may modify the photoresist surface to improve LWR, LER, and scum effects by removing roughness from the photo resist surface and removing photo resist residues which may case scumming.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: June 28, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Wan Jae Park, Akiteru Ko
  • Patent number: 11339053
    Abstract: An object of the present invention is to improve quality of a nitride crystal, and also improve performance and manufacturing yield of a semiconductor device manufactured using the crystal. Provided is a nitride crystal in which a composition formula is represented by InxAlyGa1-x-yN (satisfying 0?x?1, 0?y?1, 0?x+y?1), and the concentration of B in the crystal is less than 1×1015 at/cm3, and each of the concentrations of O and C in the crystal is less than 1×1015 at/cm3 in a region of 60% or more of a main surface.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: May 24, 2022
    Assignees: SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Hajime Fujikura, Taichiro Konno, Takehiro Yoshida
  • Patent number: 11335544
    Abstract: A plasma processing apparatus includes a balun having a first unbalanced terminal, a second unbalanced terminal, a first balanced terminal, and a second balanced terminal, a grounded vacuum container, a first electrode electrically connected to the first balanced terminal, and a second electrode electrically connected to the second balanced terminal. When Rp represents a resistance component between the first balanced terminal and the second balanced terminal when viewing a side of the first electrode and the second electrode from a side of the first balanced terminal and the second balanced terminal, and X represents an inductance between the first unbalanced terminal and the first balanced terminal, 1.5?X/Rp?5000 is satisfied.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 17, 2022
    Assignee: CANON ANELVA CORPORATION
    Inventors: Tadashi Inoue, Masaharu Tanabe, Kazunari Sekiya, Hiroshi Sasamoto, Tatsunori Sato, Nobuaki Tsuchiya
  • Patent number: 11264219
    Abstract: Provided are a radical monitoring apparatus capable of monitoring electrical diagnosis of a radical produced by direct plasma or remote plasma and the amount of change of the produced radical, and a plasma apparatus including the radical monitoring apparatus. The plasma apparatus includes a process chamber in which a plasma process is performed, a dielectric film in the process chamber and surrounding sides of a plasma discharge space in the process chamber, and a sensor inside the dielectric film and configured to monitor plasma to thereby monitor a radical generated in the plasma.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: March 1, 2022
    Inventors: Kwangtae Hwang, Jinyong Kim, Iksoo Kim, Geumbi Mun, Junwon Lee, Jiwoon Im
  • Patent number: 11264249
    Abstract: Apparatus, systems, and methods for conducting a hardmask (e.g., carbon containing hardmask) removal process on a workpiece are provided. In one example implementation, a process can include admitting a process gas into a plasma chamber, generating a plasma in the plasma chamber from the process gas using an inductively coupled plasma source, and exposing the carbon containing hardmask to the plasma to remove at least a portion of the carbon containing hardmask. The process gas can include a sulfur containing gas. The process gas does not include a halogen containing gas. The inductively coupled plasma source can be separated from the plasma chamber by a grounded electrostatic shield to reduce capacitive coupling between the inductively coupled plasma source and the plasma.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: March 1, 2022
    Assignees: Mattson Technology, Inc., Beijing E-Town Semiconductor Technology Co., Ltd.
    Inventors: Fen Dai, Tinghao Wang, Oliver D. Jan, Moo-Hyun Kim, Shawming Ma, Zhongming Liu
  • Patent number: 11195923
    Abstract: Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: December 7, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Gaurav Thareja, Xuebin Li, Abhishek Dube, Yi-Chiau Huang, Tushar Vidyadhar Mandrekar, Andy Lo, Patricia M. Liu, Sanjay Natarajan, Saurabh Chopra
  • Patent number: 11195698
    Abstract: In one embodiment, an RF impedance matching network utilizing at least one electronically variable capacitors (EVC) is disclosed. Each EVC includes discrete capacitors operably coupled in parallel, the discrete capacitors including fine capacitors and coarse capacitors. A control circuit determines a parameter related to the plasma chamber and, based on the parameter, determines which of the coarse capacitors and which of the fine capacitors to have switched in to cause an impedance match. The increase of the variable total capacitance of each EVC is achieved by switching in more of the coarse capacitors or more of the fine capacitors than are already switched in without switching out a coarse capacitor that is already switched in.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: December 7, 2021
    Inventors: Imran Ahmed Bhutta, Michael Gilliam Ulrich
  • Patent number: 11170979
    Abstract: A decrease of an etching rate of a substrate can be suppressed, and energy of ions irradiated to an inner wall of a chamber main body can be reduced. A plasma processing apparatus includes a DC power supply configured to generate a negative DC voltage to be applied to a lower electrode of a stage. In a plasma processing performed by using the plasma processing apparatus, a radio frequency power is supplied to generate plasma by exciting a gas within a chamber. Further, the negative DC voltage from the DC power supply is periodically applied to the lower electrode to attract ions in the plasma onto the substrate placed on the stage. A ratio occupied, within each of cycles, by a period during which the DC voltage is applied to the lower electrode is set to be equal to or less than 40%.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: November 9, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koichi Nagami, Kazunobu Fujiwara, Tatsuro Ohshita, Takashi Dokan, Koji Maruyama, Kazuya Nagaseki, Shinji Himori
  • Patent number: 11142829
    Abstract: According to one embodiment, a semiconductor manufacturing apparatus member includes a base and a particle-resistant layer. The base includes a main portion and an alumite layer. The main portion includes aluminum. The alumite layer is provided at a front surface of the main portion. The particle-resistant layer is provided on the alumite layer and includes a polycrystalline ceramic. An Al purity of the main portion is 99.00% or more.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: October 12, 2021
    Assignee: Toto Ltd.
    Inventors: Yasutaka Nitta, Takuma Wada
  • Patent number: 11104995
    Abstract: Disclosed is a substrate processing apparatus capable of improving the characteristic of a film formed on the surface of a wafer, using a single-wafer type substrate processing apparatus which heats and processes a wafer. The substrate processing apparatus may include: a processing vessel where a substrate is processed; a substrate supporter including: a first heater configured to heat the substrate to a first temperature; and a substrate placing surface where the substrate is placed; a heated gas supply system including a second heater configured to heat an inert gas, wherein the heated gas supply system is configured to supply a heated inert gas into the processing vessel; and a controller configured to control the first heater and the second heater such that a temperature of a front surface of the substrate and a temperature of a back surface of the substrate are in a predetermined range.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: August 31, 2021
    Assignee: Kokusai Electric Corporation
    Inventors: Takashi Yahata, Satoshi Takano, Kazuyuki Toyoda, Naofumi Ohashi, Tadashi Takasaki
  • Patent number: 11101111
    Abstract: A conventional substrate processing apparatus for generating plasma cannot generate plasma with high density and thus throughput of substrate processing is low. In order to solve this problem, provided is a substrate processing apparatus including a reaction vessel having a tubular shape and provided with a coil installed at an outer circumference thereof; a cover installed at a first end of the reaction vessel; a gas introduction port installed at the cover; a first plate installed between the gas introduction port and an upper end of the coil; a second plate installed between the first plate and the upper end of the coil; a substrate processing chamber installed at a second end of the reaction vessel; and a gas exhaust part connected to the substrate processing chamber.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: August 24, 2021
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Hidehiro Yanai, Shin Hiyama, Toru Kakuda, Toshiya Shimada, Tomihiro Amano
  • Patent number: 11094551
    Abstract: A plasma processing method performed using a plasma processing apparatus includes a first step of forming a first film on a pattern formed on a substrate and having dense and coarse areas, and a second step of performing sputtering or etching on the first film.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: August 17, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihide Kihara, Toru Hisamatsu, Kensuke Taniguchi, Yoshinari Hatazaki
  • Patent number: 11037798
    Abstract: Embodiments of the disclosure describe a cyclic etch method for carbon-based films. According to one embodiment, the method includes providing a substrate containing the carbon-based film, exposing the carbon-based film to an oxidizing plasma thereby forming an oxidized layer on the carbon-based film, thereafter, exposing the oxidized layer to a non-oxidizing inert gas plasma thereby removing the oxidized layer and forming a carbonized surface layer on the carbon-based film, and repeating the exposing steps at least once.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: June 15, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Barton G. Lane, Nasim Eibagi, Alok Ranjan, Peter L. G. Ventzek
  • Patent number: 11031245
    Abstract: Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: June 8, 2021
    Assignee: Lan Research Corporation
    Inventors: David Charles Smith, Richard Wise, Arpan Mahorowala, Patrick A. Van Cleemput, Bart J. van Schravendijk
  • Patent number: 11031419
    Abstract: Embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a base substrate and the array substrate includes a plurality of pixel units. In each of the plurality of pixel units, the array substrate includes a thin film transistor and a storage capacitor disposed above the base substrate, the storage capacitor includes a metal layer, an intermediate layer, and a reflective layer disposed in a stacked manner, the metal layer being adjacent to the base substrate. The array substrate further includes a common electrode layer disposed on a side of the storage capacitor facing away from the base substrate, the reflective layer is electrically connected to the common electrode layer, and the metal layer is electrically connected to an active layer of the thin film transistor.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: June 8, 2021
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jinjin Xue, Dawei Shi, Feng Li, Lei Yao, Wentao Wang, Haifeng Xu, Lu Yang, Lin Hou, Jinfeng Wang, Mei Li, Yezhou Fang
  • Patent number: 11011386
    Abstract: According to an exemplary embodiment, a method includes preparing a workpiece including a silicon film and a mask provided on the silicon film, etching the silicon film using the mask by plasma of a gas containing a first halogen atom, modifying a surface of the silicon film into an oxide layer by plasma of a gas containing an oxygen atom, a hydrogen atom, and a second halogen atom, the oxide layer including a first region extending along a side wall surface of the mask and a second region extending on the silicon film, etching the oxide layer to remove the second region while leaving the first region, and etching the silicon film using the mask and the oxide layer including the first region by plasma of a gas containing a third halogen atom.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: May 18, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Yusuke Shimizu, Masahiko Takahashi
  • Patent number: 11004689
    Abstract: Exemplary methods for selectively removing silicon (e.g. polysilicon) from a patterned substrate may include flowing a fluorine-containing precursor into a substrate processing chamber to form plasma effluents. The plasma effluents may remove silicon (e.g. polysilicon, amorphous silicon or single crystal silicon) at significantly higher etch rates compared to exposed silicon oxide, silicon nitride or other dielectrics on the substrate. The methods rely on the temperature of the substrate in combination with some conductivity of the surface to catalyze the etch reaction rather than relying on a gas phase source of energy such as a plasma.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: May 11, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Zihui Li, Rui Cheng, Anchuan Wang, Nitin K. Ingle, Abhijit Basu Mallick
  • Patent number: 10983721
    Abstract: An example processing device includes a memory including a discreet finite automata (DFA) buffer configured to store at least a portion of a DFA graph, the DFA graph comprising a plurality of nodes, each of the nodes having zero or more arcs each including a respective label and pointing to a respective subsequent node of the plurality of nodes, at least one of the plurality of nodes comprising a match node, wherein the at least portion of the DFA graph comprises one or more slots of a memory slice, the one or more slots comprising data representing one or more of the arcs for at least one node of the plurality of nodes, and a DFA engine implemented in circuitry, the DFA engine comprising one or more DFA threads implemented in circuitry and configured to evaluate a payload relative to the DFA graph.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: April 20, 2021
    Assignee: Fungible, Inc.
    Inventors: Yi-Hua Edward Yang, Rajan Goyal, Eric Scot Swartzendruber
  • Patent number: 10982322
    Abstract: Methods to improve front-side process uniformity by back-side metallization are disclosed. In some implementations, a metal layer is deposited on the back-side of a wafer prior to performing a plasma-based process on the front side of the wafer. Presence of the back-side metal layer reduces variations in, for example, thickness of a deposited and/or etched layer resulting from the plasma-based process.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 20, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventor: Kezia Cheng
  • Patent number: 10957572
    Abstract: A gasket for a substrate support assembly may have a top surface having a surface area and a plurality of zones that together define the surface area of the top surface. The plurality of zones may comprise at least a) a first zone comprising a first stack of gasket layers, the first zone having a first average thermal conductivity in a first direction, and b) a second zone comprising one or more gasket layers, the second zone having a second average thermal conductivity in the first direction.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: March 23, 2021
    Assignee: Applied Materials, Inc.
    Inventor: Vijay D. Parkhe
  • Patent number: 10923333
    Abstract: A substrate processing apparatus includes a first mounting unit, a second mounting unit and an adjusting unit. The first mounting unit is configured to mount thereon a target substrate to be processed that is a plasma processing target. The second mounting unit is disposed to surround the first mounting unit to mount thereon a focus ring. The adjusting unit is configured to adjust a height of a peripheral portion of the target substrate with respect to a height of a central portion of the target substrate in response to consumption of the focus ring.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: February 16, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Kenji Matsumoto
  • Patent number: 10872788
    Abstract: A method includes dispensing a liquid etchant onto a wafer, wherein the wafer is free from rotation during dispensing the liquid etchant; blowing the liquid etchant on the wafer using a gas flow, wherein a direction of the gas flow remains substantially constant during dispensing the liquid etchant; and turning the gas flow off after a target structure on the wafer is etched away by the liquid etchant.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hong-Ting Lu, Han-Wen Liao
  • Patent number: 10847358
    Abstract: The present invention provides a bulb (100, 110, 120, 130, 140, 140?) an excitation chamber (200, 210, 220, 230, 230?) a ferrite core (300, 310, 310?), a spool (400, 410); an assembly or subassembly of such components, and a lamp (100, 1100, 1200, 1300, 1400, 1500, 1600, 1600?, 1600?, 1700, 1800) for producing electromagnetic radiation, such as in the light spectrum, UV or IR.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: November 24, 2020
    Assignee: TESLO PTY LTD
    Inventor: Anthony Papallo
  • Patent number: 10811256
    Abstract: Methods for etching a carbon-containing feature are provided. The methods may include: providing a substrate having a carbon-containing feature formed thereon in a reaction space; supplying helium gas and an oxidizing to the reaction space; generating a plasma within the reaction space from a gas mixture comprising helium gas and the oxidizing gas; and anisotropically etching the carbon-containing feature utilizing the plasma to cause lateral etching of the carbon-containing feature.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: October 20, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Mitsuya Utsuno, Tomohiro Kubota, Dai Ishikawa
  • Patent number: 10796890
    Abstract: There is disclosed a plasma processing apparatus for processing a wafer put on a sample stage disposed in a processing chamber within a vacuum vessel by the use of a plasma generated in the processing chamber after mounting the wafer on the sample stage. The apparatus has heaters in areas of the interior of the sample stage which are divided radially and circumferentially. At least those of the heaters which are arranged in the areas located in the radially outer position include circumferentially arranged heater portions that are connected in series. The amounts of heat generated by these circumferentially arranged heater portions are adjusted.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: October 6, 2020
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Hironori Kusumoto, Yutaka Ohmoto, Kazunori Nakamoto, Koji Nagai
  • Patent number: 10790313
    Abstract: The present disclosure relates to an array substrate. The array substrate includes a substrate; an outer connection wiring formed on the substrate. The outer connection wiring includes an outer connection section and a wire changing section located on an inner side of the outer connection section. An inorganic film covers the outer connection wiring. The inorganic film is provided with a via hole configured to expose a part of the wire changing section, and a groove configured to expose the outer connection section. And a metal layer is formed on the inorganic film, the metal layer includes a plurality of metal wirings electrically connected to the wire changing section through the via hole.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: September 29, 2020
    Inventor: Yao Li
  • Patent number: 10790153
    Abstract: Embodiments described herein relate to apparatus and methods for performing electron beam etching process. In one embodiment, a method of etching a substrate includes delivering a process gas to a process volume of a process chamber, applying a RF power to an electrode formed from a high secondary electron emission coefficient material disposed in the process volume, generating a plasma comprising ions in the process volume, bombarding the electrode with the ions to cause the electrode to emit electrons and form an electron beam, applying a negative DC power to the electrode, accelerating electrons emitted from the bombarded electrode toward a substrate disposed in the process chamber, and etching the substrate with the accelerated ions.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 29, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Yue Guo, Yang Yang, Kartik Ramaswamy, Kenneth S. Collins, Steven Lane, Gonzalo Monroy, Lucy Zhiping Chen
  • Patent number: 10741452
    Abstract: Methods for forming semiconductor fins include forming a sacrificial semiconductor structure around a hardmask fin on an underlying semiconductor layer. A first etch is performed that partially etches away a portion of the hardmask fin and the sacrificial semiconductor structure with a first etch chemistry. A second etch is performed that etches away remaining material of the portion of the hardmask fin and partially etches remaining material of the sacrificial semiconductor structure with a second etch chemistry. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eric R. Miller, Stuart A. Sieg, Yann Mignot, Indira Seshadri, Christopher J. Waskiewicz
  • Patent number: 10734241
    Abstract: A semiconductor device includes a semiconductor body, and first and second electrodes provided on front and back surfaces of the semiconductor body, respectively. The semiconductor body includes a first semiconductor layer and a second semiconductor layer selectively provided between the first electrode and the first semiconductor layer. A method of manufacturing the semiconductor device includes forming a mask layer on a first insulating film provided on the front surface of the semiconductor body, the mask layer including an opening above the first semiconductor layer; selectively removing the first insulating film to expose the semiconductor body, the mask layer being entirely removed together with the first insulative film; and forming a second insulating film to contact the first insulating film and the semiconductor body. The first insulative film is selectively removed through the opening. The second insulating film is formed to be semi-insulative and contact the first semiconductor layer.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: August 4, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Tsuyoshi Fujita
  • Patent number: 10734205
    Abstract: In a cleaning method according to an exemplary embodiment, a plasma is formed from a cleaning gas in a chamber of a plasma processing apparatus. A focus ring is mounted on a substrate support in the chamber to extend around a central axis of the chamber. While the plasma is formed, a magnetic field distribution is formed in the chamber by an electromagnet. The magnetic field distribution has a maximum horizontal component in a location on the focus ring or a location outside the focus ring in a radial direction with respect to the central axis.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: August 4, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Mitsuhiro Iwano, Masanori Hosoya
  • Patent number: 10692945
    Abstract: A manufacturing method for an inkjet printing AMOLED display panel is disclosed. The method includes steps of: manufacturing a TFT backplane, and manufacturing an anode on the TFT backplane; manufacturing a spacer layer for isolating the anode from a pixel definition layer on the anode; manufacturing a pixel definition layer on the TFT backplane, and the pixel definition layer covers the spacer layer; patterning the pixel definition layer to form a notch on the pixel definition layer in order to expose the spacer layer; etching the spacer layer below the notch by an etching solution; and forming an ink layer on the anode by an inkjet printing method. The invention can improve the cleanliness of the anode surface in the AMOLED display panel, reduce the residue, and make the printed light-emitting layer easier to spread evenly, prevent the AMOLED display panel from displaying abnormality.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: June 23, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD
    Inventors: Kunpeng He, Xiaoxing Zhang
  • Patent number: 10679867
    Abstract: A capacitively-coupled plasma processing apparatus includes: at least one chamber body providing chambers separated from each other; upper electrodes respectively installed in upper spaces within the chambers; lower electrodes respectively installed in lower spaces within the chambers; a high frequency power supply; a transformer including a primary coil electrically connected to the high frequency power supply, and secondary coils each of which coils having a first end and a second end; first condensers respectively connected between each of the first ends of the secondary coils and the upper electrodes; and second condensers respectively connected between each of the second ends of the secondary coils and the lower electrodes. The primary coil extends around a central axis. The secondary coils are configured to be coaxially disposed with respect to the primary coil. A self-inductance of each of the secondary coils is smaller than that of the primary coil.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: June 9, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Yohei Yamazawa
  • Patent number: 10658190
    Abstract: Extreme ultraviolet (EUV) lithographic patterning methods are provided which implement directional deposition on the EUV resist mask to improve selectivity and critical dimension control during the patterning of features in multiple layers. A hard mask material is deposited on a substrate structure using directional deposition. The hard mask material forms a hard mask layer that covers patterning features of an EUV resist mask of the substrate structure. The hard mask material is etched selective to a layer underlying the EUV resist mask to remove portions of the hard mask material that were deposited on the underlying layer during the directional deposition without uncovering the patterning features of the EUV resist mask. At least one layer of the substrate structure is patterned based on the EUV resist mask and the hard mask layer.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yongan Xu, Ekmini Anuja De Silva, Su Chen Fan, Yann Mignot
  • Patent number: 10651077
    Abstract: An etching method of silicon-containing oxide film is provided. The etching method includes a first step of forming an etching pattern on the silicon-containing oxide film by etching the silicon-containing oxide film using a first plasma generated from a first gas supplied to the processing vessel, according to a pattern of a mask layered on the silicon-containing oxide film, and a second step of removing a reaction product adhering to vicinity of an opening of the etching pattern and to the mask using a second plasma generated from a second gas supplied to the processing vessel, by applying a first high frequency electric power for generating plasma and a second high frequency electric power for generating bias voltage.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: May 12, 2020
    Assignee: Tokyo Electron Limited
    Inventor: Hideki Mizuno
  • Patent number: 10636675
    Abstract: A method of removing a metal-containing layer (e.g., tungsten) from a substrate is provided. The method includes generating a first plasma in a process volume of a plasma chamber when a patterned device is disposed on a substrate support in the process volume. The patterned device includes a patterned region and an unpatterned region; a substrate; a tungsten-containing layer formed over the substrate; a supporting layer disposed between the tungsten-containing layer and the substrate. The patterned region includes exposed surfaces of the supporting layer and the unpatterned region does not include any exposed surfaces of the supporting layer. The method further includes depositing a first film over the patterned region of the tungsten-containing layer with the first plasma; and removing portions of the unpatterned region of the tungsten-containing layer with the first plasma without depositing the first film over the unpatterned region.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 28, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Akhil Mehrotra, Gene Lee, Abhijit Patil, Shan Jiang, Zohreh Hesabi
  • Patent number: 10615368
    Abstract: Embodiments described herein generally relate to a method and apparatus for encapsulating an OLED structure, more particularly, to a TFE structure for an OLED structure with desired profile control of the TFE structure. In one example, a method for forming a thin film encapsulation structure over an OLED structure includes forming a thin film encapsulation structure over an OLED structure disposed on a substrate, and performing a plasma treatment process to the thin film encapsulation structure by supplying a treatment gas mixture including a halogen containing gas to the thin film encapsulation structure.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: April 7, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jrjyan Jerry Chen, Soo Young Choi, Xiangxin Rui
  • Patent number: 10559467
    Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES COPORATION
    Inventors: John Christopher Arnold, Sean D. Burns, Yann Alain Marcel Mignot, Yongan Xu