Compound Semiconductor Patents (Class 438/718)
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Patent number: 5952245Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.Type: GrantFiled: September 25, 1996Date of Patent: September 14, 1999Assignee: Hitachi, Ltd.Inventors: Yoshimi Torii, Kazuo Nojiri, Yoshinao Kawasaki, Yoshiaki Sato, Ryooji Fukuyama, Hironobu Kawahara
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Patent number: 5942447Abstract: A wafer on which a GaAs layer is disposed on an Al.sub.x Ga.sub.1-x As (0<x.ltoreq.1) layer. An etching mask is formed on the GaAs layer. An etching gas containing chlorine, oxygen, and nitrogen is fed into a reaction chamber to generate a plasma having a plasma density of 10.sup.10 cm.sup.-3 or more, and the GaAs layer is etched using the Al.sub.x Ga.sub.1-x As layer of the wafer as an etching stop layer. This selective etching method is applied to formation of a gate recess structure in a compound semiconductor device.Type: GrantFiled: April 10, 1997Date of Patent: August 24, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Shinichi Miyakuni
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Patent number: 5897366Abstract: A method of resistless gate metal etch in the formation of a field effect transistor is disclosed, which includes providing a first layer of a first semiconductor material having a surface. A second layer of a second semiconductor material is formed on the surface and resistlessly patterned to define a masked and an unmasked portions. The unmasked portion of the second layer is etched away to the first layer to enable gate formation.Type: GrantFiled: March 10, 1997Date of Patent: April 27, 1999Assignee: Motorola, Inc.Inventors: Kumar Shiralagi, Saied N. Tehrani
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Patent number: 5888908Abstract: A method is provided for reducing the reflectivity of a metal layer prior to photolithography. A thin buffer layer, such as oxide, can be deposited over the metal layer. A short plasma etch is performed in order to roughen, but not completely remove, the thin oxide layer. This roughened layer significantly reduces the reflectivity of the underlying metal layer. As an alternative, the brief plasma etch can be applied directly to the metal layer, which results in a significant roughening of its upper surface. This also reduces the reflectivity of the metal layer.Type: GrantFiled: April 28, 1995Date of Patent: March 30, 1999Assignee: STMicroelectronics, Inc.Inventors: Gregory Joseph Stagaman, Michael Edward Haslam
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Patent number: 5888309Abstract: A method for forming within a microelectronics fabrication a via through a microelectronics layer formed of a material susceptible to sequential etching employing a fluorine containing plasma etch method followed by an oxygen containing plasma etch method. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a microelectronics layer formed of a material susceptible to sequential etching employing a fluorine containing plasma etch method followed by an oxygen containing plasma etch method. There is then formed upon the microelectronics layer a patterned photoresist layer. There is then etched through use of the fluorine containing plasma etch method while employing the patterned photoresist layer as a photoresist etch mask layer the microelectronics layer to form a patterned microelectronics layer having a via formed through the patterned microelectronics layer.Type: GrantFiled: December 29, 1997Date of Patent: March 30, 1999Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chen-Hua Yu
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Patent number: 5880032Abstract: A method of manufacturing a semiconductor device comprises the steps of introducing a first gas containing steam or alcohol into a processing vessel housing a semiconductor substrate, and introducing a hydrogen fluoride gas as a second gas into the processing vessel after stopping introduction of the first gas into the process chamber.Type: GrantFiled: July 30, 1996Date of Patent: March 9, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Kenji Doi, Ichiro Katakabe, Naoto Miyashita
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Patent number: 5872022Abstract: A method of etching a III-V compound semiconductor uses an etching gas including the group V element of the III-V compound semiconductor substrate layer while keeping the III-V compound semiconductor layer at a temperature higher than the crystal growth temperature of the III-V compound semiconductor. Etching using this method provides a higher degree of controllability than wet etching. In addition, because no etching solution is employed, the etching method can be employed in a crystal growth apparatus. Further, because an element of the III-V compound semiconductor layer is employed in the etching gas, incorporation of residual impurities can be prevented, keeping the etched surface clean.Type: GrantFiled: September 1, 1995Date of Patent: February 16, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takashi Motoda, Manabu Kato, Masayoshi Takemi
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Patent number: 5868854Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.Type: GrantFiled: December 8, 1992Date of Patent: February 9, 1999Assignee: Hitachi, Ltd.Inventors: Masayuki Kojima, Yoshimi Torii, Michimasa Hunabashi, Kazuyuki Suko, Takashi Yamada, Keizo Kuroiwa, Kazuo Nojiri, Yoshinao Kawasaki, Yoshiaki Sato, Ryooji Fukuyama, Hironobu Kawahara
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Patent number: 5840630Abstract: A focused ion beam is used to etch material from a specimen while directing a vapor of 1,2 di-iodo-ethane at the surface being etched. The etch rate is accelerated for surfaces of aluminum and gold relative to the etch rate without use of 1,2 di-iodo-ethane.Type: GrantFiled: December 20, 1996Date of Patent: November 24, 1998Assignee: Schlumberger Technologies Inc.Inventors: Michael A. Cecere, Theodore Ralph Lundquist
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Patent number: 5837617Abstract: A laminated layer having a layer containing Al (In) and a layer not containing Al (In) alternately laminated one upon another is plasma etched by an etchant gas which can etch both the layers containing and not containing Al (In). An additive gas containing F is added to the etchant gas while a layer not containing Al (In) is etched. When the surface of the layer containing Al (In) is exposed, fluorides are formed on the surface of the layer containing Al (In) and the etching is automatically stopped. An emission peak specific to Al (In) is monitored to detect which layer is presently etched.Type: GrantFiled: April 1, 1994Date of Patent: November 17, 1998Assignee: Fujitsu LimitedInventors: Hiroyuki Oguri, Teruo Yokoyama
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Patent number: 5834379Abstract: A process for synthesizing wide band gap materials, specifically, GaN, employs plasma-assisted and thermal nitridation with NH.sub.3 to convert GaAs to GaN. Thermal assisted nitridation with NH.sub.3 can be employed for forming layers of substantial thickness (on the order of 1 micron) of cubic and hexagonal GaN on a GaAs substrate. Plasma-assisted nitridation of NH.sub.3 results in formation of predominantly cubic GaN, a form particularly useful in optoelectronic devices. Preferably, very thin GaAs membranes are employed to permit formation thereon of GaN layers of any desired thickness without concern for critical thickness constraints. The thin membranes are preferably formed either with an epitaxial bonding technique, or by undercut etching.Type: GrantFiled: July 16, 1996Date of Patent: November 10, 1998Assignee: Cornell Research Foundation, Inc.Inventors: James R. Shealy, James R. Engstrom, Yu-Hwa Lo
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Patent number: 5824603Abstract: This is a device and method of forming such, wherein the device has an amorphous "TEFLON" (TFE AF) layer. The device comprising: a substrate; a TFE AF 44 layer on top of the substrate; and a semiconductor layer 42 on top of the TFE AF 44 layer. The device may be an electronic or optoelectronic device. The semiconductor layer may be a metal or other substance.Type: GrantFiled: June 7, 1995Date of Patent: October 20, 1998Assignee: Texas Instruments IncorporatedInventor: Chih-Chen Cho
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Patent number: 5795829Abstract: The high density plasma metal etch rate of a conductive material within a dense array of conductive lines is increased to no less than the etch rate of the conductive material in a bordering open field by injecting a sufficient amount of nitrogen into the total gas flow of the plasma. The injection of nitrogen in amounts of about 15% and 50% by volume of the total gas flow effectively reduces the etch rate differential between the dense array and open field, thereby reducing overetching, resist loss, and oxide loss in the open field, and facilitating planarization.Type: GrantFiled: June 3, 1996Date of Patent: August 18, 1998Assignee: Advanced Micro Devices, Inc.Inventor: Lewis Shen
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Patent number: 5783493Abstract: The present invention provides a method of manufacturing an interlevel dielectric layer (ILD) which has reduced precipitates after an etch back of the borophosphosilicate glass (BPSG) ILD layer. A dielectric layer containing boron and phosphorous is deposited on the substrate. A reflow process is performed on the dielectric layer at a temperature in a range of between about 800.degree. and 950.degree. C. The dielectric layer is etched back using a reactive ion etch. In an important step, a surface treatment is performed on the dielectric layer thorough a plasma treatment. A plasma source gas for the surface treatment is of a gas selected from the group consisting of Ar, NO.sub.2, N.sub.2, and O.sub.2, at a temperature in a range of between about 250.degree. and 400.degree. C. at a pressure in a range of between about 1 mtorr and 5 torr, at a RF power in a range of between about 300 and 400 watts, and for a time in a range of between about 15 and 80 seconds.Type: GrantFiled: January 27, 1997Date of Patent: July 21, 1998Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Rann Shyan Yeh, Chao-Hsin Chang, Hsien-Wen Chang
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Patent number: 5773366Abstract: A method for forming a tungsten wiring, wherein an etch barrier layer is formed on an area where a metal wiring will be formed, using chlorine-based plasma so that the etch barrier layer is used as a mask upon forming a metal wiring, thereby eliminating a limitation on the thickness of the tungsten junction layer. the method includes the steps of sequentially forming a tungsten junction layer and a tungsten film over a semiconductor substrate, forming a negative type photoresist film pattern using a metal wiring mask, forming a copper thin film on a selectively exposed portion of the tungsten film, growing the copper thin film in a chlorine-based plasma atmosphere, thereby forming a copper chloride thin film, removing the photoresist film pattern, sequentially etching the tungsten film and tungsten junction layer using the copper chloride thin film as a mask, and removing the copper chloride thin film, thereby forming a tungsten wiring.Type: GrantFiled: June 7, 1996Date of Patent: June 30, 1998Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Sung Bo Hwang
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Patent number: 5726102Abstract: A method for controlling the plasma etch bias of a patterned layer formed through plasma etching of a blanket layer formed beneath a patterned photoresist layer. There is first formed upon a semiconductor substrate a blanket layer. Formed upon the blanket layer is a patterned photoresist layer. The patterned photoresist layer is then treated through a pre-treatment method to form with a controlled degradation and a controlled flow a hardened patterned photoresist layer from the patterned photoresist layer. The hardened patterned photoresist layer is hardened against a further flow in a subsequent plasma etch method which is employed in etching the patterned layer from the blanket layer while employing the hardened patterned photoresist layer as an etch mask. Finally, the blanket layer is etched through the subsequent plasma etch method to form the patterned layer while employing the hardened patterned photoresist layer as the etch mask.Type: GrantFiled: June 10, 1996Date of Patent: March 10, 1998Assignee: Vanguard International Semiconductor CorporationInventor: Jui-Cheng Lo
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Patent number: 5624529Abstract: A dry etching method. According to the present invention, a gaseous plasma comprising, at least in part, boron trichloride, methane, and hydrogen may be used for dry etching of a compound semiconductor material containing layers including aluminum, or indium, or both. Material layers of a compound semiconductor alloy such as AlGaInP or the like may be anisotropically etched for forming electronic devices including field-effect transistors and heterojunction bipolar transistors and for forming photonic devices including vertical-cavity surface-emitting lasers, edge-emitting lasers, and reflectance modulators.Type: GrantFiled: May 10, 1995Date of Patent: April 29, 1997Assignee: Sandia CorporationInventors: Randy J. Shul, Christopher Constantine
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Patent number: 5616213Abstract: A method of etching Group III-V semiconductor materials wherein a plasma of methane, hydrogen and freon is provided in a reactive ion etching chamber having a semiconductor substrate therein and maintaining the substrate to be etched at an elevated temperature of about 100.degree. C. in vacuum conditions of from about 1 to about 100 milliTorr. The temperature range utilized herein is substantially higher than the temperatures used in prior art reactive ion etching of Group III-V compositions and provides substantially superior results as compared with tests of reactive ion etching using all materials and parameters used herein except that the temperature of the substrate being etched was about 34.degree. C. The amount of methane can be from a flow rate of about 5 zero to about 50 SCCM and preferably about 10 SCCM, the flow rate of hydrogen can be from about zero to about 40 SCCM and preferably about 30 SCCM and the flow rate of freon can be from about 5 to about 50 SCCM and preferably about 17 SCCM.Type: GrantFiled: June 7, 1995Date of Patent: April 1, 1997Assignee: Texas Instruments IncorporatedInventors: Timothy S. Henderson, Donald L. Plumton