Abstract: A method for fabricating a layer structure having a target topology profile in a step which has a side face and a lateral face, includes processes of: (a) depositing a dielectric layer on a preselected area of the substrate under first deposition conditions, wherein the dielectric layer has a portion whose resistance to fluorine and/or chlorine radicals under first dry-etching conditions is tuned; and (b) exposing the dielectric layer obtained in process (a) to the fluorine and/or chlorine radicals under the first dry-etching conditions, thereby removing at least a part of the portion of the dielectric layer, thereby forming a layer structure having the target topology profile on the substrate.

Abstract: A micromechanical sensor device and manufacturing method. The micromechanical sensor device is provided with a cap substrate, which has a first front side and a first back side, and which has a through-opening as a media entry region; and with a sensor substrate, which has a second front side and a second back side, and which has, on the second front side, a sensor region that is embedded in an island-like region suspended on the remaining sensor substrate. The island-like region is mechanically decoupled from the remaining sensor substrate by a lateral stress-relief trench and by a cavity situated in the sensor substrate, underneath the island-like region. The first back side is bonded to the second front side so that the through opening is situated above the sensor region. The sensor region is covered by a gel, which fills the through-opening and the stress-relief trench at least partially.

Abstract: Embodiments provide a way of treating source/drain recesses with a high heat treatment and an optional hydrogen plasma treatment. The high heat treatment smooths the surfaces inside the recesses and remove oxides and etching byproducts. The hydrogen plasma treatment enlarges the recesses vertically and horizontally and inhibits further oxidation of the surfaces in the recesses.

Abstract: In some embodiments of the present disclosure, a method of manufacturing a semiconductor structure includes the following operations. A substrate including a first atom and a second atom is provided. An etchant is dispatched from an ionizer. A compound is formed over the substrate by bonding the first atom with the etchant. A particle is released from an implanter. The compound is removed by bombarding the compound with the particle having an energy smaller than a bonding energy between the first atom and the second atom, wherein the particle is different from the etchant.

Abstract: Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.

Abstract: A semiconductor structure manufacturing method includes: providing a substrate; forming an initial trench in the substrate; forming a sacrificial layer, the sacrificial layer including a first portion and a second portion, the first portion filling the initial trench and the second portion covering an upper surface of the substrate and an upper surface of the first portion; forming a division groove in the second portion, to pattern the second portion into a sacrificial pattern, the sacrificial pattern being arranged corresponding to the first portion; forming a filling layer in the division groove, the filling layer filling the division groove; removing the sacrificial pattern and the first portion, to form a word line trench; and forming a buried gate word line in the word line trench.

Abstract: A measuring method includes placing a substrate on an electrostatic chuck disposed inside a chamber, attracting the substrate onto the electrostatic chuck, generating plasma inside the chamber, detecting an amount of light reflected at the substrate by light emission of the plasma, and calculating a natural frequency of the substrate based on the amount of light.

Abstract: The present disclosure relates to a fabricating procedure of a radio frequency device, in which a precursor wafer including active layers, SiGe layers, and a silicon handle substrate is firstly provided. Each active layer is formed from doped epitaxial silicon and underneath a corresponding SiGe layer. The silicon handle substrate is over each SiGe layer. Next, the silicon handle substrate is removed completely, and the SiGe layer is removed completely. An etch passivation film is then formed over each active layer. Herein, removing each SiGe layer and forming the etch passivation film over each active layer utilize a same reactive chemistry combination, which reacts differently to the SiGe layer and the active layer. The reactive chemistry combination is capable of producing a variable performance, which is an etching performance of the SiGe layer or a forming performance of the etch passivation film over the active layer.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

Abstract: Exemplary etching methods may include flowing a fluorine-containing precursor and a hydrogen-containing precursor into a remote plasma region of a semiconductor processing chamber. The hydrogen-containing precursor may be flowed at a flow rate of at least 2:1 relative to the flow rate of the fluorine-containing precursor. The methods may include forming a plasma of the fluorine-containing precursor and the hydrogen-containing precursor to produce plasma effluents. The methods may include flowing the plasma effluents into a substrate processing region housing a substrate. The substrate may include an exposed region of a tantalum or titanium material and an exposed region of a silicon-containing material or a metal. The methods may include contacting the substrate with the plasma effluents. The methods may include removing the tantalum or titanium material selectively to the silicon-containing material or the metal.

Abstract: Exemplary semiconductor processing systems may include an output manifold that defines at least one plasma outlet. The systems may include a gasbox disposed beneath the output manifold. The gasbox may include an inlet side facing the output manifold and an outlet side opposite the inlet side. The gasbox may include an inner wall that defines a central fluid lumen. The inner wall may taper outward from the inlet side to the outlet side. The systems may include an annular spacer disposed below the gasbox. An inner diameter of the annular spacer may be greater than a largest inner diameter of the central fluid lumen. The systems may include a faceplate disposed beneath the annular spacer. The faceplate may define a plurality of apertures extending through a thickness of the faceplate.

Abstract: A roll-to-roll surface cleaning treatment system may include an upper housing containing a first plasma generating device and a first transfer roller that faces a nozzle from which a plasma beam generated by the first plasma generating device is discharged and that winds and transfers a flexible substrate, the upper housing comprising a gas inlet, an entrance through which the flexible substrate is introduced, and an outlet through which the flexible substrate is discharged, and a lower housing connected to the entrance of the upper housing and containing a second plasma generating device and a second transfer roller that faces a nozzle from which a plasma beam generated by the second plasma generating device is discharged and that winds and transfers the flexible substrate, the lower housing comprising a gas outlet, and an inlet through which the flexible substrate is introduced.

Abstract: A method for preparing precise pattern of integrated circuits, which comprises the following steps: (S1) preparing a large pitch trench or circular through-hole structure with a hard mask in a first dielectric layer by lithography and etching; (S2) forming micro trench on the hard mask of the second dielectric layer at the bottom side wall of the trench or circular through-hole structure by plasma etching process; (S3) removing the first dielectric layer; (S4) opening the hard mask of the second dielectric layer at the micro trench formed on the hard mask of the second dielectric layer by plasma etching process; (S5) small pitch trench or circular through holes are prepared in the second dielectric layer.

Abstract: An etching method prepares a substrate having laminated films including a first film and a second film that are alternately laminated, and a mask on the laminated films, and etches the laminated films by plasma of a process gas including a carbon and fluorine-containing gas. The carbon and fluorine-containing gas includes an unsaturated bond of C, and a CF3 group.

Abstract: Techniques relate to forming a sorting device. A mesh is formed on top of a substrate. Metal assisted chemical etching is performed to remove substrate material of the substrate at locations of the mesh. Pillars are formed in the substrate by removal of the substrate material. The mesh is removed to leave the pillars in a nanopillar array. The pillars in the nanopillar array are designed with a spacing to sort particles of different sizes such that the particles at or above a predetermined dimension are sorted in a first direction and the particles below the predetermined dimension are sorted in a second direction.

Abstract: A target object processing method is provided for processing a target object using a plasma processing apparatus including a processing chamber, a mounting table which is disposed in the processing chamber and on which the target object is mounted, an outer peripheral member disposed around the mounting table, and a first voltage application device configured to apply a voltage to the outer peripheral member. The method comprises preparing the target object having an etching target film and a patterned mask formed on the etching target film, and processing the mask. The step of processing the mask includes supplying a first processing gas containing a first rare gas to the processing chamber, and a first plasma processing for processing the mask positioned at an outer peripheral portion of the target object using plasma of the first processing gas while applying a DC voltage to the outer peripheral member.

Abstract: A dielectric member that is attached to a lower surface of a stage is provided. The stage includes a base provided with a base channel through which a heat exchange medium passes. The dielectric member includes at least one first component including a passage that is connected to the base channel, and a second component surrounding the first component.

Abstract: A surround for protecting an acoustic device for sending and/or receiving acoustic signals positioned therein from impact as the surround is rolled along an interior surface of a fluid-containing pipeline, the surround comprising: a shell comprising an exterior segment configured to roll along the interior surface, the exterior segment defining at least one acoustic aperture configured to allow the passage of acoustic signals therethrough; and a lattice configured between the exterior segment and the acoustic device, the lattice comprising a plurality of unit cells, each unit cell defining an opening, wherein the plurality of unit cells are interconnected and define a plurality of openings, wherein the plurality of openings allow fluid to move between the interior of the surround and the exterior of the surround and enable the passage of the acoustic signals transmitted and/or received by the acoustic device such that the surround reduces the diminution of the quality and/or strength of the acoustic signals.

Abstract: Provided is a semiconductor device that can detect the cracking progress with high precision. A semiconductor device is formed using a semiconductor substrate, and includes an active region in which a semiconductor element is formed, and an edge termination region outside the active region. A crack detection structure is termed in the edge termination region of the semiconductor substrate. The crack detection structure includes: a trench formed in the semiconductor substrate and extending in a circumferential direction of the edge termination region; an inner-wall insulating film formed on an inner wall of the trench; an embedded electrode formed on the inner-wall insulating film and embedded into the trench; and a monitor electrode formed on the semiconductor substrate and connected to the embedded electrode.

Abstract: A method for etching silicon at cryogenic temperatures is provided. The method includes forming an inert layer from condensation of a noble gas at cryogenic temperatures on exposed surfaces such as the sidewalls of a feature to passivate the sidewalls prior to the etching process. The method further includes flowing a fluorine-containing precursor gas into the chamber to form a fluorine-containing layer on the inert layer. The method further includes exposing the fluorine-containing layer and the inert layer to an energy source to form a passivation layer on the exposed portions of the substrate and exposing the substrate to ions to etch the substrate.

Abstract: A cutting method includes: forming a reformed region in a workpiece; and after forming the reformed region in the workpiece, cutting the workpiece along an intended cut line. In the cutting the workpiece, a dry etching process is performed from a front surface toward a rear surface of the workpiece while the workpiece is fixed on a support member at least under its own weight or by suction, to form a groove from the front surface to reach the rear surface of the workpiece.

Abstract: An etching method of an exemplary embodiment involves providing a substrate in a chamber of a plasma treatment system. The substrate includes a silicon-containing film. The method further involves etching the silicon-containing film by a chemical species in plasma generated from a process gas in the chamber. The process gas contains a halogen gas component and phosphorous gas component.

Abstract: An etching method of an exemplary embodiment involves providing a substrate in a chamber of a plasma treatment system. The substrate includes a silicon-containing film. The method further involves etching the silicon-containing film by a chemical species in plasma generated from a process gas in the chamber. The process gas contains a halogen gas component and phosphorous gas component.

Abstract: Systems and methods for etching different features in a substantially equal manner are described. One of the methods includes applying a low frequency bias signal during a low TCP state and applying a high frequency bias signal during a high TCP state. The application of the low frequency bias signal during the low TCP state facilitates generation of hot neutrals, which are used to increase an etch rate of etching dense features compared to an etch rate for etching isolation features. The application of the high frequency bias signal during the high TCP state facilitates generation of ions to increase an etch rate of etching the isolation features compared to an etch rate of etching the dense features. After applying the low frequency bias signal during the low TCP state and the high frequency bias signal during the high TCP state, the isolation and dense features are etched similarly.

Abstract: Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.

Abstract: A method used in forming integrated circuitry comprises forming horizontally-spaced conductive vias above a substrate. Conducting material is formed directly above and directly against the conductive vias. The conducting material is patterned to form individual conductive lines that are individually directly above a plurality of the conductive vias that are spaced longitudinally-along the respective individual conductive line. The patterning forms the individual conductive lines to have longitudinally-alternating wider and narrower regions. The wider regions are directly above and directly against a top surface of individual of the conductive vias and are wider in a horizontal cross-section that is at the top surface than are the narrower regions in the horizontal cross-section. The narrower regions are longitudinally-between the wider regions. Other embodiments, including structure independent of method, are disclosed.

Abstract: An apparatus and methods for selectively etching a particular layer are disclosed. The apparatus and methods are directed towards maintaining the etch rate of the particular layer, while keeping intact a non-etched layer. The etching process may be accomplished by co-flowing a hydrogen precursor gas and a fluorine precursor gas into a remote plasma unit. A resulting gas mixture may then be flowed onto the substrate having a silicon oxide layer as an etch layer and a silicon nitride layer as a non-etched layer, for example. A reaction between the resulting gas mixture and the particular layer takes place, resulting in etching of the silicon oxide layer while maintaining the silicon nitride layer in the above example.

Abstract: Provided is a method of selectively etching a substrate comprising at least one cycle of: depositing a chemical precursor on a surface of the substrate to form a chemical precursor layer on the substrate, the substrate comprising a first portion and a second portion, wherein the first and the second portion are of a different composition; selectively removing the chemical precursor layer and at least a part of the first portion of the substrate; and repeating the cycle until the first portion of the substrate is substantially or completely removed, wherein deposition of the chemical precursor and selective removal of the chemical precursor layer and at least a part of the first portion of the substrate are performed under a plasma environment.

Abstract: A plasma processing apparatus is provided including a radio frequency power source; a direct current power source; a chamber enclosing a process volume; and a substrate support assembly disposed in the process volume. The substrate support assembly includes a substrate support having a substrate supporting surface; an electrode disposed in the substrate support; and an interconnect assembly coupling the radio frequency power source and the direct current power source with the electrode.

Abstract: A plasma ion source includes a plasma chamber body having at least one inlet for introducing a feed gas to an interior of the plasma chamber body. The plasma chamber body is electrically isolated from a vacuum chamber attached to the plasma chamber body. An inductive antenna in an interior of the plasma chamber body is configured to supply a source of electromagnetic energy as a function of an RF voltage supplied thereto. The plasma ion source includes an extraction grid disposed at an end of the plasma chamber body. A voltage difference between the extraction grid and plasma chamber body accelerates charged species in a plasma discharge to generate an output quasi-neutral plasma ion beam. A bias voltage applied to the plasma chamber body includes a portion of the RF voltage supplied to the antenna combined with a pulsed DC voltage.

Abstract: A method of processing a substrate is provided. The substrate includes an etching target region and a patterned region. The patterned region is provided on the etching target region. In the method, an organic film is formed on a surface of the substrate. Subsequently, the etching target region is etched by plasma generated from a processing gas. The organic film is formed in a state that the substrate is placed in a processing space within a chamber. When the organic film is formed, a first gas containing a first organic compound is supplied toward the substrate, and then, a second gas containing a second organic compound is supplied toward the substrate. An organic compound constituting the organic film is generated by polymerization of the first organic compound and the second organic compound.

Abstract: Provided herein are methods and related apparatus to smooth the edges of features patterned using extreme ultraviolet (EUV) lithography. In some embodiments, at least one cycle of depositing passivation layer that preferentially collects in crevices of a feature leaving protuberances exposed, and etching the feature to remove the exposed protuberances, thereby smoothing the feature, is performed. The passivation material may preferentially collect in the crevices due to a higher surface to volume ratio in the crevices than in the protuberances. In some embodiments, local critical dimension uniformity (LCDU), a measure of roughness in contact holes, is reduced. In some embodiments, at least one cycle of depositing a thin layer in a plurality of holes formed in photoresist, the holes having different CDs, wherein the thin layer preferentially deposits in the larger CD holes, and anisotropically removing the thin layer to remove it at the bottoms of the holes, is performed.

Abstract: A silicon oxide film or a silicon nitride film is selectively etched by using an etching gas composition including a hydrofluorocarbon that has an unsaturated bond in its molecule and is represented by CxHyFz, wherein x is an integer of from 3 to 5, and relationships y+z?2x and y?z are satisfied. Also, a silicon oxide film is etched with high selectivity relative to a silicon nitride film by controlling the ratio among the hydrofluorocarbon, oxygen, argon, etc., included in the hydrofluorocarbon-containing etching gas composition.

Abstract: Methods and systems for RF pulse reflection reduction are provided herein. In some embodiments, a method includes (a) receiving a process recipe for processing the substrate that includes a plurality of pulsed RF power waveforms from a plurality of RF generators during a first duty cycle, (b) dividing the first duty cycle into a plurality of equal time intervals, (c) for each RF generator, determining a frequency command set for all intervals and send the frequency command set to the RF generator, wherein the frequency command set includes a frequency set point for each of the intervals in the plurality of equal time intervals, and (d) providing a plurality of RF power waveforms from a plurality of RF generators to a process chamber during a first duty cycle according to the frequency command set sent to each RF generator.

Abstract: An ion beam etching device comprises: an ion source configured to generate ions; a grid on a side of the ion source, the grid configured to accelerate the generated ions to generate an ion beam; a process chamber configured to have an etching process using the ion beam performed therein; and a variable magnetic field application part adjacent to the process chamber, the variable magnetic field application part configured to apply a variable magnetic field.

Abstract: A substrate support in a substrate processing system includes an inner portion arranged to support a substrate, an edge ring surrounding the inner portion, and a controller. The controller, to selectively cause the edge ring to engage the substrate and tilt the substrate, controls at least one actuator to at least one of raise and lower the edge ring and raise and lower the inner portion of the substrate support. The controller determines an alignment of a measurement device in the substrate processing system based on a signal reflected from a surface of the substrate when the substrate is tilted.

Abstract: A manufacturing method for a Micro-Electro-Mechanical Systems (MEMS) structure includes implementing a surface modification process, to form a transformation layer on the surfaces of the MEMS structure; implementing an anti-stiction coating pre-clean process, to clean the transformation layer on the surfaces towards a particular direction; and implementing an anti-stiction coating process, to coat a monolayer on the surfaces of the MEMS structure.

Abstract: Systems and methods for adjusting power and frequency based on three or more states are described. One of the methods includes receiving a pulsed signal having multiple states. The pulsed signal is received by multiple radio frequency (RF) generators. When the pulsed signal having a first state is received, an RF signal having a pre-set power level is generated by a first RF generator and an RF signal having a pre-set power level is generated by a second RF generator. Moreover, when the pulsed signal having a second state is received, RF signals having pre-set power levels are generated by the first and second RF generators. Furthermore, when the pulsed signal having a third state is received, RF signals having pre-set power levels are generated by the first and second RF generators.

Abstract: A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the polysilicon layer to change its removal rate, thereby forming a doped layer, and removing the doped layer in the first region to expose the polysilicon layer in the first region and leaving at least a portion of the doped layer in the second region. The method also includes removing the exposed polysilicon layer in the first region at a first removal rate and the doped layer in the second region at a second removal rate, the polysilicon layer in the second region being exposed after the doped layer in the second region is removed, and removing the polysilicon layer in the first region and the second region at a third removal rate and a fourth removal rate, respectively.

Abstract: A method of etching exposed silicon on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with a hydrogen-containing precursor. The combination react with the patterned heterogeneous structures to remove an exposed silicon portion faster than a second exposed portion. The silicon selectivity results from the presence of an ion suppressor positioned between the remote plasma and the substrate processing region. The methods may be used to selectively remove silicon faster than silicon oxide, silicon nitride and a variety of metal-containing materials. The methods may be used to remove small etch amounts in a controlled manner and may result in an extremely smooth silicon surface.

Abstract: A method includes forming a polysilicon layer with an uneven upper surface over a first region and a second region of a substrate, doping a top portion of the polysilicon layer to change its removal rate, thereby forming a doped layer, and removing the doped layer in the first region to expose the polysilicon layer in the first region and leaving at least a portion of the doped layer in the second region. The method also includes removing the exposed polysilicon layer in the first region at a first removal rate and the doped layer in the second region at a second removal rate, the polysilicon layer in the second region being exposed after the doped layer in the second region is removed, and removing the polysilicon layer in the first region and the second region at a third removal rate and a fourth removal rate, respectively.

Abstract: Disclosed are sulfur-containing compounds for plasma etching channel holes, gate trenches, staircase contacts, capacitor holes, contact holes, etc., in Si-containing layers on a substrate and plasma etching methods of using the same. The plasma etching compounds may provide improved selectivity between the Si-containing layers and mask material, less damage to channel region, a straight vertical profile, and reduced bowing in pattern high aspect ratio structures.

Abstract: Techniques for producing stacked SiGe nanowires using a condensation process without parasitic Ge nanowires as an undesired by-product. In one aspect, a method of forming SiGe nanowires includes the steps of: forming a stack of alternating Si and SiGe layers on a wafer; patterning fins in the stack; selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape; burying the fins in an oxide material; and annealing the fins under conditions sufficient to diffuse Ge from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires. A FET device and method for formation thereof are also provided.

Abstract: Methods of selectively etching silicon relative to silicon germanium are described. The methods include a remote plasma etch using plasma effluents formed from a fluorine-containing precursor and a hydrogen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the silicon. The plasmas effluents react with exposed surfaces and selectively remove silicon while very slowly removing other exposed materials. The methods are useful for removing Si(1-X)GeX faster than Si(1-Y)GeY, for X<Y. In some embodiments, the silicon germanium etch selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region.

Abstract: Provided is a method of creating structure profiles on a substrate using faceting and passivation layers. A first plasma etch process performed generating a faceted sidewall and a desired inflection point; a second plasma etch process is performed using an oxygen, nitrogen, or combined oxygen and nitrogen plasma, generating a passivation layer; and a third plasma etch process using operating variables of an etch chemistry on the faceted sidewall and the passivation layer to induce differential etch rates to achieve a breakthrough on near-horizontal surfaces of the structure, wherein the third plasma etch used is configured to produce a target sidewall profile on the substrate down to the underlying stop layer. Selected two or more plasma etch variables are controlled in the performance of the first plasma etch process, the second plasma etch process, and/or the third plasma etch process in order to achieve target sidewall profile objectives.

Abstract: A method of etching exposed silicon on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with a hydrogen-containing precursor. The combination reacts with the patterned heterogeneous structures to remove an exposed silicon portion faster than a second exposed portion. The silicon selectivity results from the presence of an ion suppressor positioned between the remote plasma and the substrate processing region. The methods may be used to selectively remove silicon faster than silicon oxide, silicon nitride and a variety of metal-containing materials. The methods may be used to remove small etch amounts in a controlled manner and may result in an extremely smooth silicon surface.

Abstract: A method of forming a substrate opening includes forming a plurality of side-by-side openings in a substrate. At least some of immediately adjacent side-by-side openings are formed in the substrate to different depths relative one another. Walls that are laterally between the side-by-side openings are removed to form a larger opening having a non-vertical sidewall surface where the walls were removed in at least one straight-line vertical cross-section that passes through the sidewall surface orthogonally to the removed walls.

Abstract: Disclosed is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure comprises a first portion of a trench extending through the top semiconductor layer and through a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a second portion of the trench, having sloped sidewalls, extends into the handle wafer. The sloped sidewalls are amorphized by an implant, for example, Xenon or Argon, to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer.

Abstract: A semiconductor device with a very high aspect ratio contact has a deep trench in the substrate. A dielectric liner is formed on sidewalls and a bottom of the deep trench. A contact opening is formed through the dielectric liner at the bottom of the deep trench to expose the substrate, leaving the dielectric liner on the sidewalls. Electrically conductive material is formed in the deep trench to provide the very high aspect ratio contact to the substrate through the contact opening.

Abstract: Methods and apparatus for processing a substrate in a multi-frequency plasma processing chamber are disclosed. The base RF signal pulses between a high power level and a low power level. Each of the non-base RF generators, responsive to a control signal, proactively switches between a first predefined power level and a second predefined power level as the base RF signal pulses. Alternatively or additionally, each of the non-base RF generators, responsive to a control signal, proactively switches between a first predefined RF frequency and a second predefined RF frequency as the base RF signal pulses. Techniques are disclosed for ascertaining in advance of production time the first and second predefined power levels and/or the first and second predefined RF frequencies for the non-base RF signals.