Electrically Conductive Material (e.g., Metal, Conductive Oxide, Etc.) Patents (Class 438/720)
  • Patent number: 11842900
    Abstract: A disclosed etching method includes (a) etching a titanium nitride film with a first plasma, and (b) etching the titanium nitride film with a second plasma. The first plasma is generated from a first processing gas, and the second plasma is generated from a second processing gas. One of the first processing gas and the second processing gas contains a chlorine-containing gas and a fluorocarbon gas, and the other of the first processing gas and the second processing gas contains a chlorine-containing gas and does not contain a fluorocarbon gas. A repetition of a cycle including the operations (a) and (b) is performed. The repetition of the cycle is stopped in a state where the titanium nitride film is partially etched in a film thickness direction thereof.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: December 12, 2023
    Assignee: Tokyo Electron Limited
    Inventor: Ryuichi Asako
  • Patent number: 11798813
    Abstract: Exemplary etching methods may include flowing an oxygen-containing precursor into a processing region of a semiconductor processing chamber. The methods may include contacting a substrate housed in the processing region with the oxygen-containing precursor. The substrate may include an exposed region of ruthenium, and the contacting may produce ruthenium tetroxide. The methods may include vaporizing the ruthenium tetroxide from a surface of the exposed region of ruthenium. An amount of oxidized ruthenium may remain. The methods may include contacting the oxidized ruthenium with a hydrogen-containing precursor. The methods may include removing the oxidized ruthenium.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: October 24, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Baiwei Wang, Xiaolin C. Chen, Rohan Puligoru Reddy, Oliver Jan, Zhenjiang Cui, Anchuan Wang
  • Patent number: 11721542
    Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. A substrate comprising a surface structure with a metal bottom, dielectric sidewalls, and a field of dielectric is exposed to a dual plasma treatment in a processing chamber to remove chemical residual and/or impurities from the metal bottom, the dielectric sidewalls, and/or the field of the dielectric and/or repair surface defects in the dielectric sidewalls and/or the field of the dielectric. The dual plasma treatment comprises a direct plasma and a remote plasma.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: August 8, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Yi Xu, Yufei Hu, Kazuya Daito, Yu Lei, Dien-Yeh Wu, Jallepally Ravi
  • Patent number: 11651977
    Abstract: Methods for processing a workpiece are provided. Conducting a thermal treatment on a workpiece are provided. The workpiece contains at least one layer of metal. The method can include generating one or more species from a process gas. The process gas can include hydrogen or deuterium. The method can include filtering the one or more species to create a filtered mixture and exposing the workpiece to the filtered mixture. An oxidation process on a workpiece are provided. The method can be conducted at a process temperature of less than 350° C.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: May 16, 2023
    Assignees: BEIJING E-TOWN SEMICONDUCTOR TECHNOLOGY CO., LTD, MATTSON TECHNOLOGY, INC.
    Inventors: Shanyu Wang, Chun Yan
  • Patent number: 11651966
    Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a method for processing a substrate includes applying at least one of low frequency RF power or DC power to an upper electrode formed from a high secondary electron emission coefficient material disposed adjacent to a process volume; generating a plasma comprising ions in the process volume; bombarding the upper electrode with the ions to cause the upper electrode to emit electrons and form an electron beam; and applying a bias power comprising at least one of low frequency RF power or high frequency RF power to a lower electrode disposed in the process volume to accelerate electrons of the electron beam toward the lower electrode.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: May 16, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Kartik Ramaswamy, Yang Yang, Kenneth Collins, Steven Lane, Gonzalo Monroy, Yue Guo
  • Patent number: 11562973
    Abstract: A display panel, a manufacturing method thereof, and a display device are disclosed. The display panel includes: a base substrate, provided with a terminal and a terminal protection layer pattern; the terminal protection layer pattern includes a first shielding region and a first opening region, an orthographic projection of the first shielding region on the base substrate and an orthographic projection of the terminal on the base substrate have an overlapping region, the overlapping region is located at an edge of the orthographic projection of the terminal on the base substrate, and an orthographic projection of the first opening region on the base substrate is located in the orthographic projection of the terminal on the base substrate.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 24, 2023
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Dawei Wang
  • Patent number: 11527659
    Abstract: A semiconductor device includes channel region, first and second two-dimensional metallic contacts, a gate structure, and first and second metal contacts. The channel region includes a two-dimensional semiconductor material. The first two-dimensional metallic contact is disposed at a side of the channel region and includes a two-dimensional metallic material. The second two-dimensional metallic contact is disposed at an opposite side of the channel region and includes the two-dimensional metallic material. The gate structure is disposed on the channel region in between the first and second two-dimensional metallic contacts. The first metal contact is disposed at an opposite side of the first two-dimensional metallic contact with respect to the channel region. The second metal contact is disposed at an opposite side of the second two-dimensional metallic contact with respect to the channel region.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yang Li, Lain-Jong Li, Han Yeh, Wen-Hao Chang
  • Patent number: 11522084
    Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: December 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 11469111
    Abstract: A method for processing a substrate for processing a substrate includes: (a) providing a substrate having an etching region and a patterned region on the etching region; (b) forming an organic film on a surface of the substrate; and (c) etching the etching region using plasma generated from a processing gas through the patterned region. The step (b) includes (b1) supplying a first gas containing an organic compound to the substrate to form a precursor layer on the substrate, and (b2) supplying a second gas containing a modifying gas to the substrate and supplying energy to the precursor layer and/or the second gas to modify the precursor layer.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: October 11, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shinya Ishikawa, Toru Hisamatsu
  • Patent number: 11289341
    Abstract: A photo-free lithography process with low cost, high throughput, and high reliability is provided. A template mask is bonded to a production workpiece and comprises a plurality of openings defining a pattern. An etch is performed into the production workpiece, through the plurality of openings, to transfer the pattern of the template mask to the production workpiece. The template mask is de-bonded from the production workpiece. A system for performing the photo-free lithography process is also provided.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chue San Yoo
  • Patent number: 11183397
    Abstract: Systems and methods for etching titanium containing layers on a workpiece are provided. In one example, a method includes placing the workpiece on a workpiece support in a processing chamber. The workpiece includes a first layer and a second layer. The first layer is a titanium containing layer. The method includes admitting a process gas into the processing chamber. The process gas includes an ozone gas and a fluorine containing gas. The method includes exposing the first layer and the second layer on the workpiece to the process gas to at least partially etch the first layer at a greater etch rate relative to the second layer.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: November 23, 2021
    Assignees: Beijing E-Town Semiconductor Technology, Co., LTD, Mattson Technology, Inc.
    Inventors: Qi Zhang, Haichun Yang, Hua Chung, Ting Xie, Michael X. Yang
  • Patent number: 11088019
    Abstract: Tin oxide films are used to create air gaps during semiconductor substrate processing. Tin oxide films, disposed between exposed layers of other materials, such as SiO2 and SiN can be selectively etched using a plasma formed in an H2-containing process gas. The etching creates a recessed feature in place of the tin oxide between the surrounding materials. A third material, such as SiO2 is deposited over the resulting recessed feature without fully filling the recessed feature, forming an air gap. A method for selectively etching tin oxide in a presence of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, or SiCN, includes, in some embodiments, contacting the substrate with a plasma formed in a process gas comprising at least about 50% H2. Etching of tin oxide can be performed without using an external bias at the substrate and is preferably performed at a temperature of less than about 100° C.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: August 10, 2021
    Assignee: Lam Research Corporation
    Inventors: Patrick A. Van Cleemput, Seshasayee Varadarajan, Bart J. van Schravendijk
  • Patent number: 10998199
    Abstract: There is provided an etching method including: a first gas supply step of supplying a reducing gas to a workpiece having a metal film formed thereon to reduce a front surface of the metal film, the workpiece being accommodated in at least one processing chamber; and subsequently, a second gas supply step of supplying an oxidizing gas for oxidizing the metal film and an etching gas composed of a ?-diketone to etch the oxidized metal film.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: May 4, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Susumu Yamauchi, Jun Lin
  • Patent number: 10892228
    Abstract: Methods of manufacturing a conductive feature and a package are provided. One of the methods includes the following steps. A seed layer is formed. A conductive pattern is formed over the seed layer. The seed layer and the conductive pattern include a same material. A dry etch process is performed to partially remove the seed layer exposed by the conductive pattern, to form a seed layer pattern. A plasma treatment process is performed on the seed layer pattern and the conductive pattern thereon, wherein the step of partially removing the seed layer and the step of performing the plasma treatment process are in-situ processes.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: January 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Yun-Chen Hsieh
  • Patent number: 10672618
    Abstract: Embodiments of systems and methods for patterning features in tantalum nitride (TaN) are described. In an embodiment, a method may include receiving a substrate comprising a TaN layer. The method may also include etching the substrate to expose at least a portion of the TaN layer. Additionally, the method may include performing a passivation process to reduce lateral etching of the TaN layer. The method may further include etching the TaN layer to form a feature therein, wherein the passivation process is controlled to meet one or more target passivation objectives.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Vinh Luong, Isabel Cristina Chu, Ashim Dutta
  • Patent number: 10283319
    Abstract: Atomic layer etching (ALE) processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase non-metal halide reactant and a second vapor phase halide reactant. In some embodiments both the first and second reactants are chloride reactants. In some embodiments the first reactant is fluorinating gas and the second reactant is a chlorinating gas. In some embodiments a thermal ALE cycle is used in which the substrate is not contacted with a plasma reactant.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: May 7, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Tom E. Blomberg, Varun Sharma, Suvi Haukka, Marko Tuominen, Chiyu Zhu
  • Patent number: 10280519
    Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: May 7, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Tom E. Blomberg, Varun Sharma, Suvi Haukka, Marko Tuominen, Chiyu Zhu
  • Patent number: 10273584
    Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: April 30, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Tom E. Blomberg, Varun Sharma, Suvi Haukka, Marko Tuominen, Chiyu Zhu
  • Patent number: 10231333
    Abstract: Methods of making a copper interconnect plated through hole assembly are disclosed. Nano copper ink dispersed in an organic solvent is able to be filled in the plated through hole and forming the copper interconnect by sintering at a temperature below the melting of the copper.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: March 12, 2019
    Assignee: Flextronics AP, LLC.
    Inventors: Weifeng Liu, Zhen Feng, Anwar Mohammed, David Geiger, Murad Kurwa
  • Patent number: 10079176
    Abstract: A barrier seed tool is configured to clean trenches in a first chamber, line the trenches with a diffusion barrier layer, and form a copper seed layer over the diffusion barrier layer in a second chamber. The clean chamber is configured to reduce overhangs in the copper seed layer by producing a plasma comprising positively and negatively charged ions including halogen ions, filtering the plasma to selectively exclude positively charged ions, and bombarding with the filtered plasma. The tool and related method can be used to reduce overhangs and improve subsequent gap fill while avoiding excessive damage to the dielectric matrix.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: September 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Ya-Lien Lee
  • Patent number: 9960052
    Abstract: Embodiments of the present invention provide methods for patterning a metal layer, such as a copper layer, to form an interconnection structure in semiconductor devices. In one embodiment, a method of patterning a metal layer on a substrate includes (a) supplying an etching gas mixture comprising a hydro-carbon gas into a processing chamber having a substrate disposed therein, the substrate having a metal layer disposed thereon, (b) exposing the metal layer to an ashing gas mixture comprising a hydrogen containing gas to the substrate, and (c) repeatedly performing steps (a) and (b) until desired features are formed in the metal layer. During the patterning process, the substrate temperature may be controlled at greater than 50 degrees Celsius.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: May 1, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Sumit Agarwal, Ann Chien, Chiu-Pien Kuo, Mark Hoinkis, Bradley J. Howard
  • Patent number: 9837286
    Abstract: A method for selectively etching a tungsten layer on a substrate includes arranging a substrate including a tungsten layer on a substrate support. The substrate processing chamber includes an upper chamber region, an inductive coil arranged outside of the upper chamber region, a lower chamber region including the substrate support and a gas dispersion device arranged between the upper and lower chamber regions. The gas dispersion device includes a plurality of holes in fluid communication with the upper and lower chamber regions. The method further includes controlling pressure in the substrate processing chamber in a range from 0.4 Torr to 10 Torr; supplying an etch gas mixture including fluorine-based gas to the upper chamber region; striking inductively coupled plasma in the upper chamber region by supplying power to the inductive coil; and selectively etching the tungsten layer relative to at least one other film material of the substrate.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: December 5, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Dengliang Yang, Helen H. Zhu, George Matamis, Brad Jacobs, Joon Hong Park, Joydeep Guha
  • Patent number: 9659791
    Abstract: Methods are described for etching metal layers that are difficult to volatize, such as cobalt, nickel, and platinum to form an etched metal layer with reduced surface roughness. The methods include pretreating the metal layer with a local plasma formed from a hydrogen-containing precursor. The pretreated metal layer is then reacted with a halogen-containing precursor to form a halogenated metal layer having a halogenated etch product. A carbon-and-nitrogen-containing precursor reacts with the halogenated etch product to form a volatile etch product that can be removed in the gas phase from the etched surface of the metal layer. The surface roughness may be reduced by performing one or more plasma treatments on the etching metal layer after a plurality of etching sequences. Surface roughness is also reduced by controlling the temperature and length of time the metal layer is reacting with the etchant precursors.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: May 23, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, David Cui, Anchuan Wang, Nitin K. Ingle
  • Patent number: 9396992
    Abstract: A barrier seed tool is configured to clean trenches in a first chamber, line the trenches with a diffusion barrier layer, and form a copper seed layer over the diffusion barrier layer in a second chamber. The clean chamber is configured to reduce overhangs in the copper seed layer by producing a plasma comprising positively and negatively charged ions including halogen ions, filtering the plasma to selectively exclude positively charged ions, and bombarding with the filtered plasma. The tool and related method can be used to reduce overhangs and improve subsequent gap fill while avoiding excessive damage to the dielectric matrix.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: July 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Ya-Lien Lee
  • Patent number: 9359679
    Abstract: Embodiments of the present disclosure provide methods for etching a metal layer, such as a copper layer, to form an interconnection structure in semiconductor devices. In one example, a method of patterning a metal layer on a substrate includes supplying a first etching gas mixture comprising a hydro-carbon gas and a hydrogen containing gas into a processing chamber having a substrate disposed therein, the substrate having a metal layer disposed thereon, supplying a second gas mixture comprising the hydrogen containing gas to a surface of the etched metal layer disposed on the substrate, and supplying a third gas mixture comprising an inert gas into the processing chamber to sputter clean the surface of the etched metal layer.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: June 7, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Sumit Agarwal, Bradley J. Howard
  • Patent number: 9299582
    Abstract: Methods of selectively etching metal-containing materials from the surface of a substrate are described. The etch selectively removes metal-containing materials relative to silicon-containing films such as silicon, polysilicon, silicon oxide, silicon germanium and/or silicon nitride. The methods include exposing metal-containing materials to halogen containing species in a substrate processing region. A remote plasma is used to excite the halogen-containing precursor and a local plasma may be used in embodiments. Metal-containing materials on the substrate may be pretreated using moisture or another OH-containing precursor before exposing the resulting surface to remote plasma excited halogen effluents in embodiments.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: March 29, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Nitin K. Ingle, Jessica Sevanne Kachian, Lin Xu, Soonam Park, Xikun Wang, Jeffrey W. Anthis
  • Patent number: 9299575
    Abstract: Methods of evenly etching tungsten liners from high aspect ratio trenches are described. The methods include a remote plasma etch using plasma effluents formed from a fluorine-containing precursor and a high flow of helium. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with tungsten coating a patterned substrate having high aspect ratio trenches. The plasmas effluents react with exposed surfaces and evenly remove tungsten from outside the trenches and on the sidewalls of the trenches. The plasma effluents pass through an ion suppression element positioned between the remote plasma and the substrate processing region. Optionally, the methods may include concurrent ion bombardment of the patterned substrate to help remove potentially thicker horizontal tungsten regions, e.g., at the bottom of the trenches or between trenches.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: March 29, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Seung Park, Xikun Wang, Jie Liu, Anchuan Wang, Sang-jin Kim
  • Patent number: 9076641
    Abstract: Contacts for semiconductor devices and methods of making thereof are disclosed. A method comprises forming a first layer on a semiconductor, the first layer comprising one or more metals; forming a second layer on the first layer, the second layer comprising the one or more metals, nitrogen and oxygen; and heating the first and second layer such that oxygen migrates from the second layer into the first layer and the first layer comprises a sub-stoichiometric metal oxide after heating. Exemplary embodiments use transition metals such as Ti in the first layer. After heating there is a sub-stoichiometric oxide layer of about 2.5 nm thickness between a metal nitride conductor and the semiconductor. The specific contact resistivity is less than about 7×10?9 ?·cm2.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: July 7, 2015
    Assignee: Intermolecular, Inc.
    Inventor: Khaled Ahmed
  • Publication number: 20150140812
    Abstract: Embodiments of methods for etching cobalt metal using fluorine radicals are provided herein. In some embodiments, a method of etching a cobalt layer in a substrate processing chamber includes: forming a plasma from a process gas comprising a fluorine-containing gas; and exposing the cobalt layer to fluorine radicals from the plasma while maintaining the cobalt layer at a temperature of about 50 to about 500 degrees Celsius to etch the cobalt layer.
    Type: Application
    Filed: October 22, 2014
    Publication date: May 21, 2015
    Inventors: BHUSHAN N. ZOPE, AVGERINOS V. GELATOS
  • Publication number: 20150132970
    Abstract: An apparatus for processing reaction products that are deposited when an etching target film contained in a target object to be processed is etched is provided with: a processing chamber; a partition plate; a plasma source; a mounting table; a first processing gas supply unit; a second processing gas supply unit. The processing chamber defines a space, and the partition plate is arranged within the processing chamber and divides the space into a plasma generating space and a substrate processing space, while suppressing permeation of ions and vacuum ultraviolet rays. The plasma source generates a plasma in the plasma forming space. The mounting table is arranged in the substrate processing space to mount the target object thereon.
    Type: Application
    Filed: April 16, 2013
    Publication date: May 14, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Eiichi Nishimura, Akitaka Shimizu, Fumiko Yamashita, Daisuke Urayama
  • Publication number: 20150118859
    Abstract: A metal-containing deposit can be efficiently removed. A plasma processing method includes removing a deposit, which adheres to a member within a processing vessel and contains at least one of a transition metal and a base metal, by plasma of a processing gas containing a CxFy gas, in which x is an integer equal to or less than 2 and y is an integer equal to or less than 6, and without containing a chlorine-based gas and a nitrogen-based gas.
    Type: Application
    Filed: October 23, 2014
    Publication date: April 30, 2015
    Inventors: Masaru NISHINO, Takao FUNAKUBO, Shinichi KOZUKA, Ryosuke NIITSUMA, Tsutomu ITO
  • Publication number: 20150104951
    Abstract: Provided is a method of etching a copper layer. The method includes generating plasma of a processing gas within a processing container which accommodates an object to be processed that includes the copper layer and a metal mask formed on the copper layer. The metal mask contains titanium. In addition, the processing gas includes CH4 gas, oxygen gas, and a noble gas. In an exemplary embodiment, the metal mask may include a layer made of TiN.
    Type: Application
    Filed: October 13, 2014
    Publication date: April 16, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Eiichi NISHIMURA, Keiichi SHIMODA, Kei NAKAYAMA
  • Publication number: 20150099369
    Abstract: An apparatus configured to remove metal etch byproducts from the surface of substrates and from the interior of a substrate processing chamber. A plasma is used in combination with a solid state light source, such as an LED, to desorb metal etch byproducts. The desorbed byproducts may then be removed from the chamber.
    Type: Application
    Filed: May 29, 2014
    Publication date: April 9, 2015
    Applicant: Applied Materials, Inc.
    Inventors: Subhash Deshmukh, Joseph Johnson, Jingjing Liu, He Ren
  • Publication number: 20150093897
    Abstract: Semiconductor devices and methods of fabricating the same are provided. The methods include preparing a template having a three dimensional (3D) stair type structure formed in intaglio, forming an imprint pattern having the stair type structure using the template, and simultaneously forming stair type patterns on a substrate using the imprint pattern.
    Type: Application
    Filed: June 9, 2014
    Publication date: April 2, 2015
    Inventors: Cha-Won Koh, Hyun-Woo Kim, Jeon-ll Lee, Hyo-Sung Lee
  • Patent number: 8980763
    Abstract: Methods of selectively etching tungsten relative to silicon-containing films (e.g. silicon oxide, silicon carbon nitride and (poly)silicon) as well as tungsten oxide are described. The methods include a remote plasma etch formed from a fluorine-containing precursor and/or hydrogen (H2). Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the tungsten. The plasma effluents react with exposed surfaces and selectively remove tungsten while very slowly removing other exposed materials. Sequential and simultaneous methods are included to remove thin tungsten oxide which may, for example, result from exposure to the atmosphere.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 17, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, Ching-Mei Hsu, Nitin K. Ingle, Zihui Li, Anchuan Wang
  • Patent number: 8975191
    Abstract: There is provided a plasma etching method including a first process of etching an intermediate layer, which contains silicon and nitrogen and is positioned below a resist mask formed on a surface of a substrate, to cause a silicon layer positioned below the intermediate layer to be exposed through the resist mask and the intermediate layer, a second process of subsequently supplying a chlorine gas to the substrate to cause a reaction product to attach onto sidewalls of opening portions of the resist mask and the intermediate layer, and a third process of etching a portion of the silicon layer corresponding to the opening portion of the intermediate layer using a process gas containing sulfur and fluorine to form a recess in the silicon layer.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: March 10, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhito Tohnoe, Yusuke Hirayama, Yasuyoshi Ishiyama, Wataru Hashizume
  • Patent number: 8969213
    Abstract: A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chiahsun Tseng, David V. Horak, Chun-chen Yeh, Yunpeng Yin
  • Patent number: 8932959
    Abstract: Etching of a thin film stack including a lower thin film layer containing an advanced memory material is carried out in an inductively coupled plasma reactor having a dielectric RF window without exposing the lower thin film layer, and then the etch process is completed in a toroidal source plasma reactor.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: January 13, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas D. Nemani, Mang-mang Ling, Jeremiah T. Pender, Kartik Ramaswamy, Andrew Nguyen, Sergey G. Belostotskiy, Sumit Agarwal
  • Patent number: 8932406
    Abstract: The molecular etcher carbonyl fluoride (COF2) or any of its variants, are provided for, according to the present invention, to increase the efficiency of etching and/or cleaning and/or removal of materials such as the unwanted film and/or deposits on the chamber walls and other components in a process chamber or substrate (collectively referred to herein as “materials”). The methods of the present invention involve igniting and sustaining a plasma, whether it is a remote or in-situ plasma, by stepwise addition of additives, such as but not limited to, a saturated, unsaturated or partially unsaturated perfluorocarbon compound (PFC) having the general formula (CyFz) and/or an oxide of carbon (COx) to a nitrogen trifluoride (NF3) plasma into a chemical deposition chamber (CVD) chamber, thereby generating COF2. The NF3 may be excited in a plasma inside the CVD chamber or in a remote plasma region upstream from the CVD chamber.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 13, 2015
    Assignee: Matheson Tri-Gas, Inc.
    Inventors: Glenn Mitchell, Ramkumar Subramanian, Carrie L. Wyse, Robert Torres, Jr.
  • Patent number: 8921234
    Abstract: Methods of etching exposed titanium nitride with respect to other materials on patterned heterogeneous structures are described, and may include a remote plasma etch formed from a fluorine-containing precursor. Precursor combinations including plasma effluents from the remote plasma are flowed into a substrate processing region to etch the patterned structures with high titanium nitride selectivity under a variety of operating conditions. The methods may be used to remove titanium nitride at faster rates than a variety of metal, nitride, and oxide compounds.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: December 30, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jie Liu, Jingchun Zhang, Anchuan Wang, Nitin K. Ingle, Seung Park, Zhijun Chen, Ching-Mei Hsu
  • Patent number: 8894870
    Abstract: A system and method for etching a material, including a compound having a formulation of XYZ, wherein X and Y are one or more metals and Z is selected from one or more Group 13-16 elements, such as carbon, nitrogen, boron, silicon, sulfur, selenium, and tellurium, are disclosed. The method includes a first etch process to form one or more first volatile compounds and a metal-depleted layer and a second etch process to remove at least a portion of the metal-depleted layer.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: November 25, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Jereld Lee Winkler, Eric James Shero, Fred Alokozai
  • Patent number: 8877651
    Abstract: A method for manufacturing a semiconductor device includes forming a contact etch stop layer on an active area of a substrate that has a gate stack formed thereon. The gate stack includes a metal gate and a metal oxide. The contact etch stop layer includes a silicon oxide layer sandwiched between a first silicon nitride layer and a second silicon nitride layer that is disposed on the active area. The method further includes forming a contact hole extending through an interlayer dielectric layer on the first silicon nitride layer using the first silicon nitride layer as a protection for the active area, removing a portion of the first silicon nitride layer disposed at the bottom of the contact hole using the silicon oxide layer as a protection for the active area, and removing the metal oxide using the second silicon nitride layer as a protection for the active area.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: November 4, 2014
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Qiuhua Han, Xinpeng Wang, Yi Huang
  • Publication number: 20140264861
    Abstract: A method for fabricating one or more conductive lines in an integrated circuit includes providing a layer of copper containing conductive metal in a multi-layer structure fabricated upon a wafer, providing a first hard mask layer over the layer of copper containing conductive metal, performing a first sputter etch of first hard mask layer using a chlorine-based plasma or a sulfur fluoride-based plasma, and performing a second sputter etch of first hard mask layer using a second plasma, wherein a portion of the layer of copper containing conductive metal residing below a portion of the first hard mask layer that remains after the second sputter etch forms the one or more conductive lines. In one embodiment, the second plasma is a fluorocarbon-based plasma.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicants: Applied Materials, Incorporated, International Business Machines Corporation
    Inventors: MARK D. HOINKIS, Eric A. Joseph, Hiroyuki Miyazoe, Chun Yan
  • Publication number: 20140273492
    Abstract: Provided are methods for etching films comprising transition metals. Certain methods involve activating a substrate surface comprising at least one transition metal, wherein activation of the substrate surface comprises exposing the substrate surface to heat, a plasma, an oxidizing environment, or a halide transfer agent to provide an activated substrate surface; and exposing the activated substrate surface to a reagent comprising a Lewis base or pi acid to provide a vapor phase coordination complex comprising one or more atoms of the transition metal coordinated to one or more ligands from the reagent. Certain other methods provide selective etching from a multi-layer substrate comprising two or more of a layer of Co, a layer of Cu and a layer of Ni.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 18, 2014
    Inventors: Jeffrey W. Anthis, Benjamin Schmiege, David Thompson
  • Patent number: 8828248
    Abstract: Write heads may be formed by reactive ion etching (RIE) a dielectric mask and then reactive ion etching a polymeric underlayer. The first RIE affects the second RIE. The first portion of the first RIE process is performed with a ratio of CF4 to CHF3 between about 1.3 to 2, a gas flow ratio of CF4 to He between 2.2 and about 3, and a ratio of RF source power to RF bias power between about 10 and about 16. The second portion of the first RIE process is performed with a ratio of CF4 to CHF3 between about 0.3 to 0.8, a gas flow ratio of CF4 to He between about 1.2 and about 1.8, and a ratio of RF source power to RF bias between about 22 to 28. With the above parameters, the dielectric mask can be formed with minimized damage on the underlayer.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: September 9, 2014
    Assignee: HGST Netherlands B.V
    Inventors: Guomin Mao, Satyanarayana Myneni, Aron Pentek, Xiaoye Zhao
  • Patent number: 8809198
    Abstract: A method for selectively removing nano-crystals on an insulating layer. The method includes providing an insulating layer with nano-crystals thereon; exposing the nano-crystals to a high density plasma comprising a source of free radical chlorine, ionic chlorine, or both to modify the nano-crystals; and removing the modified nano-crystals with a wet etchant.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: August 19, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Ramakanth Alapati, Paul Morgan, Max Hineman
  • Patent number: 8790530
    Abstract: A method and manufacture for charge storage layer separation is provided. A layer, such as a polymer layer, is deposited on top of an ONO layer so that the polymer layer is planarized, or approximately planarized. The ONO includes at least a first region and a second region, where the first region is higher than the second region. For example, the first region may be the portion of the ONO that is over the source/drain region, and the second region may be the portion of the ONO that is over the shallow trench. Etching is performed on the polymer layer to expose the first region of the ONO layer, leaving the second region of the ONO unexposed. The etching continues to occur to etch the exposed ONO at the first region so that the ONO layer is etched away in the first region and the second region remains unexposed.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: July 29, 2014
    Assignee: Spansion LLC
    Inventors: Angela T. Hui, Gang Xue
  • Patent number: 8791001
    Abstract: The present disclosure provides a method for making a semiconductor device. The method includes forming a first material layer on substrate; forming a patterned photoresist layer on the first material layer; applying an etching process to the first material layer using the patterned photoresist layer as a mask; and applying a nitrogen-containing plasma to the substrate to remove the patterned photoresist layer.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: July 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Ryan Chia-Jen Chen, Yih-Ann Lin, Jr Jung Lin
  • Publication number: 20140206192
    Abstract: This present disclosure relates to an atomic layer etching method for graphene, including adsorbing reactive radicals onto a surface of the graphene and irradiating an energy source to the graphene on which the reactive radicals are adsorbed.
    Type: Application
    Filed: January 22, 2014
    Publication date: July 24, 2014
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Geun Young YEOM, Woong Sun LIM, Kyung Seok MIN, Yi Yeon KIM, Jong Sik OH
  • Patent number: 8785331
    Abstract: The present invention discloses a method for replacing chlorine atoms on a film layer. More particularly, sufficient replacement ions for replacing the chlorine atoms are formed in a plasma process by reducing a volume ratio of a gas in a gas mixture (i.e. the film layer may be etched with the ions formed by dissociation of the gas) and dissociation of the gas mixture further decreases the etching reaction to the film layer in a process for replacing the chlorine atoms. In comparison to a conventional process by pure oxygen, the present invention can improve the prior art re-etching problem to avoid affecting an electric property of a thin film transistor, also has an advantage of manufacturing time reduction for an increased production yield.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: July 22, 2014
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Yang-Ling Cheng