Abstract: A method for manufacturing an electrode of a capacitor used in a semiconductor device, wherein a support insulating layer, an etch stop layer including a tantalum oxide layer, and a mold sacrificial insulating layer are sequentially formed on a semiconductor substrate. The mold sacrificial insulating layer, the etch stop layer and the support insulating layer are sequentially patterned to form a three-dimensional mold for a storage node. A storage node layer is formed to cover the inner surface of the mold. Next, storage nodes for capacitors are formed by dividing the storage node layer. The residual mold sacrificial insulating layer is removed by selectively wet etching, using the tantalum oxide layer as an etch stopper.

Abstract: Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric layers. Such embodiments include forming metal-containing dielectric layers over a silicon-containing substrate where a metal-containing layer is first formed and that treated to form a dielectric layer. Dielectric layers formed by methods of the present invention have a dielectric constant greater than that of silicon dioxide, and can have an equivalent oxide thickness of less than 2 nanometers. Such dielectric layers are useful in the forming of a variety of semiconductor devices such as transistors, capacitors and the like where such devices and integrated circuits formed from such devices are encompassed by embodiments in accordance with the present invention.

Abstract: Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric layers. Such embodiments include forming metal-containing dielectric layers over a silicon-containing substrate where a metal-containing layer is first formed and that treated to form a dielectric layer. Dielectric layers formed by methods of the present invention have a dielectric constant greater than that of silicon dioxide, and can have an equivalent oxide thickness of less than 2 nanometers. Such dielectric layers are useful in the forming of a variety of semiconductor devices such as transistors, capacitors and the like where such devices and integrated circuits formed from such devices are encompassed by embodiments in accordance with the present invention.

Abstract: A method of manufacturing an image sensor, the method comprises the steps providing a substrate having a gate insulating layer abutting a portion of the substrate; depositing a silicon layer on the gate insulating layer; creating a plurality of openings in the deposited silicon layer for forming a plurality of etched deposited silicon; growing an oxide on first surfaces of the etched deposited silicon which first surfaces initially form a boundary for the openings; coating photoresist in the plurality of openings between the first surfaces of the oxidized silicon; and exposing the photoresist for removing the photoresist which overlies the silicon and retains a portion of the photoresist in the openings and on the first surface of the oxidized silicon.

Abstract: A method for fabricating a semiconductor device includes the following steps. At first, a Ru or RuO2 film and a SiO2 layer are formed over a Si substrate in that order. Then, a resist pattern is formed on the SiO2 layer and is then provided as a mask to etch the SiO2 layer to form a contact hole. The Ru or RuO2 film is exposed at the bottom of the contact hole. Subsequently, a plasma ashing is performed using an ashing gas prepared by mixing O2 with N2 where the composition ratio of N2 is 50% or more at a substrate temperature of 200° C. or more for ashing the resist pattern. Consequently, the present invention allows the ashing of the resist pattern over the Ru or RuO2 film at a high selectivity to prevent the Ru or RuO2 film from becoming disappeared.

Abstract: Described is a manufacturing method of an integrated circuit which uses a thin film such as platinum or BST as a hard mask upon patterning ruthenium or the like, thereby making it possible to form a device without removing the hard mask. In addition, the invention method makes it possible to interpose a protecting film such as platinum in order to prevent, upon removing a resist used for the patterning of the hard mask, an underlying ruthenium film or the like from being damaged.

Abstract: Fine etching of ruthenium or ruthenium oxide is suited for a ferroelectric and high dielectric film such as BST. Over a silicon oxide film 46 and a plug 49, a titanium nitride film 50, ruthenium film 51, ruthenium dioxide film 52 and silicon oxide film 53 are stacked successively. After patterning the silicon oxide film 53 with a resist film, the resist film is removed. In the presence of the patterned silicon oxide film 53, the ruthenium dioxide film 52 and ruthenium film 51 are etched under processing pressure of 15 mTorr, plasma source power of 500 W, RF bias power of 200 W, oxygen flow of 715 sccm, chlorine flow of 80 sccm, total flow of about 800 sccm, gas residence time of 49.3 msec, and over etching of 100%.

Abstract: A plasma etch reactor 20 includes a reactor chamber 22 with a grounded upper electrode 24, a lower electrode 28 which is attached to a high frequency power supply 30 and a low frequency power supply 32, and a peripheral electrode 26 which is located between the upper and lower electrode, and which is allowed to have a floating potential. Rare earth magnets 46, 47 are used to establish the magnetic field which confines the plasma developed within the reactor chamber 22. The plasma etch reactor 20 is capable of etching emerging films used with high density semiconductor devices.

Abstract: In a method of manufacturing a contact element, provision is made of a laminated body which has an insulating film, an electrically conductive layer stacked on the insulating film, and bump holes opened. A treatment is carried out so as to removen organic materials and the like from an interior of the bump holes and/or a surface of the insulating film before bumps are formed on the bump holes. The treatment may be a plasma treatment or an X-ray irradiation.

Abstract: As an electrically conductive layer or a lower layer of conductor layers to be patterned, a conductor layer which is dry-etchable with an oxygen-containing gas is provided. A dry etching process of the conductor layer with the oxygen-containing gas is performed highly selectively to a ground film.

Abstract: A method is disclosed to improve copper process integration in the forming copper interconnects in integrated circuits. This is accomplished by integrating the process of forming a copper seed layer in an interconnect structure such as a trench or a groove, with the process of plasma cleaning of the structure prior to the electroplating of copper into the trench. NH3 plasma can be used for this purpose. Or, H2/N2 thermal reduction can also be employed. The integrated process promotes well-controlled electro-chemical deposition (ECD) of copper for solid filling of the trench.

Abstract: A dry-etching method comprises the step of dry-etching a metal thin film as a chromium-containing film, wherein the method is characterized by using, as an etching gas, a mixed gas including (a) a reactive ion etching gas, which contains an oxygen-containing gas and a halogen-containing gas, and (b) a reducing gas added to the gas component (a), in the process for dry-etching the metal thin film. The dry-etching method permits the production of a photomask by forming patterns to be transferred to a wafer on a photomask blank. The photomask can in turn be used for manufacturing semiconductor circuits. The method permits the decrease of the dimensional difference due to the coexistence of coarse and dense patterns in a plane and the production of a high precision pattern-etched product.

Abstract: The present invention is a method for hydrogen-free plasma etching of indium tin oxide using a plasma generated from an etchant gas containing chlorine as a major constituent (i.e., chlorine comprises at least 20 atomic %, preferably at least 50 atomic %, of the etchant gas). Etching is performed at a substrate temperature of 100° C. or lower. The chlorine-comprising gas is preferably Cl2. The etchant gas may further comprise a non-reactive gas, which is used to provide ion bombardment of the surface being etched, and which is preferably argon. The present invention provides a clean, fast method for plasma etching indium tin oxide. The method of the invention is particularly useful for etching a semiconductor device film stack which includes at least one layer of a material that would be adversely affected by exposure to hydrogen, such as N- or P-doped silicon.

Abstract: A method for forming a metal silicide layer in a self-aligned manner on a source region and a drain region and a gate electrode of a semiconductor device formed on a semiconductor substrate, the method comprising the steps of: depositing a cobalt film over an entire surface of the semiconductor device formed on the semiconductor substrate, forming the metal silicide layer on the source region and drain region and the gate electrode by performing a heat treating thereof, and etching away an unreacted cobalt remaining on the semiconductor substrate using an admixture solution made of hydrochloric acid, hydrogen peroxide, and water, having relative concentration ratio ranging from 1:1:5 to 3:1:5, at a solution temperature of 25 to 45° C., with an etching time of 1 to 20 minutes.

Abstract: A method of removing an oxide layer from an article. The article is located in a reaction chamber. An interhalogen compound reactive with the oxide layer is introduced into the reaction chamber. The interhalogen compound forms volatile by-product gases upon reaction with the oxide layer. For compounds the form volatile chlorides, bromides or iodides, a reducing gas, such as for example hydrogen, ammonia, amines, phosphine, silanes; and higher silanes, may optionally be added simultaneously with the interhalogen to form a volatile by-product. Unreacted interhalogen compound and volatile by-product gases are removed from the reaction chamber. In one embodiment, the temperature in the reaction chamber may be elevated prior to or after introducing the interhalogen compound. In another embodiment, a metal layer is deposited in-situ on a portion of the article within the reaction chamber.

Abstract: A technique for forming a borderless transistor gate and source/drain region contact structure which provides an on-chip area efficient layout and connection between the device gate layer and an associated source/drain region that can also overlap adjoining isolation structures. In a representative embodiment, this may be effectuated through the overlapping of one portion of the contact region over the edge of the gate polysilicon layer and another part of the contact over the source/drain diffusion. The structure and process of the present invention provides a desirable size reduction in the contact for given design rule dimensions and the resultant contact structure is inherently “self-aligned” to both the gate polysilicon layer and the isolation region in that the contact has no need for an interstitial space between it and the gate polysilicon or isolation regions to prevent unintended electrical connections.

Abstract: There is provided a method of carrying out plasma-enhanced etching of a vanadium oxide film, including the steps of (a) depositing one of a resist film and an insulating film on a vanadium oxide film, (b) patterning the one of a resist film and an insulating film to thereby form a mask, and (c) carrying out plasma-enhanced etching of a vanadium oxide film through the use of an etching gas containing a fluoride gas at a volume ratio of 10% or greater, which fluoride having fluorine (F) atoms by six or greater. The method raises an etching ratio of a vanadium oxide film to an underlying insulating layer, resulting in that it is possible to prevent the underlying insulating layer from being etched together, when the vanadium oxide film is etched.

Abstract: Non-volatile and oxide residues that form during semiconductor processing are removed from the semiconductor structure in a two-stage process. An inert gas and a reducing gas are introduced to the reactor. In the first stage, the non-volatile contaminants are sputtered from the semiconductor structure by creating a plasma to ionize the inert gas. The power applied to the plasma is preferably high enough to give the ions of the inert gas a high degree of directionality as they approach the structure. The first stage is continued until the non-volatile contaminants have been sufficiently removed from the structure. In the second stage, the power is reduced and the reducing gas (e.g., hydrogen) reacts with the oxides (e.g., copper oxide) to form elemental metal and water vapor. During the second stage there is no appreciable sputtering, and therefore the damage to the structure is limited as compared with processes that use sputtering and reduction simultaneously.

Abstract: A hard Al oxide film having a high melting point, which grows on the surface of an Al—Cu film during a wafer is carried in atmospheric air, obstructs the burying of a viahole with the Al—Cu film by high pressure reflow, with a result that a void remains in the hole. The present invention is intended to remove such an Al oxide film grown on the Al—Cu film formed by sputtering, by Ar+ sputtering/etching directly before high pressure reflow. Moreover, when a Ti oxide film is present on the surface of a Ti based underlying film formed by CVD, an Al oxide film is possibly grown at the boundary between the Ti based underlying film and an Al—Cu film laminated thereon. In this case, the Ti oxide film is similarly removed directly before formation of the Al—Cu film, thereby preventing the growth of the Al oxide film.

Abstract: A method of forming a gate electrode in a semiconductor device which can effectively prevent abnormal oxidation of a metal layer without occurring thermal budget and the deterioration of a gate insulating layer during gate re-oxidation process, is disclosed. In the present invention, one selected from a group consisting of an iridium(Ir) layer, a ruthenium(Ru) layer and an osmium(Os) layer capable of forming a nonvolatile conductive metal oxide layer, is used as a metal layer of a gate electrode instead of a W layer in conventional art. Therefore, although a gate re-oxidation process is performed by a well known method, it is effectively prevented that the metal layer is abnormally oxidized, thereby forming an uniform oxide layer on the side wall of the gate. Furthermore, since the oxide layer is conductive, the resistivity of the gate electrode is reduced.

Abstract: A method for fabricating source/drain and gate of a TFT (thin film transistor) array is disclosed herein. After depositing multi-layer structures according to the present invention, an etching process is performed to define source/drain or gate of a TFT array and an excellent taper profile is easily obtained even though only the prior art etchant is used. The method for depositing multi-layer structures includes the following steps. Firstly, form a major conductive metallic layer on the substrate or on the previous layers depending on whether gate or source/drain bus is to be formed, then form a barrier layer on the metallic layer with dopant doped into the barrier layer. It is noted that the concentration of the dopant has a gradient distribution, and has a maximum value at the edge of the barrier layer adjacent to the metallic layer.

Abstract: Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.

Abstract: There is described a method of forming a semiconductor device in which a contact plug penetrates through an interlayer insulating film. The method is capable of formation of a multilayer wiring structure of small resistance. Contact holes are formed in an interlayer oxide film laid on a silicon substrate by etching, through use of a CF-based gas plasma. An organic layer deposited at the bottom of the contact holes is removed through cleaning etching through use of a plasma of a mixed gas consisting of CF4 and O2. After removal of the organic layer, a conductive contact plug is formed in each of the contact holes.

Abstract: Disclosed are methods and systems for etching dielectric layers in a high density plasma etcher. A method includes providing a wafer having a photoresist mask over a dielectric layer in order to define at least one contact via hole or open area that is electrically interconnected down to the silicon substrate of the wafer. The method then proceeds to inserting the wafer into the high density plasma etcher and pulsed application a TCP power source of the high density plasma etcher. The pulsed application includes ascertaining a desired etch performance characteristic, which includes photoresist selectivity and etch rate which is associated with a continuous wave application of the TCP source. Then, selecting a duty cycle of the pulsed application of the TCP source and scaling a peak power of the pulsed application of the TCP source in order to match a cycle-averaged power that would be delivered by the continuous wave application of the TCP source.

Abstract: A method for manufacturing an electrode of a capacitor used in a semiconductor device, wherein a support insulating layer, an etch stop layer including a tantalum oxide layer, and a mold sacrificial insulating layer are sequentially formed on a semiconductor substrate. The mold sacrificial insulating layer, the etch stop layer and the support insulating layer are sequentially patterned to form a three-dimensional mold for a storage node. A storage node layer is formed to cover the inner surface of the mold. Next, storage nodes for capacitors are formed by dividing the storage node layer. The residual mold sacrificial insulating layer is removed by selectively wet etching, using the tantalum oxide layer as an etch stopper.

Abstract: A plasma processing chamber includes a substrate holder and a member of silicon nitride such as a liner, focus ring or a gas distribution plate, the member having an exposed surface adjacent the substrate holder and the exposed surface being effective to minimize particle contamination during processing of substrates. The chamber can include an antenna which inductively couples RF energy through the gas distribution plate to energize process gas into a plasma state.

Abstract: Planarizing High Temperature Superconductor (HTS) surfaces, especially HTS thin film surfaces is crucial for HTS thin film device processing. Disclosed is a method of surface planarization for HTS film. The method includes first smoothing the HTS surface by Gas Cluster Ion Beam bombardment, followed by annealing in partial pressure of oxygen to regrow the damaged surface layer. A rough HTS surface can be planarized down to a smoothness with a standard deviation of one nanometer or better.

Abstract: A method for fabricating short channel field effect transistors with dual gates and with a gate dielectric having a high dielectric constant. The field effect transistor is initially fabricated to have a sacrificial gate dielectric and a dummy gate electrode. Any fabrication process, such as an activation anneal or a salicidation anneal of the source and drain of the field effect transistor, using relatively high temperature is performed with the field effect transistor having the sacrificial gate dielectric and the dummy gate electrode. The dummy gate electrode and the sacrificial gate dielectric are etched from the field effect transistor to form a gate opening. A layer of dielectric with high dielectric constant is deposited on the side wall and the bottom wall of the gate opening, and a crystallization enhancing layer is deposited on the bottom wall of the gate opening.

Abstract: A hydrogen barrier layer is formed above a ferroelectric thin film in an integrated circuit. The hydrogen barrier layer is directly over a protected segment of the ferroelectric thin film, while a sacrificial segment of the ferroelectric thin film extends laterally beyond the edges of the hydrogen barrier layer. The sacrificial segment absorbs hydrogen so that it cannot diffuse laterally into the protected segment of the ferroelectric thin film. After it absorbs hydrogen, the sacrificial segment is etched away to allow electrical connection to circuit layers below it. The ferroelectric thin film preferably comprises a layered superlattice compound. Excess bismuth or niobium added to the standard precursor solution of a strontium bismuth tantalum niobate compound helps to reduce hydrogen degradation of the ferroelectric properties.

Abstract: A fabricating method for a solar cell device (2) comprises the steps of: forming a transparent oxide electrode (12) on the surface of an insulating substrate (10); cleaning the surfaces of the insulating substrate (10) and the transparent oxide electrode (12) with a halogen gas having a saturated vapor pressure higher than that of etching gas in providing the transparent oxide electrode (12); and forming a laminated structure by laminating a surface treatment layer (14), a silicon nitride film (16), a p-type semiconductor layer (18), a buffer layer (20), an intrinsic semiconductor layer (22), an n-type semiconductor layer (24), and a metal electrode (26) in order. Through the above fabricating method, having the step of cleaning the surfaces of the insulating substrate (10) and the transparent oxide electrode (12), the surfaces are made clean to be high in transparency, thereby obtaining a required amount of transmitted light.

Abstract: A method and structure for etching a thin film perovskite layer (e.g., barium strontium titanate 836) overlying a second material without substantially etching the second material. The method comprises forming a substantially-silicon-free dielectric etchstop layer (e.g., aluminum nitride 858) on a second dielectric layer comprising silicon (e.g., silicon dioxide 818), depositing the perovskite layer over the etchstop layer, forming a mask layer (e.g., photoresist 842) over the perovsklte layer, patterning and removing portions of the mask layer to form a desired pattern, and etching portions of the perovskite layer not covered by the mask layer, whereby the etching stops on the etchstop layer. The structure comprises a substantially-silicon-free dielectric etchstop layer overlying a second dielectric layer comprising silicon, and a perovskite layer having a desired pattern and comprising an etched side overlying a substantially unetched portion of the etchstop layer.

Abstract: A method of etching a platinum group metal film uses a gas mixture containing argon (Ar), oxygen (O2) and halogen gases and a method of forming a lower electrode of a capacitor uses the etching method. The gas mixture contains O2, Ar, and a third component, preferably a halogen, e.g., chlorine (Cl2) or hydrogen bromide (HBr). In the method of forming a lower electrode, a conductive film containing a metal belonging to a platinum (Pt) group is formed on a semiconductor substrate, a hard mask partially exposing the conductive film is then formed on the conductive film. Then, the exposed conductive film is dry-etched using the hard mask as an etching mask and a three-component gas mixture containing argon (Ar) and oxygen (O2), to form a conductive film pattern beneath the hard mask, and the hard mask is then removed.

Abstract: A method is for cleaning via openings during manufacturing of integrated circuits. The method preferably comprises the steps of sputter cleaning the via opening at least once, and exposing the via opening to a reducing atmosphere at least once. The method may include alternatingly repeating the sputter cleaning and exposing steps. The step of sputter cleaning is preferably performed prior to the step of exposing, and a sputter cleaning may be performed after a last step of exposing the via opening to the reducing atmosphere. In one embodiment, the exposed metal portion comprises a metal compound, such as an oxide. Accordingly, the step of sputter cleaning removes at least a portion of the metal oxide, and the step of exposing comprises reducing at least a portion of the metal oxide. The invention is particularly applicable when the metal interconnection layer is a copper, as copper readily oxides at its exposed surface.

Abstract: A method of fabricating a local interconnect uses hydrogen plasma or hydrogen thermal treatment to form a local interconnect by transforming a part of the refractory metal oxide to a conductor. The local interconnect can be used to electrically connect two electrodes in a device, or to electrically connect same electrodes of different devices.

Abstract: A improved and new method for forming dual damascene etch back of copper lines and interconnects (studs) using a combination of oxidation of Cu and chemical/mass transport of the Cu oxide by the action of acid. The etch back solves the dishing problem in that it planarized the Cu. Etch back rates can be high at high temperatures. The surface of the substrate is kept clean and free of polishing scratches from CMP. The process produces better uniformity across the substrate and better electrical performance due the increased copper line cross-sectional area.

Abstract: A method and apparatus for using photoemission to determine the endpoint of a dry etch process. In one embodiment, the endpoint of a dry etch process is determined when the dry etch process is acting on a substrate comprising a layer of a first material overlying a second material. The substrate is illuminated with a beam of monochromatic light. The photon energy of the monochromatic light is greater than the work function of one of the two materials, and less than the work function of the other material. Thus the beam of light is capable of inducing photoemission of electrons in only one of the two materials: the material with a work function less than the photon energy of the beam of light. The electrons emitted by the photoemitting so material are collected. The current generated by the collected stream of electrons, the photocurrent, is amplified. A time-series of amplified photocurrent measurements is monitored for changes that correspond to the endpoint of the dry etch process.

Abstract: In one aspect, the invention includes a semiconductor processing method of forming a contact between two electrically conductive materials comprising: a) forming a first conductive material over a substrate, the first conductive material being capable of being oxidized in the presence of oxygen to an insulating material; b) sputter cleaning the first conductive material in the presence of oxygen in a gaseous phase and in the presence of an oxygen gettering agent; and c) forming a second conductive material in electrical contact with the first conductive material.

Abstract: A semiconductor device includes a semiconductor substrate, and a laminated film insulatively formed over the semiconductor substrate, wherein the laminated film includes a semiconductor film, a metal film of refractory metal formed on the semiconductor film, a conductive oxidation preventing film disposed between the metal film and the semiconductor film, for preventing oxidation of the semiconductor film in an interface between the metal film and the semiconductor film, and an oxide film formed on a side surface of the semiconductor film and formed to extend into upper and lower portions of the semiconductor film in a bird's beak form.

Abstract: A method of forming metal lines is disclosed. The method comprises the steps of: forming a composite metal layer over a wafer, the composite metal layer having a top layer of titanium/titanium nitride; oxidizing the top layer of titanium/titanium nitride to form a layer of titanium oxide; and patterning and etching the composite metal layer to form the metal lines.

Abstract: The present invention is a method related to the deposition of a metallization layer in a trench in a semiconductor substrate. The focus of the invention is to sequentially perform heated deposition and etch unit processes to provide a good conformal film of metal on the inner surfaces of a via or trench. The deposition and etch steps can also be performed simultaneously.

Abstract: A semiconductor processing method of forming a plurality of conductive lines includes, a) providing a substrate; b) providing a first conductive material layer over the substrate; c) providing a first insulating material layer over the first conductive layer; d) etching through the first insulating layer and the first conductive layer to the substrate to both form a plurality of first conductive lines from the first conductive layer and provide a plurality of grooves between the first lines, the first lines being capped by first insulating layer material, the first lines having respective sidewalls; e) electrically insulating the first line sidewalls; and f) after insulating the sidewalls, providing the grooves with a second conductive material to form a plurality of second lines within the grooves which alternate with the first lines. Integrated circuitry formed according to the method, and other methods, is also disclosed.

Abstract: A process for forming a semiconductor device using a conductive etch stop. The process includes the steps of fabricating a wafer structure up to a first level oxide deposition. A conductive etch stop is deposited over the first level oxide deposition, and selected portions of the conductive etch stop are removed. An inter-level oxide layer is deposited on the conductive etch stop, and selected portions of the inter-level oxide deposition are etched up to the conductive etch stop. The conductive etch stop may be either removed from the semiconductor or left as a conductor.

Abstract: Transistors may be fabricated by isolating a first region (16) of a semiconductor layer from a second region (18) of the semiconductor layer (12). A first disposable gate structure (26) of the first transistor may be formed over the first region (16) of the semiconductor layer (12). The first disposable gate structure (26) may comprise a replaceable material. A second disposable gate structure (28) of the second complementary transistor may be formed over the second region (18) of the semiconductor layer (12). A replacement layer (70) may be formed over the first disposable gate structure (26). The replacement layer (70) may comprise a replacement material. At least a portion of the replaceable material of the first disposable gate structure (26) may be substitutionally replaced with the replacement material of the replacement layer (70) to form a first gate structure (80).

Abstract: A damascene structure and method for forming such structure. In one embodiment, the damascene structure of the present invention includes a first layer of oxide which is a stochiometric oxide deposited onto a semiconductor substrate. A second layer of oxide which is a non-stochiometric oxide is then deposited onto the semiconductor substrate which is followed by a stochiometric oxide layer. The semiconductor substrate is then masked and etched so as to form vias using a selective etch process which etches the stochiometric oxide and stops etching on the non-stochiometric oxide layer. The etch chemistry is then changed in-situ, allowing the removal of the non-stochiometric oxide at the bottom of the via. The wafer is then re-masked in the pattern of trench interconnect using a selective etch process to selectively etch the layer of stochiometric oxide in the damascene trench down to the layer of non-stochiometric oxide while simultaneously completing the etching of vias.

Abstract: An etch method includes providing a material layer consisting essentially of a group member selected from the group consisting of an indium oxide (InO), a tin oxide (SnO), a mixture of indium and tin oxides, a compound of indium and of tin and of oxygen having the general formulation In.sub.x Sn.sub.y O.sub.z where z is substantially greater than zero but less than 100% and where the sum x+y fills the remainder of the 100%, and a mixture of the preceding ones of the group members. A reactive gas including a halogen-containing compound and an oxygen-containing compound is supplied to a vicinity of the material layer. Also, an electric field is supplied to react the supplied reactive gas with the material layer so as to form volatile byproducts of reactive gas and the material layer.

Abstract: A method of integrated circuit fabrication creating copper interconnect structures wherein the formation of copper oxide is reduced or eliminated by etching away the copper oxide performing an H.sub.2 plasma treatment in a plasma enhanced chemical vapor deposition chamber.

Abstract: A method fabricating salicide. A substrate having a polysilicon gate and a source/drain region is provided. A silicon oxide layer is formed on the polysilicon gate and the substrate. Using dry etch, a part of the silicon oxide layer is removed to leave a spacer with a waistline on a side wall of the polysilicon gate. A metal layer is formed on the polysilicon gate and the source/drain region.

Abstract: A thick plated interconnect (80) may be fabricated by forming a metal layer (20) above a semiconductor layer (12). A dielectric layer (22) may be formed on the metal layer (20). A via (24) may be formed in the dielectric layer (22) to expose the metal layer (20). A copper lead (50) may be formed electrically coupled to the metal layer (20) through the via (24) of the dielectric layer (22). A barrier member (88) may be formed on the copper lead (50). A bondable member (86) comprising aluminum may be formed on the barrier member (88).

Abstract: A method of fabricating a semiconductor device includes the step of removing native oxide on the surface of a metal silicide layer formed on a shallow impurity diffusion layer and exposed at the bottom portion of a contact hole by sputter etching under an incident ion condition of a high density and a low energy. In this sputter etching, the side surface of the contact hole is prevented from being sputtered and re-deposited on the bottom portion of the contact hole, whereby the native oxide is effectively removed while the impurity diffusion layer is prevented from being damaged. In addition, a substrate may be heated during sputter etching for preventing ion species such as Ar.sup.+ from being entrapped in the metal silicide layer.

Abstract: A method of forming low resistance contact structures in vias arranged between interconnect levels is provided. The method involves interconnect lines having an anti-reflective layer formed thereupon. An interlevel dielectric layer is formed over the interconnect lines. A photoresist layer is formed over the interlevel dielectric layer and patterned to define via locations. During via etch, an organic (carbon-based) polymer layer forms upon the anti-reflective-coated interconnect lines at the bottoms of the vias. The photoresist and the etch byproduct polymer layers are then removed using a dry etch process which employs a forming gas comprising nitrogen and hydrogen. A native oxide layer subsequently forms upon the anti-reflective-coated interconnect lines when exposed to oxygen. The native oxide layer is then removed, along with any residual etch byproduct polymer, during a sputter etch procedure.