Abstract: Provided is a conductive film comprising a substrate and a conductive part comprising at least a fine wire pattern formed on a first side of the substrate, wherein surface free energy SFE1 on the first side is larger than surface free energy SFE2 on a second side of the substrate opposite to the first side.

Abstract: To dry a substrate formed with a pattern on a front surface satisfactorily and with excellent drying performance, a substrate processing method comprises: a liquid film formation step of forming a liquid film of a processing liquid, in which cyclohexanone oxime is dissolved in a solvent, on a front surface of a substrate formed with a pattern by supplying the processing liquid to the front surface of the substrate; a solidified film formation step of forming a solidified film of the cyclohexanone oxime by solidifying the liquid film of the processing liquid; and a sublimation step of removing the solidified film from the front surface of the substrate by sublimating the solidified film.

Abstract: A manufacturing method of a metal structure is disclosed, which includes the following steps: forming a seed layer on a substrate; forming a patterned metal layer on the seed layer, wherein the patterned metal layer includes a metal member; forming a first patterned photoresist layer on the seed layer, wherein a thickness of the first patterned photoresist layer is less than a thickness of the patterned metal layer; and performing a first patterning process to the seed layer through the first patterned photoresist layer to form a patterned seed layer, wherein after the first patterning process, the metal member includes a first part and a second part, the first part is disposed between the patterned seed layer and the second part, and a width of the first part is greater than a width of the second part.

Abstract: A plasma processing apparatus includes a plasma chamber that accommodates a substrate having a film including a side wall surface and a bottom surface that define an opening; and a controller that controls a process on the substrate in the plasma chamber. The controller includes a sequencer that performs a sequence including forming a precursor layer on the opening of the film; and generating a plasma to form a protective film on the side wall surface of the opening of the film from the precursor layer and to etch the bottom surface of the opening of the film. The controller simultaneously forms the protective film on the side wall surface of the opening of the film and etches the bottom surface of the opening of the film.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a resist structure over a substrate. The resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer. The hydrogen plasma treatment is configured to smooth sidewalls of the trench without etching the ARC layer. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.

Abstract: To dry a substrate formed with a pattern on a front surface satisfactorily and with excellent drying performance, a substrate processing method comprises: a liquid film formation step of forming a liquid film of a processing liquid, in which cyclohexanone oxime is dissolved in a solvent, on a front surface of a substrate formed with a pattern by supplying the processing liquid to the front surface of the substrate; a solidified film formation step of forming a solidified film of the cyclohexanone oxime by solidifying the liquid film of the processing liquid; and a sublimation step of removing the solidified film from the front surface of the substrate by sublimating the solidified film.

Abstract: The present disclosure relates to an apparatus and method that manipulates the voltage at an edge ring relative to a substrate located on a substrate support located within a processing chamber. The apparatus includes a substrate support assembly that has a body having a substrate electrode embedded therein for applying a voltage to a substrate. The body of the substrate support assembly additionally has an edge ring electrode embedded therein for applying a voltage to an edge ring. The apparatus further includes an edge ring voltage control circuit coupled to the edge ring electrode. A substrate voltage control circuit is coupled to the substrate electrode. The edge ring voltage control circuit and the substrate voltage control circuit are independently tunable to generate a difference in voltage between the edge ring voltage and the substrate voltage.

Abstract: Methods, apparatuses, and systems related to a semiconductor nitridation passivation are described. An example method includes performing a dry etch process on a semiconductor structure on a wafer in a semiconductor fabrication process. The method further includes performing a dry strip process on the semiconductor structure. The method further includes performing a first wet strip clean process on the semiconductor. The method further includes performing a second wet strip clean process on the semiconductor. The method further includes performing a nitridation passivation on the semiconductor structure to avoid oxidization of the semiconductor structure. The method further performing a spacer material deposition on the semiconductor structure.

Abstract: Embodiments of the present disclosure provide wet process based methods for modifying threshold value (Vt) of high-k metal gate using self-assembled monolayer (SAM) on dedicated transistor. In one embodiment, the method includes forming a gate structure over a substrate, the gate structure comprising a gate dielectric layer, a barrier layer formed over the gate dielectric layer, and an oxide layer formed over the barrier layer, and forming a self-assembled monolayer on the oxide layer by exposing the oxide layer to an aqueous solution containing metal oxides in a metal dissolving acid.

Abstract: To provide a layer such as a charge transport layer having a refractive index significantly lowered without impairing electrical conductivity and surface roughness, and a method for producing it. A deposited film composition obtained by co-depositing a fluorinated polymer having a saturated vapor pressure at 300° C. of at least 0.001 Pa and an organic semiconductor material.

Abstract: The present disclosure relates to a semiconductor processing apparatus. The processing chamber includes a chamber body and lid defining an interior volume, a substrate support disposed in the interior volume and a showerhead assembly disposed between the lid and the substrate support. The showerhead assembly includes a faceplate configured to deliver a process gas to a processing region defined between the showerhead assembly and the substrate support and an underplate positioned above the faceplate, defining a first plenum between the lid and the underplate, the having multiple zones, wherein each zone has a plurality of openings that are configured to pass an amount of inert gas from the first plenum into a second plenum defined between the faceplate and the underplate, in fluid communication with the plurality of openings of each zone such that the inert gas mixes with the process gas before exiting the showerhead assembly.

Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor film including an oxide semiconductor material, forming a gate electrode facing the semiconductor film, forming a gate insulating film between the gate electrode and the semiconductor film, the gate insulating film having a side face that is uncovered with the gate electrode; and washing the side face of the gate insulating film with use of a chemical liquid that is able to dissolve the oxide semiconductor material.

Abstract: In accordance with an exemplary embodiment of the present disclosure, a method of manufacturing an organic light-emissive display can be provided. A plurality of electrodes can be provided on a substrate. A first hole conducting layer can be deposited via inkjet printing over the plurality of electrodes on the substrate. A liquid affinity property of selected surface portions of the first hole conducting layer can be altered to define emissive layer confinement regions. Each emissive layer confinement region can have a portion that respectively corresponds to each of the plurality of electrodes provided on the substrate. An organic light-emissive layer can be deposited via inkjet printing within each emissive layer confinement region.

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Abstract: A method for etching a target layer on a substrate by a dry etching process includes at least one etching cycle, wherein an etching cycle includes: depositing a carbon halide film using reactive species on the target layer on the substrate; and etching the carbon halide film using a plasma of a non-halogen hydrogen-containing etching gas, which plasma alone does not substantially etch the target layer, thereby generating a hydrogen halide as etchant species at a boundary region of the carbon halide film and the target layer, thereby etching a portion of the target layer in the boundary region.

Abstract: Example embodiments relate to a method of forming a photoresist pattern and a method of fabricating a semiconductor device using the same. The method of fabricating a semiconductor device comprises forming a mask layer on a substrate, forming a photoresist pattern on the mask layer, the photoresist pattern having pattern portions at a first height and recess portions, applying a first liquid onto the photoresist pattern, filling the recess portions with a pattern filler at a second height, the pattern filler having an higher etch rate than the etch rate of the pattern portions to the same etchant, removing the first liquid, etching the pattern filler after removing the first liquid, etching the mask layer via the photoresist pattern to form a mask pattern, and etching the substrate via the mask pattern to form a fine pattern.

Abstract: An etching method for etching a silicon-containing layer into a pattern of a mask is provided. The mask is formed by etching, from a block copolymer layer that includes a first polymer and a second polymer, that is layered on the silicon-containing layer of an object to be processed via an intermediate layer, and that is enabled to be self-assembled, a second region including the second polymer and the intermediate layer right under the second region. The etching method includes generating plasma by supplying a process gas including carbon C, sulfur S, and fluorine F to the inside of a processing chamber of a plasma processing apparatus in which the object to be processed is provided; and forming a protective film on the mask and etching the silicon-containing layer according to the generated plasma.

Abstract: A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.

Abstract: According to one embodiment, a pattern forming method includes supplying, onto an under layer, a self-organization material including a block copolymer which includes a first polymer and a second polymer, and a third polymer having a molecular structure with oxygen attached to a cyclic structure, wherein the third polymer is bonded to the first polymer, and phase-separating the block copolymer to form a phase-separation pattern on the under layer.

Abstract: A patterning method is disclosed. A hard mask layer, a lower pattern transfer layer, an upper pattern transfer layer are formed on a target layer. A first SARP process is performed to pattern the upper pattern transfer layer into an upper pattern mask. A second SARP process is performed to pattern the lower pattern transfer layer into a lower pattern mask. The upper pattern mask and the lower pattern mask define hole patterns. The hole patterns is filled with a dielectric layer. The dielectric layer and the upper pattern mask are etched back until the lower pattern mask is exposed. The lower pattern mask is removed, thereby forming island patterns. Using the island patterns as an etching hard mask, the hard mask layer is patterned into hard mask patterns. Using the hard mask patterns as an etching hard mask, the target layer is patterned into target patterns.

Abstract: Methods of forming non-mandrel cuts. A dielectric layer is formed on a metal hardmask layer, and a patterned sacrificial layer is formed on the dielectric layer. The dielectric layer is etched to form a non-mandrel cut in the dielectric layer that is vertically aligned with the opening in the patterned sacrificial layer. A metal layer is formed on an area of the metal hardmask layer exposed by the non-mandrel cut in the dielectric layer. The metal hardmask layer is patterned with the metal layer masking the metal hardmask layer over the area.

Abstract: Techniques herein provide methods for depositing spin-on metal materials for creating metal hard mask (MHM) structures without voids in the deposition. This includes effective spin-on deposition of TiOx, ZrOx, SnOx, HFOx, TaOx, et cetera. Such materials can help to provide differentiation of material etch resistivity for differentiation. By enabling spin-on metal hard mask (MHM) for use with a multi-line layer, a slit-based or self-aligned blocking strategy can be effectively used. Techniques herein include identifying a fill material to fill particular openings in a given relief pattern, modifying a surface energy value of surfaces within the opening such that a contact angle value of an interface between the fill material in liquid form and the sidewall or floor surfaces enables gap-free or void-free filling.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.

Abstract: A method of forming a semiconductor device includes following steps. First of all, a first work function layer is formed on a substrate. Next, a first patterned photoresist layer is formed on the first work function layer. Then, the first work function layer is partially removed by using the first patterned photoresist layer as a mask to form a patterned first work function layer. Subsequently, the first patterned photoresist layer is removed by providing radical oxygen.

Abstract: A method for growing a transition metal dichalcogenide on a substrate, the method including providing a growth substrate having a first side and a second side opposite the first side; providing a source substrate having a first side and a second side opposite the first side; depositing a transition metal oxide on at least a portion of the first side of the source substrate; combining the growth substrate with the source substrate such that the first side of the growth substrate contacts the transition metal oxide, the combining producing a substrate stack; exposing the substrate stack to a chalcogenide gas, whereby the transition metal oxide reacts with the chalcogenide gas to produce a layer of a transition metal dichalcogenide on at least a portion of the first side of the growth substrate; and removing the source substrate from the growth substrate having the layer of the transition metal dichalcogenide thereon.

Abstract: A method includes providing a substrate that underlies a layer of SiGe; forming a plurality of fins in the layer of SiGe. Each formed fin has a fin shape and fin location preserving hard mask layer on a top surface. The method also includes depositing Si on a first subset of the set of fins in what will be an nFET area; performing a Si—Ge inter-mixing process on the first subset of fins to reduce a concentration of Ge in the first subset while producing a Si—Ge intermix layer; removing the Si—Ge intermix layer leaving the first subset of fins having the reduced concentration of Ge, and forming a second subset of fins in what will be a pFET area. The second subset is also formed from the layer of SiGe and has a greater percentage of Ge than a percentage of Ge in the first subset of fins.

Abstract: The present invention provides a packaging method for an electronic device, which includes a step of forming a packaging substrate, the step of the forming a packaging substrate includes: forming, on a base substrate, a defining pattern which comprises a groove for defining position of frit; providing colloidal frit in the groove; presintering the colloidal frit to obtain preliminarily cured frit; polishing upper surfaces of the defining pattern and the preliminarily cured frit; and removing the defining pattern, and completely curing the preliminarily cured frit, so as to form solid frit on the base substrate. The present invention also provides a packaging system. By using the packaging method provided by the present invention, a better packaging effect can be achieved.

Abstract: A lithography method is provided in accordance with some embodiments. The lithography method includes forming an under layer of a polymeric material on a substrate; forming a silicon-containing middle layer on the under layer, wherein the silicon-containing middle layer has a silicon concentration in weight percentage less than 20% and is wet strippable; forming a patterned photosensitive layer on the silicon-containing middle layer; performing a first etching process to transfer a pattern of the patterned photosensitive layer to the silicon-containing middle layer; performing a second etching process to transfer the pattern to the under layer; and performing a wet stripping process to the silicon-containing middle layer and the under layer.

Abstract: An etching method is provided for performing an etching process on an etching target film arranged on a substrate. The etching method includes the steps of supplying a treatment gas including a halogen-containing gas, hydrogen gas, an inert gas, and oxygen gas; performing a treatment on a patterned mask arranged on the etching target film using a plasma generated from the treatment gas; and etching the etching target film that has undergone the treatment using a plasma generated from an etching gas.

Abstract: Methods for removing residual polymers formed during etching of a boron-doped amorphous carbon layer are provided herein. In some embodiments, a method of etching a feature in a substrate includes: exposing a boron doped amorphous carbon layer disposed on the substrate to a first plasma through a patterned mask layer to etch a feature into the boron doped amorphous carbon layer, wherein the first plasma is formed from a first process gas that reacts with the boron doped amorphous carbon layer to form residual polymers proximate a bottom of the feature; and exposing the residual polymers to a second plasma through the patterned mask layer to etch the residual polymers proximate the bottom of the feature, wherein the second plasma is formed from a second process gas comprising nitrogen (N2), oxygen (O2), hydrogen (H2), and methane (CH4).

Abstract: A plasma etching method includes a plasma process of plasma-processing a surface of a photoresist, which has a predetermined pattern with plasma generated from a hydrogen-containing gas. Further, the plasma etching method includes an etching process of etching a silicon-containing film with plasma generated from a CF-based gas and a gas containing a CHF-based gas by using the plasma-processed photoresist as a mask. Furthermore, in the plasma etching method, the plasma process and the etching process are repeated at least two or more times.

Abstract: The semiconductor device includes an insulating film that is formed using a cyclic siloxane having a six-membered ring structure as a raw material; a trench that is formed in the insulating film; and a interconnect that is configured by a metal film embedded in the trench. In the semiconductor device, a modified layer is formed on a bottom surface of the trench, in which the number of carbon atoms and/or the number of nitrogen atoms per unit volume is larger than that inside the insulating film.

Abstract: Methods of exchanging ligands to form colloidal nanocrystals (NCs) with chalcogenocyanate (xCN)-based ligands and apparatuses using the same are disclosed. The ligands may be exchanged by assembling NCs into a thin film and immersing the thin film in a solution containing xCN-based ligands. The ligands may also be exchanged by mixing a xCN-based solution with a dispersion of NCs, flocculating the mixture, centrifuging the mixture, discarding the supernatant, adding a solvent to the pellet, and dispersing the solvent and pellet to form dispersed NCs with exchanged xCN-ligands. The NCs with xCN-based ligands may be used to form thin film devices and/or other electronic, optoelectronic, and photonic devices. Devices comprising nanocrystal-based thin films and methods for forming such devices are also disclosed. These devices may be constructed by depositing NCs on to a substrate to form an NC thin film and then doping the thin film by evaporation and thermal diffusion.

Abstract: A manufacturing method for a grating is disclosed for the angular dispersion of light impinging the grating. The grating comprises tapered structures and cavities. A cavity width and/or corrugation amplitude is varied for achieving a desired grating efficiency according to calculation. A method is disclosed for conveniently creating gratings with variable cavity width and/or corrugation amplitude. The method comprises the step of anisotropically etching a groove pattern into a grating master. Optionally a replica is produced that is complementary to the grating master. By variation of an etching resist pattern, the cavity width of the grating may be varied allowing the optimization towards different efficiency goals.

Abstract: A method for producing a semiconductor apparatus substrate includes steps of: forming silicon-containing film having silicon content of 1% by mass or more and 30% by mass or less on an organic under layer film formed on an substrate; forming a resist film on silicon-containing film; forming a resist pattern by exposing and developing resist film; transferring pattern to silicon-containing film using resist pattern as a mask; transferring pattern to organic under layer film using silicon-containing film as a mask to leave part or all of silicon-containing film on organic under layer film; implanting ions into substrate using organic under layer film as a mask; and peeling organic under layer film used as mask for ion implantation on which part or all of silicon-containing film remains, with peeling liquid.

Abstract: An embodiment includes a method comprising: etching a material to expose a metal component in a metal layer, which is located on a substrate, while the substrate is in an etch chamber that is under vacuum; and performing an ash process on the metal component while the substrate is still in the etch chamber that is still under vacuum; wherein the material includes at least one of a dielectric and a mask and the metal component includes at least one of an interconnect, a via, and a contact. Other embodiments are described herein.

Abstract: Embodiments of the present invention provide methods for etching a material layer using synchronized RF pulses. In one embodiment, a method includes providing a gas mixture into a processing chamber, applying a first RF source power at a first time point to the processing chamber to form a plasma in the gas mixture, applying a first RF bias power at a second time point to the processing chamber to perform an etching process on the substrate, turning off the first RF bias power at a third time point while continuously maintaining the first RF source power on from the first time point through the second and the third time points, and turning off the first RF source power at a fourth time point while continuously providing the gas mixture to the processing chamber from the first time point through the second, third and fourth time points.

Abstract: According to one embodiment, a mask includes a line-and-space mask pattern. The mask has a separation portion separating a line pattern in a predetermined region within the line-and-space mask pattern. The mask also includes a connection pattern arranged in a crossing direction crossing the extending direction of the line pattern connecting the separated line patterns. The connection pattern is arranged on a position where the end of the line pattern, which is separated by the separation portion, projects from the connection pattern.

Abstract: A method is provided for forming a multi-color OLED device that includes providing a substrate, coating the substrate with a fluorinated photoresist solution to form a first photo-patternable layer and exposing it to produce a first pattern of exposed fluorinated photoresist material and a second pattern of unexposed fluorinated photoresist material, developing the photo-patternable layer with a fluorinated solvent to remove the second pattern of unexposed fluorinated photoresist material without removing the first pattern of exposed fluorinated photoresist material, depositing a first organic light-emitting material over the substrate to form a first organic light-emitting layer for emitting a first color of light and applying the first pattern of exposed fluorinated photoresist material to control the removal of a portion of the first organic light-emitting layer.

Abstract: A sensing device has a semiconductor substrate with an opening and a membrane spanning the opening. A heater is arranged on the membrane. To reduce the thermal conductivity of the membrane, a recess is etched into the membrane from below.

Abstract: A photoresist stripping and cleaning composition free from N-alkylpyrrolidones and added quaternary ammonium hydroxides comprising a component (A) which comprises the polar organic solvents N-methylimidazole, dimethylsulfoxide and 1-aminopropane-2-ol.

Abstract: A manufacturing method of an array substrate, comprising the following steps: S1 forming a gate signal line and a gate electrode on a base substrate, successively depositing a gate insulating layer, an active layer, and a metal layer, faulting a mask formed of photoresist on the metal layer, and removing the metal layer outside a region for forming a data line and source/drain electrodes through the mask; S2. simultaneously etching the active layer and ashing the photoresist so as to expose the metal layer within a channel region; S3. etching the active layer exposed by the photoresist after being ashed after the step S2; S4. removing the metal layer within the channel region.

Abstract: Methods for reducing the line width roughness on a photoresist pattern are provided herein. In some embodiments, a method of processing a patterned photoresist layer disposed atop a substrate includes flowing a process gas into a processing volume of a process chamber having the substrate disposed therein; forming a plasma within the process chamber from the process gas, wherein the plasma has a ion energy of about 1 eV to about 10 eV; and etching the patterned photoresist layer with species from the plasma to at least one of smooth a line width roughness of a sidewall of the patterned photoresist layer or remove debris.

Abstract: A plasma processing method in which performing a plasma etching on metal layers formed on a substrate is conducted to form a pattern having the metal layers in a stacked structure, and then a deposit containing a metal that forms the metal layers and being deposited on a sidewall portion of the pattern is removed, the method includes: forming a protective layer by forming an oxide or chloride of the metal on sidewall portions of the metal layers; removing the deposit by applying a plasma of a gas containing fluorine atoms; and reducing the oxide or chloride of the metal by applying a plasma containing hydrogen after forming the protective layer and removing the deposit.

Abstract: A method of manufacturing a semiconductor device may include: forming an interlayer insulating layer having openings on a substrate; forming a metal layer in the openings and on the interlayer insulating layer, the metal layer including a sidewall portion on a sidewall of each of the openings and a bottom portion on a bottom surface of each of the openings, wherein the bottom portion is thicker than the sidewall portion; reflowing the metal layer to form metal patterns in the openings, the metal patterns having top surfaces at a level lower than a topmost surface of the interlayer insulating layer; and/or forming capping patterns covering the metal patterns in the openings.

Abstract: Embodiments of the present invention provide an array substrate, a method for manufacturing the same and a display device. The method for manufacturing a thin film transistor array substrate comprises: forming a passivation layer and a resin layer on a substrate in sequence; removing a part of the resin layer through a patterning process, so as to form a resin-layer via hole passing through the resin layer; etching the passivation layer under the resin-layer via hole, so as to form a via hole passing through the resin layer and the passivation layer; treating the via hole with an etching process, so that a sidewall at the resin layer and a sidewall at the passivation layer for the via hole smoothly adjoin.

Abstract: A land grid array (LGA) package including a substrate having a plurality of lands formed on a first surface of the substrate, a semiconductor chip mounted on a second surface of the substrate, a connection portion connecting the semiconductor chip and the substrate, and a support layer formed on part of a surface of a first land.

Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first area with a first poly layer and a second area with a second poly layer is provided. A nitride HM film is then deposited above the first poly layer of a first device in the first area and above the second poly layer in the second area. Afterwards, a first patterned passivation is formed on the nitride HM film in the first area to cover the nitride HM film and the first device, and a second patterned passivation is formed above the second poly layer in the second area. The second poly layer in the second area is defined by the second patterned passivation.

Abstract: A method of plasma etching a silicon carbide workpiece includes forming a mask on a surface of the silicon carbide workpiece, performing an initial plasma etch on the masked surface using a first set of process conditions, wherein the plasma is produced using an etchant gas mixture which includes i) oxygen and ii) at least one fluorine rich gas which is present in the etchant gas mixture at a volume ratio of less than 50%, and subsequently performing a bulk plasma etch process using a second set of process conditions which differ from the first set of process conditions.

Abstract: Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. A photoresist layer is patterned to simultaneously define mask elements in the array, interface and periphery areas. The pattern is transferred to an amorphous carbon layer. Spacers are formed on the sidewalls of the patterned amorphous carbon layer. Protective material is deposited and patterned to expose mask elements in the array region and in parts of the interface or periphery areas. Exposed amorphous carbon is removed, leaving free-standing spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which the substrate is etched.