Abstract: A method and apparatus for fabricating electrochemical copper interconnections between the component parts of an integrated circuit on a semiconductor device. A cathodic platter is provided that includes contact pins that contact the surface of a semiconductor wafer at predetermined locations during the electrochemical deposition process. The contact pins are arranged on the cathodic platter so that when placed on the surface of the semiconductor wafer the contact pins surround the perimetrical edges of each respective semiconductor device on the semiconductor wafer. Once the semiconductor wafer is properly positioned on the cathodic platter, a copper conductive layer can be electrochemically and uniformly deposited on the surface of the semiconductor device.

Abstract: A process for forming a polysilicon line having linewidths below 0.23 &mgr;m. The layer of polysilicon (20) is deposited over a semiconductor body (10). A layer of bottom anti-reflective coating (BARC) (30) is deposited over the polysilicon layer (20). A resist pattern (40) is formed over the BARC layer (30) using conventional lithography (e.g., deep UV lithography). The BARC layer (30) is etched with an etch chemistry of HBr/O2 using the resist pattern (40) until the endpoint is detected. The BARC layer (30) and resist pattern (40) are then overetched using the same etch chemistry having a selectivity of approximately one-to-one between the BARC and resist. The overetch is a timed etch to control the linewidth reduction in the resist/BARC pattern. The minimum dimension of the pattern (50) is reduced to below the practical resolution limit of the lithography tool. Finally, the polysilicon layer (20) is etched using the reduced width pattern (50).

Abstract: Described is a method of increasing the capacitance of semiconductor capacitors by providing a first solid-state electrode pattern on a semiconductor medium, etching topographic features on said first electrode pattern in a manner effective in increasing the surface area of said first electrode pattern, depositing a dielectric layer upon said electrode pattern that substantially conforms to said topographic features, and depositing a second solid-state electrode pattern upon said dielectric layer and sufficiently insulated from said first solid-state electrode pattern so as to create a capacitance with said first solid-state electrode pattern.

Abstract: In the manufacture of a micromechanical device, a substrate, having a mask thereon, is etched using a flourine-containing etchant gas or vapour in the absence of a plasma through an opening in the mask to a desired depth to form a trench having a side wall and a base in the substrate. A layer of protecting substance is deposited on the exposed surfaces of the substrate and mask, and the protecting substance is then selectively removed from the base. The base is then etched using the fluorine-containing etchant.

Abstract: A method and system for etching gate oxide during transistor fabrication is disclosed. The method and system begin by depositing a gate oxide on a substrate, followed by a deposition of a tunnel oxide mask over a portion of the gate oxide. The method and system further include performing a combination dry/wet-etch to remove the gate oxide uncovered by the tunnel oxide mask, which minimizes tunnel oxide undercut.

Abstract: A method for fabricating MEMS wherein a structural member is released without using a sacrificial layer. In one embodiment, the method comprises forming a buried hydrogen-rich layer in a semiconductor substrate, defining a release structure in the semiconductor substrate above the buried hydrogen-rich layer, and separating at least a portion of the release structure from the semiconductor substrate by cleaving the semiconductor substrate at the buried hydrogen-rich layer. The method can be used to fabricate hybrid devices wherein a MEMS device and a semiconductor device are formed on the same chip.

Abstract: A capacitor includes a substrate, an insulating layer on the substrate, the insulating layer having a contact hole, a first storage node in the contact hole and on the insulating layer, a second storage node on a peripheral portion of the first storage node, the second storage node having a planar top surface, a dielectric layer on the surface of the first and second storage nodes, and a plate node on the dielectric layer.

Abstract: In a method of etching an Al or Al alloy layer, an Al or Al alloy layer is formed on an underlying surface, the surface of the Al or Al alloy layer is processed with TMAH, a resist pattern is formed on the surface of the Al or Al alloy layer processed with TMAH, and by using the resist pattern as an etching mask, the Al or Al alloy layer is wet-etched.

Abstract: The high Q inductor process for reducing substrate interaction of integrated inductors includes etching away some of the silicon substrate after the inductor has been formed on the substrate. A first etch process is performed to form an opening in the center of the inductor exposing the silicon substrate. A second etch process is performed to etch the exposed silicon substrate to form a trench in the silicon substrate. A third etch process is performed to etch the trench into an inverted pyramidal cavity within the substrate and extending beneath the inductor. The pyramidal cavity is then filled with a solution, such as spin-on-glass thereby providing mechanical support for the inductor.

Abstract: A method of fabricating a mask forms a rectangular opening within etch resistant material that overlays a substrate. The mask preferably comprises two layers of photoresist separated by a layer of light blocking material. One of the layers of photoresist is patterned per a longitudinal exposure strip, and the other per an overlap of a lateral exposure strip with the longitudinal exposure strip, so as to provide an opening for the mask where the two overlap. With this mask over a substrate, the substrate is etched to form a container therein with a rectangular cross-section corresponding to the aperture of the mask. The container is then lined with electrically conductive material, dielectric, and electrically conductive material respectively to form a capacitor in the container—e.g., a container-cell capacitor for a DRAM device.

Abstract: A single mask process for manufacture of a FRED employs a thick oxide layer over an N type silicon surface and a thin nitride layer over the oxide. A single mask defines FRED device spaced P diffusions. The oxide spanning the P diffusions is laterally etched away, under the nitride layer to expose the surface of adjacent P diffusions and the spanning N type silicon surface. All nitride is then removed and a top contact layer of aluminum is applied atop the silicon surface, contacting a P guard ring diffusion; the surface of the P diffusions defining PN junctions; and the top of the N silicon to define a Schottky diode contact.

Abstract: A manufacturing method for a micromechanical device. In this method, a substrate is prepared with a plating base area to accommodate an anchoring region, and an adhesive layer is formed and structured on the substrate, so that the anchoring region is formed in the plating base area in the form of a quasi-insular region in a recess of the adhesive layer. The quasi-insular region is connected to the adhesive layer outside of the plated based area by at least one thin web. A mask is formed on the adhesive layer and structured so that the anchoring region and an overgrowth region adjacent to the anchoring region remain unmasked. An electroplated layer is deposited on the unmasked anchoring region so that the overgrowth region is overgrown, and the mask and the part of the adhesive layer that has not been overgrown are removed.

Abstract: A fabrication method for a capacitor having high capacitance that increases capacitance of a capacitor and consequently decreases defective semiconductor devices includes: forming a doped first polysilicon layer pattern on a semiconductor substrate; forming a silicide film pattern on the first polysilicon layer pattern; annealing the semiconductor substrate; sequentially forming a first insulating film and a second insulating film over the silicide film pattern; forming a contact hole to expose a portion of the silicide film pattern and then sequentially placing the semiconductor substrate in an etchant solution and a buffered etchant solution to remove a portion of the first insulating film formed on the silicide film pattern; forming a first capacitor electrode on a portion of an upper surface of the second insulating film pattern and the silicide film pattern, and at inner walls of the contact hole; and forming a dielectric layer on an outer surface of the lower electrode and then a second capacitor electr

Abstract: A method and apparatus for manufacturing a semiconductor physical quantity sensor according to the present invention achieves the high sensing accuracy and reliability and prevents a sticking phenomenon. Specifically, a semiconductor physical quantity sensor is cleaned by a displacement liquid and is dried while a SOI substrate is revolving. The number of revolutions is determined so that a suction force (Fs), which acts on a silicon substrate by a surface tension of the displacement liquid, a sensor spring force FK and a centrifugal force (Fr) generated by the acceleration in the revolution can satisfy the following condition: (FK+Fr)>FS. In order to prevent the sticking phenomenon after the stop of the spray, the semiconductor physical quantity sensor is dried by spraying an inert gas such as nitrogen including minus ions so that the revolving SOI substrate can eliminate static electricity generated by friction of the air flow.

Abstract: An etch process for increasing the alignment tolerances between capacitor components and an adjacent contact corridor in Dynamic Random Access Memories. The etch process is implemented in a capacitor structure formed over a semiconductor substrate The capacitor structure includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. The second conductor has a horizontal region laterally adjacent to and extending away from the first conductor.

Abstract: The invention has two embodiments for forming a contact plug having large nail shaped landing pad. The large pad areas increase the overlay tolerances. The first embodiment comprises forming first 20 and second 24 insulating layers over a semiconductor structure. A first photoresist layer 28 with a first opening is formed over the second insulating layer 24. The second insulating layer 24 is isotropically etched using an etchant with a high selectivity thereby forming a disk shaped opening 26A. The disk shaped opening is used to define the large nail shaped landing pad. The first insulating layer 20 is etched using a dry etch thereby forming a nail shaped contact opening 26. The opening is filled with polysilicon to form the nail shaped conductive plug 36. The second embodiment begins by forming a first insulating layer 40 over a semiconductor structure. A first photoresist layer 44 with a first opening is formed over the first insulating layer 24.

Abstract: A dry etch using CFx in an O2-rich environment will clean the contact/via at the same time it retracts a layer of TiN enclosed in the dielectric layer, such as the plate layer in a Capacitor-Under-Bitline DRAM cell.

Abstract: A method of manufacturing a flash memory device in which minimal gate edge lifting is accomplished by etching a portion of the ends of the layer of tunnel oxide forming cavities, forming silicon nitride plugs in the cavities and forming a layer of oxide on the surface of the flash memory device wherein the silicon nitride plugs minimize gate edge lifting.

Abstract: One embodiment of the invention is a method for forming a raised structure on a semiconductor wafer. In the method, a patterned masking layer is formed over a wafer layer. The patterned masking layer typically includes a first mask covering a first region of the wafer layer and at least one side mask adjacent to the first mask, covering a side region of the wafer layer. After forming the patterned masking layer, exposed portions of the wafer layer adjacent the masks are removed using the patterned masking layer. This leaves a first raised structure (relative to an adjacent removed area) in the first substrate region and a sacrificial raised structure in the side region adjacent the first raised structure. After removing the exposed portions of the wafer layer, the sacrificial raised structure is selectively removed while leaving the first raised structure intact.

Abstract: A method for fabricating an inter-metal dielectric layer. Several conducting wires are formed on a substrate, and openings lie between the adjacent conducting wires. A first dielectric layer fills the openings, and the surface of the first dielectric layer is lower than that of the conducting wires. A spacer is formed on a sidewall of each of the conducting wires. The first dielectric layer is removed to expose the bottom of the spacer. A second dielectric layer is formed to cover the conducting wires.

Abstract: A non-volatile semiconductor memory device and a manufacturing method of the same where an etching residue generating short-circuit between gates is made harmless or a device is miniaturized are obtained. The method includes the steps of forming on a semiconductor substrate, a first gate layer and a second gate layer, forming a second gate electrode by etching the second gate layer, forming a first gate electrode by etching the first gate layer using the second gate electrode as a mask, and removing a residue left on a step portion by isotropic etching.

Abstract: A thin-film system is deposited onto a surface of a semiconductor region. After at least one window has been opened in the thin-film system, the window serves as a mask for a first selective processing of a first semiconductor partial region. By undercutting the thin-film system, the edge of the window is drawn back approximately uniformly by a mean undercutting depth. The at least one enlarged window serves as a mask for a second selective processing of a second semiconductor partial region. A semiconductor structure is also provided.

Abstract: The present invention is directed toward building a microelectronic device in which a semiconductor substrate has thereon an etch buffer layer used in a processing method in which the buffer layer will act as an etch uniformity aid. In a method of making the microelectronic device, a semiconductor substrate is covered with an etch buffer layer and with an insulative layer. A first etch is performed by patterning and etching through a mask. The first etch penetrates the insulative layer, forms a cavity therein, and is selective to the buffer layer so as to expose the buffer layer. A second etch is performed that is selective to the insulative layer and the semiconductor substrate, and is not selective to the buffer layer. The buffer layer can be an insulative material of a type other than the material of the insulative layer or the buffer layer can also be of a conductive material.

Abstract: A sensor having high sensitivity is formed using a suspended structure with a high-density tungsten core. To manufacture it, a sacrificial layer of silicon oxide, a polycrystal silicon layer, a tungsten layer and a silicon carbide layer are deposited in succession over a single crystal silicon body. The suspended structure is defined by selectively removing the silicon carbide, tungsten and polycrystal silicon layers. Then spacers of silicon carbide are formed which cover the uncovered ends of the tungsten layer, and the sacrificial layer is then removed.

Abstract: The present disclosure includes a method of plasma etching a trench having rounded top corners in a silicon substrate. One embodiment includes the following general steps: a) providing a semiconductor structure comprising a hard masking layer, overlying a silicon substrate; b) plasma etching through said hard masking layer and any additional underlying layers overlying said silicon substrate using at least one plasma feed gas which does not provide polymer deposition on surfaces of said semiconductor structure during etching; where said plasma etching exposes a face of said silicon substrate; and c) plasma etching at least a first portion of a trench into said silicon substrate using reactive species generated from a feed gas comprising a source of fluorine, a source of carbon, a source of hydrogen, and a source of high energy species which provide physical bombardment of said silicon substrate.

Abstract: An integrated circuit and method are provided for sensing activity such as temperature variations in a surrounding environment. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to the switch detecting circuit region. The sensor switching region preferably includes a fixed contact layer, a sacrificial layer on the fixed contact layer, and a floating contact on the sacrificial layer and having portions thereof overlying the fixed contact layer in spaced relation therefrom in an open switch position and extending lengthwise generally transverse to a predetermined direction. The floating contact preferably includes at least two layers of material. Each of the at least two layers have a different thermal expansion coefficient so that the floating contact displaces in the predetermined direction responsive to a predetermined temperature variation so as to contact the fixed contact layer and thereby form a closed switch position.

Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.

Abstract: A method for forming a semiconductor device having air regions, the method comprises providing a base, forming a pattern of metal leads, depositing a layer of oxide over the metal leads, forming a layer of nitride over said layer of oxide, opening and etching a trench down to the base layer of material, and depositing and planarizing a dielectric layer. An alternate approach teaches the deposition of a layer of SOG over the layer of oxide that has been deposited over the metal leads, planarizing this layer of SOG down to the top of the metal leads, depositing a layer of PECVD oxide, patterning and etching this layer of PECVD oxide thereby creating openings that are in between the metal leads. The SOG that is between the metal leads can be removed thereby creating air gaps as the intra-level dielectric for the metal leads.

Abstract: A substrate has an insulating surface; a fine wire region disposed on the insulating surface of the substrate and extending long in one direction; a first insulating film formed on the fine wire region at least at a partial area along the longitudinal direction of the fine wire region; and a first micro box region formed on the first insulating film over the fine wire region at a partial area along the longitudinal direction of the fine wire region a semiconductor device. The semiconductor device has a fine wire region and a micro box region to realize control of a single electron level. The manufacturing method for the semiconductor device is also disclosed.

Abstract: A wafer structure on an IC chip allows the bonding pads on the IC chip to be firmly secured to the IC chip, thereby preventing detachment of the bonding pads during assembly of the IC package. The wafer structure comprises a substrate on which at least a pad area is defined. The pad area is formed with a first insulating layer, a gate on the first insulating layer, a second insulating layer on the gate, and a third insulating layer on the second insulating layer. The second insulating layer has a plurality of lower openings formed therethrough and the third insulating layer has a plurality of upper openings formed therethrough, each upper opening corresponding to one of the lower openings. The lower openings are wider than the upper openings. Plugs are formed in the lower and upper openings and are bonded to a metallization layer which serves as a bonding pad for the IC chip.

Abstract: A method of Si anisotropic etching makes it possible to relax the restrictions imposed upon the processing configuration of an Si substrate provided with the <100> plane orientation. This Si anisotropic etching method can be preferably used for the formation of the ink supply opening of an ink jet head, for example. When an Si material (Si substrate) having the <100> crystal plane orientation is processed by this anisotropic etching method, it is arranged to give heat treatment to such Si material in advance before etching. Thus, the processed section can be obtained in a bent configuration formed by the two <111> planes of crystal plane orientation. Therefore, the etching initiation surface is made smaller than that needed for the conventional art even when the same width should be obtained for a penetrating process, hence making a chip smaller accordingly for the reduction of costs.

Abstract: A process for forming a trench in a semiconductor material is provided. The process includes (a) providing a semiconductor substrate, a first mask layer adjacent the surface of the semiconductor substrate, and a second mask layer adjacent the surface of the first mask layer, the second mask layer defining a first open area and the first mask layer defining a second open area that is larger than the first open area and aligned therewith in a manner so that in the area of the openings the first mask layer is undercut with respect to the second mask layer; and (b) removing a portion of the semiconductor substrate through the open area defined by the second mask layer to form a trench in said semiconductor substrate. An IC device formed using the process is also provided.

Abstract: The present invention provides a method of forming a dual damascene structure on a semiconductor wafer. The semiconductor wafer comprises a substrate, and a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer and a photoresist layer sequentially formed on the substrate. A dry-etching process is performed first to vertically remove a specific portion of the second silicon oxide layer down to the silicon nitride layer so as to form a hole. Then the photoresist layer is removed and the portion of the silicon nitride layer positioned under the hole is removed using a phosphoric acid solution. A lithographic process is then performed to form a photoresist layer on the second silicon oxide layer, the photoresist layer comprising a line-shaped opening positioned above the hole with a width larger than the diameter of the hole. Then an etching process is performed along the line-shaped opening to vertically remove the second silicon oxide layer and the first silicon oxide layer.

Abstract: A process for reducing dimensions of circuit elements in a semiconductor device. The process reduces feature sizes by using an intermediate etchable mask layer between a photo-resistive mask and a layer to be etched. The etchable mask layer below the photo-resistive mask is etched and portions remain which undercut the pattern on the photo-resistive mask. After removing the photo-resistive mask, the remaining mask portions are then used to mask the layer to be etched. By undercutting the photo-resistive mask, the mask portions form a pattern having features with widths that are less than widths of features in the photo-resistive mask. The layer to be etched can then be etched to provide circuit elements with reduced dimensions.

Abstract: A device manufacturing method prevents damage from plasma charging and vertical cross talk. The method comprises the steps of forming an insulating layer over a substrate that has a MOS device and source/drain regions already formed thereon. The insulating layer is formed by a non-plasma operation so that plasma damage is avoided. Thereafter, a conductive layer is formed over the substrate. The conductive layer is used to channel away excess charges produced during subsequent plasma operations, thereby balancing electric potential and preventing damage to the device from current flow. Subsequently, an inter-layer dielectric layer is formed over the conductive layer, and then the inter-layer dielectric layer, the conductive layer and the insulating layer are patterned to form an opening that exposes the source/drain region.

Abstract: A method for manufacturing a via structure comprising the steps of providing a semiconductor substrate, and then forming conductive line and dielectric layer over the substrate. Next, a photolithographic and a first etching operation are conducted so that an opening in the dielectric layer exposing the conductive line surface is formed. The first etching operation uses several etchants including fluorobutane, which has the highest concentration. Since there is a re-entrance structure at the bottom of the opening, a second etching operation is performed. In the second etching operation, a portion of the conductive line is etched for a fixed time interval to control the degree of etching. Consequently, a slanting surface is formed at the bottom of the opening and the re-entrance structure is eliminated. With a planarized bottom, step coverage of subsequently deposited material is increased.

Abstract: The present invention is directed toward building a microelectronic device in which a semiconductor substrate has thereon an etch buffer layer used in a processing method in which the buffer layer will act as an etch uniformity aid. In a method of making the microelectronic device, a semiconductor substrate is covered with an etch buffer layer and with an insulative layer. A first etch is performed by patterning and etching through a mask. The first etch penetrates the insulative layer, forms a cavity therein, and is selective to the buffer layer so as to expose the buffer layer. A second etch is performed that is selective to the insulative layer and the semiconductor substrate, and is not selective to the buffer layer. The buffer layer can be an insulative material of a type other than the material of the insulative layer or the buffer layer can also be of a conductive material.

Abstract: A crystalline semiconductor gate electrode having a re-entrant geometry and a process for making same are disclosed. The novel gate electrode may be formed from a polysilicon layer on a substrate by first implanting a masked polysilicon layer with a neutral species, i.e., a species which will not introduce a dopant into the polysilicon, such as a Group IV element, e.g., silicon, or a Group VIII element, e.g., argon. The neutral species is implanted into the masked polysilicon layer at an angle to provide a tapered implanted region which undercuts one side of the length (long dimension) of the mask. The substrate may then be rotated 180.degree. and then again implanted to provide a tapered implanted region which undercuts the opposite side of the length of the mask. When gate electrodes with such re-entrant geometry are to be formed on a substrate with their long axes at right angles to one another, i.e.

Abstract: A method for etching a metal layer on a substrate with dimensional control is disclosed. First, an anti-reflection layer is formed over the metal layer. A photoresist layer is then formed over the anti-reflection layer. A metal layer pattern is defined by patterning the photoresist layer. An etching process is performed to etch the anti-reflection layer with dimensional loss compared with the metal layer pattern, by using the photoresist layer as a mask. Another etching process is performed to etch the metal layer with dimensional gain compared with the anti-reflection layer, by using the anti-reflection layer as a mask. A metal layer with nearly zero-biased dimension is achieved.

Abstract: A process for forming an etch mask having a discontinuous regular pattern utilizes beads, each of which has a substantially unetchable core covered by a removable spacer coating. Beads which have a core and a spacer coating are dispensed as a hexagonally-packed monolayer onto a thermo-adhesive layer, which is on a target layer. The beads are kept in place by a bead confinement wall. Following a vibrational step which facilitates hexagonal packing of the beads, the resultant assembly is heated so that the beads adhere to the adhesive layer. Excess beads are then discarded. Spacer shell material is then removed from each of the beads, leaving core etch masks. The core-masked target layer is then plasma etched to form a column of target material directly beneath each core. The cores and any spacer material underneath the cores are removed. The resulting circular island of target material may be used as an etch mask during wet isotropic etching of an underlying layer.

Abstract: A method for forming a T-shape gate having a length below 0.25 .mu.m for use in ultra-frequency semiconductor devices is disclosed. The insulating layer is side-etched by using the gate mask pattern through a conventional photolithography, the length of the insulating layer being controlled by the side-etching. The length of the insulating layer determines the length of the T-shape gate for allowing the T-shape gate having the length below 0.25 .mu.m to be obtained.

Abstract: A method of fabricating an electrically conductive plug on a semiconductor workpiece. A dielectric layer is deposited on the workpiece, and a cavity is etched in the dielectric. An etchant-resistant material is deposited on the wall of the cavity adjacent the cavity mouth so as to form an inwardly-extending lateral protrusion, the etchant-resistant material being resistant to etching by at least one etchant substance which etches said electrically conductive material substantially faster than it etches the etchant resistant material. The cavity is filled by an electrically conductive material. In another aspect of the method, the etchant-resistant material can be omitted. Instead, upper and lower portions of the cavity are etched anisotropically and isotropically, respectively, so as to form a lower portion of the cavity that is wider than the upper portion. In a third aspect of the method, a higher density upper layer of dielectric is deposited over a lower density lower layer of dielectric.

Abstract: A method of manufacturing a micromachined reflector antenna onto a substrate firstly etches a reflector aperture surface defining a dish cavity in an oxide layer and secondly rotates a hinge over the reflector aperture surface with the hinge being used as the reflector central feed. The micromachined reflector can be made into an array of reflector antennas and integrated onto a single substrate with front end receiver circuits operating as a high frequency receiver on a chip reduced in size and cost and operating at hundreds of GHz.

Abstract: A method for non-destructively determining the amount of undercutting in a hidden layer of material disposed on a substrate after device patterning by etching. The method involves forming at least two lines of etch resistant material of increasing width over the hidden layer of material of the substrate and inspecting the lines after etching for a given time period to determine how many lines have been removed. The width dimension of the largest removed line corresponds approximately to the amount of undercut for two sides in the hidden layer of material after etching for the given time period.

Abstract: A process is disclosed for fabricating a device with a cavity formed at one end thereof. A body is provided with a depression, and mask layer is applied to the surface of the body and the depression, the mask layer having a lower etch rate than the body. Near the depression, an opening is formed in the mask layer. Starting from the opening, the body is subjected to an isotropic etching process to form the cavity below the mask layer, with the mask layer being essentially preserved and forming in the area of the depression a structure extending into the cavity.

Abstract: Bonding pad structures may be fabricated by forming a layered structure including a first conducting layer and first and second insulating layers on top of a substrate. Openings are etched through the first and second insulating layers, with the openings being wider in the first insulating layer than in the second insulating layer. The etching process may be carried out in two steps, with the second step preferentially isotropically etching the first insulating layer so that the openings are wider in the first insulating layer than in the second insulating layer and a portion of the second insulating layer overhangs the opening above the first insulating layer. Metal is then deposited within the openings and on top of the second insulating layer. An interlocking structure is formed with the conducting material extending underneath of the overhang portions of the second insulating layer. A passivation layer may be formed over the conducting material.

Abstract: A micromachining method is disclosed for forming a suspended micromechanical structure from {111} crystalline silicon. The micromachining method is based on the use of anisotropic dry etching to define lateral features of the structure which are etched down into a {111}-silicon substrate to a first etch depth, thereby forming sidewalls of the structure. The sidewalls are then coated with a protection layer, and the substrate is dry etched to a second etch depth to define a spacing of the structure from the substrate. A selective anisotropic wet etchant (e.g. KOH, EDP, TMAH, NaOH or CsOH) is used to laterally undercut the structure between the first and second etch depths, thereby forming a substantially planar lower surface of the structure along a {111} crystal plane that is parallel to an upper surface of the structure.

Abstract: A semiconductor processing method of forming a contact opening to a substrate includes forming at least one conductive line over the substrate adjacent a substrate contact area to which electrical connection is to be made. A first oxide layer is formed over the substrate to cover at least part of the contact area. A second oxide layer is formed over the first oxide layer and is formed from a different oxide than the first oxide layer. A first etch is conducted over the contact area and through the second oxide layer to a degree sufficient to leave at least a portion of the first oxide layer over the contact area. A second etch is conducted to a degree sufficient to remove substantially all of the first oxide layer left behind and to remove a desired amount of the second oxide layer laterally outwardly of the contact area.

Abstract: An isotropic or partially isotropic etch shrinks lithographically patterned photoresist (211, 212) to yield reduced linewidth patterned photoresist (213, 214) with a buried antireflective coating also acting as an etchstop or a sacrificial layer. The reduced linewidth pattern (213, 214) provide an etch mask for subsequent anisotropic etching of underlying material such as polysilicon (206) or metal or insulator or ferroelectric.

Abstract: A channel layer is formed in a surface of a semiconductor substrate, and a plurality of trenches are formed in the surface of the semiconductor substrate, the trenches being deeper than the channel layer. Then, gate electrodes are formed in the trenches, respectively, after which body layers are formed between the trenches and source layers are formed adjacent to the trenches.