Abstract: A method for fabricating metal lines in multilevel VLSI semiconductor integrated circuit devices is provided so as to reduce parasitic capacitance. An undercutting etching step is performed so as to form trenches underneath the metal lines for accommodating air voids, followed by forming an intra-layer dielectric between the metal lines and into the trenches so as to form air voids underneath the metal lines. As a result, the parasitic capacitance will be decreased.

Abstract: In a method of manufacturing a semiconductor device, to form an opening in an insulation film such as a silicon oxide on a semiconductor substrate in a reverse tapered sectional configuration such that no gap is formed between a side surface of an epitaxial growth layer formed in the opening and the opening in the insulation film, the insulation film having the opening is subjected to a thermal process in an atmosphere of non-oxidizing gas including hydrogen elements such as hydrogen, silane or disilane gas. An opening is formed in the insulation film on the semiconductor substrate using isotropic etching. As a result of the above-described thermal process, decomposition of a silicon oxide proceeds from the interface between the insulation film and the semiconductor substrate at a side-wall of the opening to eventually form the opening in a reverse tapered sectional configuration at least in an edge portion thereof.

Abstract: A method and structure are disclosed related to tapered contact holes in VLSI and ULSI technologies. The contact hole is formed by taking advantage of two-tiered polycide lines formed with a step. The polycide lines with steps are further formed with oxide spacers. The resulting structure is then used to form contact hole in between the oxide spacers. Because the oxide spacers are used--without the need for a tightly toleranced mask--to delimit the area of the contact at the bottom of the hole, a larger area of contact is obtained in addition to the tapered edges that are formed. Polycide is chosen to be a multilayer structure comprising tungsten-silicide (WSi.sub.2) over poly-silicon (poly-Si). Next, polycide is patterned by etching with a recipe which etches the WSi.sub.2 faster than it etches the underlying poly-Si. The etching, therefore, results in a structure where the WSi.sub.2 forms a step over the poly-Si layer.

Abstract: A method of etching an oxide/poly/oxide sandwich structure in which both oxide layers are anisotropically etched, and the poly layer is also isotropically etched to recess the poly from the edge of the contact walls. The oxide etch can be done using oxide to nitride etch stop technology. The process is an in situ etch, that is, a single parallel plate plasma reactor is employed.

Abstract: The chemoresistive gas sensor comprises a heating element integrated in a dedicated SOI substrate having an air gap in the intermediate oxide layer between two wafers of monocrystalline silicon. A sensitive element of tin oxide is formed over the heating element and separated from it by a dielectric insulating and protective layer. A trench formed at the end of the fabrication of the device, extends from the surface of the wafer in which the heating element is integrated, up to the air gap to mechanically separate and insulate the sensitive element from the rest of the chip, thereby improving the mechanical characteristics sensitivity and response of the sensor.

Abstract: A semiconductor processing method of forming a contact opening to a substrate includes forming at least one conductive line over the substrate adjacent a substrate contact area to which electrical connection is to be made. A first oxide layer is formed over the substrate to cover at least part of the contact area. A second oxide layer is formed over the first oxide layer and is formed from a different oxide than the first oxide layer. A first etch is conducted over the contact area and through the second oxide layer to a degree sufficient to leave at least a portion of the first oxide layer over the contact area. A second etch is conducted to a degree sufficient to remove substantially all of the first oxide layer left behind and to remove a desired amount of the second oxide layer laterally outwardly of the contact area.

Abstract: A single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independently of crystal orientation.

Abstract: A method of manufacturing a semiconductor device is disclosed in which semiconductor switching elements (2) and an integrated microcomponent (3) with a fixed electrode (6) and an electrode (7) which is movable relative to the fixed electrode (6) are provided adjacent a surface of a semiconductor slice (1), which slice (1) is subsequently subdivided into individual semiconductor devices. After the semiconductor switching elements (2) have been provided, metal conductor tracks (20) of a first level are provided on the surface which form the fixed electrode (6) and electrical connections (9), over which an insulating layer (21) and metal conductor tracks (22) of a second level are provided, which form the movable electrode (7) and further electrical connections (8), after which the insulating layer (21) between the fixed (6) and the movable electrode (7) is removed.

Abstract: This is a method of fabricating a heterojunction bipolar transistor on a wafer. The method can comprise: forming a doped subcollector layer 31 on a semiconducting substrate 30; forming a doped collector layer 32 on top of the collector layer, the collector layer doped same conductivity type as the subcollector layer; forming a doped base epilayer 34 on top of the collector layer, the base epilayer doped conductivity type opposite of the collector layer; forming a doped emitter epilayer 36, the emitter epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming a doped emitter cap layer 37 on top of the emitter epilayer, the emitter cap layer doped same conductivity as the emitter epilayer; forming an emitter contact 38 on top of the emitter cap layer; forming a base contact on top of the base layer; forming a collector contact on top of the collector layer; and selective etching the collector layer to produce an undercut 45 beneath the base layer.

Abstract: A method of manufacturing a semiconductor component includes sputtering a first metal layer (16) over a substrate (11), sputtering a second metal layer (17) over the first metal layer (16), selectively etching the second metal layer (17) versus the first metal layer (16), selectively etching the first metal layer (16) versus the second metal layer (17), and thereafter, selectively re-etching the second metal layer (17) versus the first metal layer (16).

Abstract: A motion sensor including a sensing wafer with a bulk micromachined sensing element, and a capping wafer on which is formed the conditioning circuitry for the sensor. The sensing and capping wafers are configured such that, when bonded together, the capping wafer encloses the sensing element to form a monolithic sensor. The capping wafer is further configured to expose bond pads on the sensing wafer, and to enable singulation of the two-wafer stack into individual dies. Wire bonds can be made to both wafers, such that the sensor can be packaged in essentially any way desired.

Abstract: A method of fabricating semiconductor devices with a passivated surface includes providing a contact layer on a substrate so as to define an inter-electrode surface area. A first layer and an insulating layer, which are selectively etchable relative to each other and to the substrate and the contact layer, are deposited on the contact layer and the inter-electrode surface area. The insulating layer and the first layer are individually and selectively etched to define an electrode contact area and to expose the inter-electrode surface area. The exposed inter-electrode surface area is passivated, either subsequent to or during the etching of the first layer. A metal contact is formed in the electrode contact area in abutting engagement with the insulating layer so as to seal the inter-electrode surface area.

Abstract: This invention relates to the area of microelectromechanical systems in which electronic circuits and mechanical devices are integrated on the same silicon chip. The method taught herein allows the fabrication of thin film structures in excess of 150 microns in height using thin film deposition processes. Wafers may be employed as reusable molds for efficient production of such structures.

Abstract: A method for fabricating a dynamic random access memory comprises the steps of forming a diffusion region in a semiconductor substrate, providing an insulation layer on the semiconductor substrate, forming a contact hole in the insulation layer to expose the diffusion region at the contact hole, depositing a semiconductor layer on the insulation layer in the amorphous state such that the semiconductor layer establishes an intimate contact with the exposed diffusion region via the contact hole, patterning the semiconductor layer to form a capacitor electrode, depositing a dielectric film on the capacitor electrode such that said dielectric film covers the capacitor electrode; and depositing a semiconductor material to form an opposing electrode such that the opposing electrode buries the capacitor electrode underneath while establishing an intimate contact with the dielectric film that covers the capacitor electrode.

Abstract: A semiconductor device is made up of a substrate having a top surface, and a fin type capacitor having a first electrode including a first part which extends upwards from the substrate and a second part which extends approximately parallel to the top surface of the substrate from the first part. The second part is made up of at least one conductor layer.

Abstract: A manufacturing method for a dynamic RAM containing a screen-type structure cylindrical stack cell capacitor. An SiO.sub.2 layer 22 is formed on a polysilicon layer 11 (or a semiconductor substrate 1) to serve as a preform or spacer. A nitride layer 31 is stacked on this SiO.sub.2 layer, and nitride layer 31 and SiO.sub.2 layer 22 are worked into virtually the same pattern. Then the outside surface of SiO.sub.2 layer 22 is etched using nitride layer 31 as a mask, causing the nitride layer 31 to form a lateral projection structure 31A in the region removed by the etching. A polysilicon layer 23 is adhered to the top of silicon layer 11, which serves as a capacitor lower electrode, from the top of nitride layer 31 and SiO.sub.2 layer 22, including this projected portion. Polysilicon layer 23 is etched to leave a portion of polysilicon layer 23 on the outside surface of SiO.sub.2 layer 22 directly beneath the projecting portion 31A of nitride layer 31.

Abstract: A method is described for manufacturing a miniaturized accelerometer having a narrow bandwidth and behaving as a switch sensitive only to low frequencies such as are contained in earthquakes. The method includes provision of an unbalanced see-saw beam assembly composed of beams 2 and masses 3 at opposite ends of the beams 2. The beams 2 have their suspension at a location with slightly different distances from the masses 3 along a line parallel to and vertically offset from the line connecting centers of gravity of the masses 3.

Abstract: A CMOS-technology, DRAM integrated circuit includes paired P-type and N-type wells in a substrate, which wells are fabricated using a self-aligning methodology. Similarly, FET's of the DRAM circuit are fabricated in the wells of the substrate using a self-aligning methodology to provide FET's of opposite polarity in a DRAM which may have paired memory cells and dummy cells for symmetry of circuitry. The DRAM includes a multitude of annular multi-plate capacitor structures formed atop the FET's of the substrate, and plural layers of insulative dielectric with embedded bit and word traces providing for connection of the multitude of memory cells of the DRAM to external circuitry.

Abstract: An MISFET type semiconductor sensor, which can avoid deterioration of characteristics, and a method for fabricating same are disclosed. Silicon oxide films and a silicon nitride film are formed on an upper surface of a p-type silicon substrate, and a movable portion is disposed above the silicon nitride film with a predetermined interval interposed therebetween. A movable gate electrode portion exists on a portion of the movable portion and is displaced by acceleration. Fixed electrodes (a source/drain portion) composed of an impurity diffusion layer are formed on the p-type silicon substrate, and a flowing current changes due to a change in a relative position with the movable gate electrode portion due to acceleration. Projections for movable-range restriction use are provided on a lower surface of the movable portion other than the movable gate electrode portion, and form a gap which is narrower than a gap between the p-type silicon substrate and movable gate electrode portion.

Abstract: A bridging member extending across a cavity in a semiconductor substrate (e.g. single crystal silicon) has successive layers--a masking layer, an electrically conductive layer (e.g. polysilicon) and an insulating layer (e.g. SiO.sub.2). A first electrical contact (e.g. gold coated with ruthenium) extends on the insulating layer in a direction perpendicular to the extension of the bridging member across the cavity. A pair of bumps (e.g. gold) are on the insulating layer each between the contact and one of the cavity ends. Initially the bridging member and then the contact and the bumps are formed on the substrate and then the cavity is etched in the substrate through holes in the bridging member. A pair of second electrical contacts (e.g. gold coated with ruthenium) are on the surface of an insulating substrate (e.g. pyrex glass) adjacent the semiconductor substrate. The two substrates are bonded after the contacts are cleaned.

Abstract: A method for manufacturing sensors from a multilayer plate with upper and lower monocrystalline silicon layers and an etching layer between them. The upper silicon layer is structured by the introduction of troughs therein extending down to the etching layer. Sensor structures, such as a bending beam that is used in an acceleration sensor, are created by etching the etching layer beneath a part of the silicon layer structured in this manner.