Abstract: Because of environmental pollution prevention laws, PFC (perfluorocarbon) and HFC (hydrofluorocarbon), both etching gases for silicon oxide and silicon nitride films, are expected to be subjected to limited use or become difficult to obtain in the future. An etching gas containing fluorine atoms is introduced into a plasma chamber. In a region where plasma etching takes place, the fluorine-containing gas plasma is made to react with solid-state carbon in order to produce molecular chemical species such as CF4, CF2, CF3 and C2F4 for etching. This method assures a high etch rate and high selectivity while keeping a process window wide.

Abstract: The present invention provides a manufacturing method of a semiconductor device including the steps of: forming a silicon nitride film on a semiconductor substrate and forming a CVD silicon oxide film on the silicon nitride film, patterning the silicon nitride film and the CVD silicon oxide film using a resist mask, forming a trench by etching the semiconductor substrate by using the patterned silicon nitride film and the patterned CVD silicon oxide film as a mask after releasing the resist mask, and embedding an insulating material into the trench and flattening the embedded insulating material using the silicon nitride film as a stopper, in which the manufacturing method includes a step of annealing the semiconductor substrate after the step of forming the CVD silicon oxide film and before the step of etching the semiconductor substrate.

Abstract: A semiconductor manufacturing process wherein silicon nitride is plasma etched with selectivity to an overlying and/or underlying dielectric layer such as a silicon oxide or low-k material. The etchant gas includes a fluorocarbon reactant and an oxygen reactant, the ratio of the flow rate of the oxygen reactant to that of the fluorocarbon reactant being no greater than 1.5. The etch rate of the silicon nitride can be at least 5 times higher than that of the oxide. Using a combination of CH3F and O2 with optional carrier gasses such as Ar and/or N2, it is possible to obtain nitride:oxide etch rate selectivities of over 40:1. The process is useful for simultaneously removing silicon nitride in 0.25 micron and smaller contact or via openings and wide trenches in forming structures such as damascene and self-aligned structures.

Abstract: An etching gas is supplied into a process chamber and turned into plasma so as to etch a silicon nitride film arranged on a field silicon oxide film on a wafer (w). A mixture gas containing at least CH2F2 gas and O2 gas is used as the etching gas. Parameters for planar uniformity, by which the etching apparatus is set in light of a set value of the planar uniformity, include the process pressure and the mixture ratio (CH2F2/O2) of the mixture gas. As the set value of the planar uniformity is more strict, either one of the process pressure and the mixture ratio is set higher.

Abstract: A method for etching silicon nitride selective to silicon dioxide and silicon (polycrystalline silicon or monocrystalline silicon) comprises the use of oxygen along with an additional etchant of either CHF3 or CH2F2. Flow rates, power, and pressure settings are specified.

Abstract: A method for forming an isolation region on a semiconductor substrate with a high yield, comprising partially covering the surface of a semiconductor substrate with an oxidation inhibitor film, depositing a material for side-wall parts on the oxidation inhibitor film and also on an exposed region of the surface, which is revealed through an opening of the oxidation inhibitor film, to form side-wall parts at the edge portions of the oxidation inhibitor film, then, removing by a plasma etching process the unnecessary portions of said side-wall material deposited on the oxidation inhibitor film and on the exposed region of the substrate and leaving intact the side-wall parts at the edge portions of the oxidation inhibitor film, and cleaning the exposed region on the surface of the semiconductor substrate, revealed through the opening of the oxidation inhibitor film, before subsequent heat treatment to generate a field oxide film.

Abstract: A structure/method for reducing the stress between a dielectric, passivation layer and a metallic structure comprising coating the metallic structure with a low stress modulus buffer material, and forming the dielectric passivation layer covering the low stress modulus buffer material. The low stress modulus buffer material is composed of a layer of a polymeric material selected from at least one of the group consisting of a hydrogen/alkane SQ (SilsesQuioxane) resin, polyimide, and a polymer resin. The dielectric, passivation layer is composed of at least one layer of a material selected from at least one of the group consisting of silicon oxide and silicon nitride. A protective layer is formed over the dielectric, passivation layer. The low stress modulus buffer material has a thermal coefficient of expansion between that of the metallic structure and that of the dielectric passivation layer.

Abstract: A subcritical or supercritical water is used to selectively etch a silicon nitride film against a silicon dioxide film or to selectively etch a silicon dioxide film against a crystalline silicon region. This method is applicable to a process of forming a MISFET or a charge emitting device.

Abstract: The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first material. An imagable material is formed on the second material, and patterned. A pattern is then transferred from the patterned imagable material to the first and second materials. The invention also includes a structure comprising a first layer of silicon nitride over a substrate, and a second layer on the first layer. The second layer comprises silicon and is free of nitrogen. The structure further comprises a third layer consisting essentially of imagable material on the second layer.

Abstract: A process and etchant gas composition for anisotropically etching a trench in a silicon nitride layer of a multilayer structure. The etchant gas composition has an etchant gas including a polymerizing agent, a hydrogen source, an oxidant, and a noble gas diluent. The oxidant preferably includes a carbon-containing oxidant component and an oxidant-noble gas component. The fluorocarbon gas is selected from CF4, C2F6, and C3F8; the hydrogen source is selected from CHF3, CH2F2, CH3F, and H2; the oxidant is selected from CO, CO2, and O2; and the noble gas diluent is selected from He, Ar, and Ne. The constituents are added in amounts to achieve an etchant gas having a high nitride selectivity to silicon oxide and photoresist. A power source, such as an RF power source, is applied to the structure to control the directionality of the high density plasma formed by exciting the etchant gas.

Abstract: A method for forming sidewall spacers with square shoulders on polysilicon gates and the structure formed by the method are disclosed. In the method, a polysilicon gate is first formed on a silicon substrate wherein the gate has a silicon nitride pad on top. A conformal silicon nitride layer is then blanket deposited on top of the structure followed by the deposition of a silicon oxide layer on top of the conformal silicon nitride layer. The silicon oxide layer is then planarized until a top of the conformal silicon nitride layer is exposed. The conformal silicon nitride layer and the silicon nitride pad are then wet etched away to expose the polysilicon gate by using the silicon oxide layer as a mask. After a photoresist layer is coated and etched-back such that only a cavity formed by the silicon oxide layer, the polysilicon gate and the conformal silicon nitride layer is filled with the photoresist, the silicon oxide layer is wet etched away by an etchant such as HF.

Abstract: A method of manufacturing a cylindrical storage node in a semiconductor device, in which loss differences of the cylindrical storage node between the center and the edge of cell areas, caused by an etch-back process of storage node isolation, is minimized, thereby maintaining uniform electrical capacitances over the entire area of a semiconductor wafer.

Abstract: Disclosed is a novel method for fabricating a stencil mask comprising the formation of an absorber pattern, including an alignment key or target, on the topside of an SOI wafer having a transparent buried insulating layer. The formation of the absorber pattern is followed by the formation of an alignment window from the backside of the SOI wafer using the insulating layer as a lens. The alignment window allows the alignment between the absorber pattern and the frame pattern to be verified, using light passing through the window lens and illuminating the alignment key, before initiating the frame etch, thereby improving the quality and/or throughput of the stencil mask manufacturing process.

Abstract: Borderless contacts are used in integrated circuits in order to conserve chip real estate. As part of the process for manufacturing borderless contacts, an etch-stopping layer of silicon nitride is first laid over the area that is to be contacted. Investigation has now shown that this can lead to damage to the silicon at the edges of the via. The present invention eliminates this damage by introducing a buffer layer between the silicon surface and said sidon nitride layer. Suitable materials for the buffer layer that have been found to be infective include silicon oxide and silicon oxynitride with the latter offering some ditional advantages over the former. Experimental data confirming the effectiveness of the buffer layer are provided, together with a process for its manufacture.

Abstract: Methods for removing a silicon-oxy-nitride layer and wafer surface cleaning are disclosed. The method for removing a silicon-oxy-nitride layer utilizes a solution of ethylene glycol and hydrogen fluoride to completely remove the silicon-oxy-nitride layer from a substrate. Moreover, the method for wafer surface cleaning also uses a solution of ethylene glycol and hydrogen fluoride to remove chemical oxide or native oxide from wafer surfaces and an ethylene glycol solvent to rinse the wafer surfaces.

Abstract: Improved methods and apparatus for chemically assisted etch processing in a plasma processing system are disclosed. In accordance with one aspect of the invention, improved techniques suitable for performing an etch process in the plasma processing can be realized. The invention operates to reduce the critical dimension bias that is associated with the etch process. Lower critical dimension bias provides many benefits. One such benefit is that features with higher aspect ratio can be etched correctly. In addition, several other undesired effects, e.g., micro loading, bowing and passivation, can be curtailed using the techniques of the present invention.

Abstract: A process for fabricating a semiconductor device using an ARC layer includes the formation of a silicon-rich silicon nitride material to provide an anti-reflective layer over a electrically conductive or semiconductor surface. The silicon-rich silicon nitride material is plasma deposited to provide a material having a desired refractive index, thickness uniformity, and density. The process includes the formation of a device layer on a semiconductor substrate. The device layer includes at least a silicon layer and a silicon oxide layer. A silicon-rich silicon nitride layer is formed to overlie the device layer. The silicon-rich silicon nitride material can be selectively etched, such that the silicon material and the silicon oxide material in the underlying device layer are not substantially etched.

Abstract: An oxide etching process, particularly useful for selectively etching oxide over a feature having a non-oxide composition, such as silicon nitride and especially when that feature has a corner that is prone to faceting during the oxide etch. The invention uses one of three hydrogen-free fluorocarbons having a low F/C ratio, specifically hexafluorobutadiene (C4F6), hexafluorocyclobutene (C4F6), and hexafluorobenzene (C6F6). At least hexafluorobutadiene has a boiling point below 10° C. and is commercially available. The fluorocarbon together with a substantial amount of a noble gas such as argon is excited into a high-density plasma in a reactor which inductively couples plasma source power into the chamber and RF biases the pedestal electrode supporting the wafer. Preferably, one of two two-step etch process is used. In the first, the source and bias power are reduced towards the end of the etch.

Abstract: An integrated in situ oxide etch process particularly useful for a counterbore dual-damascene structure over copper having in one inter-layer dielectric level a lower nitride stop layer, a lower oxide dielectric, a lower nitride stop layer, an upper oxide dielectric layer, and an anti-reflective coating (ARC). The process is divided into a counterbore etch and a trench etch with photolithography for each, and each step is preferably performed in a high-density plasma reactor having an inductively coupled plasma source primarily generating the plasma and a capacitively coupled pedestal supporting the wafer and producing the bias power. The counterbore etch preferably includes at least four substeps of opening the ARC, etching through the upper oxide and nitride layers, selectively etching the lower oxide layer but stopping on the lower nitride layer, and a post-etch treatment for removing residue.

Abstract: A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact region beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. There is then etched the silicon oxide layer while employing a reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) an etched silicon oxide layer which exposes the contact region without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the etched silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer while employing a downstream plasma etch method employing a second etchant gas composition comprising a fluorocarbon etchant gas and oxygen.

Abstract: A method for making an integrated circuit preferably includes the steps of: forming a trench laterally adjacent an active region in a semiconductor substrate; forming a dielectric layer on the semiconductor substrate filling the trench and covering the active area; selectively etching the dielectric layer to remove at least a portion of the dielectric layer overlying the active region and to define a recess within the dielectric layer filling the trench to serve as an alignment mark; and polishing the selectively etched dielectric layer and leaving the alignment mark. The method may also include forming an optically opaque layer adjacent the polished dielectric layer and with the alignment mark causing a repeated alignment mark in the optically opaque layer. The alignment mark and/or repeated alignment mark may be used for alignment in a subsequent processing step.

Abstract: A plasma etch process, particularly applicable to an self-aligned contact etch in a high-density plasma for selectively etching oxide over nitride, although selectivity to silicon is also achieved. In the process, a fluoropropane or a fluoropropylene is a principal etching gas in the presence of a substantial amount of an inactive gas such as argon. Good nitride selectivity has been achieved with hexafluoropropylene (C3F6), octafluoropropane (C3F8), heptafluoropropane (C3HF7), hexafluoropropane (C3H2F6). The process may use one or more of the these gases in proportions to optimize selectivity and a wide process window. Difluoromethane (CH2F2) or other fluorocarbons may be combined with the above gases, particularly with C3F6 for optimum selectivity over other materials without the occurrence of etch stop in narrow contact holes and with a wide process window.

Abstract: An SiN film is formed by applying a thermal nitridation process to a surface of a Si substrate to form a first SiN film and then forming a second SiN film on the first SIN film by conducting a CVD process that uses SiCl4 and an ammoniac gas, wherein the CVD process is conducted at a temperature in the range of 550-660° C.

Abstract: A technique for forming a borderless transistor gate and source/drain region contact structure which provides an on-chip area efficient layout and connection between the device gate layer and an associated source/drain region that can also overlap adjoining isolation structures. In a representative embodiment, this may be effectuated through the overlapping of one portion of the contact region over the edge of the gate polysilicon layer and another part of the contact over the source/drain diffusion. The structure and process of the present invention provides a desirable size reduction in the contact for given design rule dimensions and the resultant contact structure is inherently “self-aligned” to both the gate polysilicon layer and the isolation region in that the contact has no need for an interstitial space between it and the gate polysilicon or isolation regions to prevent unintended electrical connections.

Abstract: A semiconductor processing method is provided for making contact openings. It includes depositing several insulative layers and performing an anisotropic etch. One layer is a conformal oxide covering the contact area and adjacent structures. A second layer is a breadloafed oxide deposited over the contact area and adjacent structures. A third layer is a doped oxide deposited over the two lower layers. The anisotropic etch is performed through the oxide layers to the contact area located on a lower substrate. The etch is selectively more rapid in the third oxide than in the two other oxides. The breadloafed oxide provides additional protection and reduces the risk of etch-through to conductive structures adjacent the contact area. An alternate embodiment replaces the two lowest oxide layers by a breadloafed nitride layer. In this embodiment, the anisotropic etch is selectively more rapid in oxides than in nitrides.

Abstract: An integrated self aligned contact process includes oxide etch with high oxide etch rate, integrated selective oxide etch and nitride liner removal with high selectivity to corner nitride with the ability to remove the bottom nitride liner, and stripping of all polymer and photoresist. C4F8 and CH2F2 are used for the high selectivity oxide etch step. The unique behavior of CH2F2 in high density plasma allows polymer protection to form on the nitride corner/sidewall while at the same time etching the bottom nitride.

Abstract: A method and apparatus for improving the accuracy of a contact to an underlying layer comprises the steps of forming a first photoresist layer over the underlying layer, forming a mask layer over the first photoresist layer, then forming a patterned second photoresist layer over the mask layer. The mask layer is patterned using the second photoresist layer as a pattern then the first photoresist layer is patterned using the mask layer as a pattern. A tapered hole is formed in the first photoresist layer, for example using an anisotropic etch. The tapered hole has a bottom proximate the underlying layer and a top distal the underlying layer with the top of the hole being wider than the bottom of the hole.

Abstract: In a semiconductor memory having a cylindrical storage electrode which is electrically connected to a semiconductor substrate through a contact hole formed to penetrate through an insulating film formed on the semiconductor substrate, the cylindrical storage electrode has a horizontal fin formed integrally with the cylindrical storage electrode and to extend inwardly from an inner surface of the cylindrical storage electrode to form an annular ring extending along the inner circumference of the cylindrical storage electrode one turn. A dielectric film is formed to cover a surface of the cylindrical storage electrode including the surface of the horizontal fin, and is covered with a plate electrode. Thus, the cylindrical storage electrode has an increased effective surface area even if the area per memory cell is reduced. Accordingly, a necessary storage capacitance can be obtained with an increased integration density.

Abstract: A method for depositing a sacrificial oxide for fabricating a semiconductor device includes preparing p-doped silicon regions on a semiconductor wafer for depositing a sacrificial oxide on the p-doped silicon regions. The method also includes the step of placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the p-doped silicon regions to form a sacrificial oxide on the p-doped silicon regions when a potential difference is provided between the wafer and the solution. Processing the wafer using the sacrificial oxide layer is also included.

Abstract: To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.

Abstract: A method to improve silicon oxynitride when used as an etching stop for silicon oxide plasma etching, by nitridizing with a nitrogen plasma, in the fabrication of an integrated circuit is achieved. The method is applied to forming etch stopping silicon oxynitride spacers for MOS transistors and for forming etch stopping silicon oxynitride for dual damascene interconnects. A semiconductor substrate is provided wherein devices and features have been formed in and on the semiconductor substrate. A silicon oxynitride layer is deposited overlying the semiconductor substrate. The silicon oxynitride layer is nitridized. An interlevel dielectric oxide layer is deposited overlying surface of the silicon oxynitride layer. The interlevel dielectric oxide layer is etched through to the silicon oxynitride layer where defined by photolithography and wherein the silicon oxynitride layer acts as an etching stop.

Abstract: Method and apparatus for plasma etching both metal and inorganic dielectric layers in a single chamber during deep sub-micron semiconductor fabrication. Fluorine based chemistries, or a mixture of fluorine and chlorine based chemistries, are used to etch the inorganic dielectric layer. A switch is then made to chlorine based chemistries, within the same etching chamber, which are utilized to etch the metal layer. Overetching may also be performed with chlorine based chemistries to clear any residuals.

Abstract: A process for controlling the etch of a silicon dioxide layer at a high etch rate and high selectivity with respect to silicon nitride, particularly in a multilayer structure, by maintaining various portions of the etch chamber at elevated temperatures.

Abstract: A method for fabricating an interconnect structure by a dual damascene process is described, in which a first low dielectric constant material is formed on a substrate, followed by forming a gradient silicon oxy-nitride layer on the first low dielectric constant. A second low dielectric constant layer is further formed on the gradient silicon oxy-nitride layer. A trench line is then formed in the second low dielectric constant material using the gradient silicon oxy-nitride layer as an etch-stop, followed by forming a via under the trench line.

Abstract: A method of fabricating an integrated circuit, and an integrated circuit so fabricated, is disclosed. A silicon dioxide layer (14) that is doped with both boron and phosphorous, typically referred to as BPSG, is used as a planarizing layer in the integrated circuit structure, above which conductive structures (46, 52, 54) are disposed. A silicon nitride layer (30) is in place below the BPSG layer (14), and serves as a barrier to the diffusion of boron and phosphorous from the BPSG layer (14) during high temperature processes such as reflow and densification of the BPSG layer (14) itself. Contact openings (PC, BLC, CT) are etched through the BPSG layer (14) and the silicon nitride layer (30) using a two-step etch process.

Abstract: A method for use in the fabrication of semiconductor devices includes forming a titanium nitride film and depositing a silicon hard mask over the titanium nitride film. The silicon hard mask is used to pattern a titanium nitride interconnect from the titanium nitride film and the silicon hard mask is also used as a contact etch stop for forming a contact area. In forming the interconnect, the silicon hard mask is dry etched stopping selectively on and exposing portions of the titanium nitride film and the exposed portions of the titanium nitride film are etched resulting in the titanium nitride interconnect. In using the silicon hard mask as a contact etch stop, an insulating layer is deposited over the silicon hard mask and the insulating layer is etched using the silicon hard mask as an etch stop to form the contact area. The silicon hard mask is then converted to a metal silicide contact area. Interconnects formed using the method are also described.

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first film over a semicondutor substrate, introducing a reaction gas including a dilution gas into a reaction atmosphere and then growing a antireflection film made of silicon nitride or silicon nitride oxide on the first film by a plasma chemical vapor deposition method in the reaction atmosphere, coating resist on the antireflection film directly or via a second film and then patterning the resist via exposure and development, patterning the first film located in an area not covered with the resist by etching, and removing the antireflection film by use of hydrofluoric acid after patterning of the first film, whereby expansion of impurity diffusion can be prevented and also retreat of sidewalls can be suppressed.

Abstract: A method for improving trench isolation is disclosed. A trench is etched into the substrate by using a photo mask. A bottom oxide layer, a sidewall oxide layer and a polycrystalline silicon layer are deposited into the trench and over the wafer, and are etched to clear from the surface, then over-etched till a recess is formed within the trench. Thereafter, an oxide etch step is applied to remove a certain thickness of the sidewall oxide layer in order to expose the polycrystalline silicon edge in the opening of the trench. Then, an oxidation step is utilized to form a capping oxide layer on top of the recess by oxidizing the top and the exposed edge of the polycrystalline silicon film in the trench so that a uniform plug edge can be achieved inside the trench to prevent stress problem induced by a wedge shaped oxide growing in the space between the plug and the substrate.

Abstract: A method for fabricating and patterning semiconductor devices with a resolution down to 0.12 &mgr;m on a substrate structure. The method begins by providing a substrate structure comprising various layers of oxide and/or nitride formed over either monocrystalline silicon or polycrystalline silicon. A silicon oxynitride layer is formed on the substrate structure. Key characteristics of the oxynitride layer include: a refractive index of between about 1.85 and 2.35 at a wavelength of 248 nm, an extinction coefficient of between 0.45 and 0.75 at a wavelength of 248 nm, and a thickness of between about 130 Angstroms and 850 Angstroms. A photoresist layer is formed over the silicon oxynitride layer and exposed at a wavelength of between about 245 nm and 250 nm; whereby during exposure at a wavelength of between 245 nm 250 nm, the silicon oxynitride layer provides a phase-cancel effect.

Abstract: Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a layer of highly absorbing silicon rich nitride to serve as a hardmask between a semiconductor substrate and a photoresist. The highly absorbing layer of silicon rich nitride has an extinction coefficient (k)>0.5. As reflected light passes through the layer of silicon rich nitride, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photolithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the silicon rich nitride in accordance with the pattern formed on the photoresist.

Abstract: A semiconductor device includes a F-doped interlayer insulation film and a high-refractive index insulation film having a refractive index higher than a refractive index of the F-doped interlayer insulation film, such that the high-refractive index insulation film is disposed at least one of a top side and a bottom side of the F-doped interlayer insulation film.

Abstract: Sidewall spacers, adjacent a gate electrode and source/drain regions of a MOS transistor are formed of a dielectric material that can be completely or partially removed to “lift-off” silicide stringers if formed. After silicide stringer removal, a dielectric layer, having a first portion and second portion that are selectively etchable with respect to one another, is deposited. A gate contact opening is formed in the dielectric layer where the opening is essentially the same dimension as the gate length. Alignment of the opening to the gate electrode is buffered by the thickness of the first portion of the dielectric layer, adjacent sidewalls of the gate electrode.

Abstract: A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N—H bonds, O—H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing the NH3 flow, decreasing the SiH4 flow, decreasing the nitrogen flow, or all three, in a standard PECVD silicon nitride fabrication process. The etch stop can alternatively be made by pulsing the RF field in either a PECVD process or an LPCVD process.

Abstract: The poor uniformity of Interlevel Dielectric Deposition (ILD) thickness for High Aspect Ratio (HAR) contact after Chemical Mechanical Planarization (CMP) will cause serious underlayer loss due to the longer over-etching time that is required to compensate for thickness differences within the wafer. Prior Art uses 1.5K Plasma Enhanced Tetra-Ethyl-Ortho-Silicate (PETEOS) to serve as a stop layer and thus reduce underlayer loss. The present invention teaches using a non-silicon oxide containing SiN/SiON or Si3N4/SiON as a stop layer. The present invention therefore is aimed at reducing underlayer loss and thereby improving the uniformity of the underlayer thickness upon completion of the hole etching process. Concurrently, the over-etch time can be reduced to less than 10% of the time required for Prior Art contact hole etching.

Abstract: A method of forming a PE-CVD silicon nitride spacer having a good profile in the fabrication of a self-aligned contact wherein a two-step etching process forms the spacer is described. Semiconductor device structures are formed on a semiconductor substrate. A layer of silicon nitride is deposited by plasma-enhanced chemical vapor deposition over the surface of the substrate and overlying the semiconductor device structures. The silicon nitride layer is etched away using a two-step etching process to leave silicon nitride spacers on the side surfaces of the semiconductor device structures. The two-step process comprises a first etching away of 70% of the silicon nitride layer using Cl2/He chemistry and a second etching away of the remaining silicon nitride on top surface of the semiconductor device strucutures using SF6/CHF3/He chemistry.

Abstract: In a method for manufacturing a semiconductor device, an insulating layer is formed on a refractory metal layer, and a contact hole in the insulating layer by a dry etching process using an etching gas. The etching gas includes one of: a mixture gas of fluorocarbon and hydrogen; a mixture gas of hydrofluorocarbon and hydrogen; a gas of hydrofluorocarbon; and a fluorocarbon gas except for CF4.

Abstract: A method for forming the gate electrode in an integrated circuit, in which a cap silicon nitride layer is deposited in a two step process to improve the condition of silicon nitride residue remaining on the surface of tungsten silicide. First, a layer of polysilicon and a layer of tungsten silicide are sequentially formed on the semiconductor substrate, subsequently, a thin film of silicon nitride is formed at a first temperature and a second silicon nitride is formed at a second temperature, then the pattern of the contact window of gate is defined and the first etching is performed to remove the second and the second silicon nitride, finally, the second etching is performed to remove the layers of polysilicon and tungsten silicide to form a gate electrode.

Abstract: A dynamic random access memory (DRAM) cell storage node and a fabricating method thereof are provided. A storage contact plug 118 is formed in a first insulating layer 104 on a semiconductor substrate. A second insulating layer 110, a material layer 112, and a third insulating layer 114 are sequentially formed on the first insulating layer. The material layer prevents etchant of the third insulating layer from attacking the second insulating layer. The third insulating layer, the material layer, and the second insulating layer are sequentially etched to form an opening exposing the storage contact plug and a portion of the surface of the first insulating layer. The opening is filled with a conductive layer to form a storage node 116. The third insulating layer is etched until the top surface of the material layer is exposed, and the material layer is etched until the top surface of the second insulating layer is exposed.

Abstract: A method for manufacturing integrated circuit apparatuses; particularly, 1) a method for removing barrier material that lies between copper conductors in damascene interconnections, and 2) a method for removing a thin layer of silicon nitride material that has been intentionally un-etched during the formation of trenches and vias in damascene interconnect dielectric and thereby not exposing copper metal.

Abstract: In a method for preparing a semiconductor device wherein a first silicon oxide film, a second silicon oxide film and a silicon nitride film are sequentially deposited on a silicon substrate, and both silicon oxide films and the silicon nitride film are patterned, a patterned resist 45 is formed on the silicon nitride film, the silicon nitride film is etched with phosphoric acid the resist serving as a mask, and both silicon oxide films are etched with hydrofluoric acid the resist serving as a mask.