Abstract: A plasma etch process is described for the etching of oxide with a high selectivity to nitride, including nitride formed on uneven surfaces of a substrate, e.g., on sidewalls of steps on an integrated circuit structure. The addition of one or more hydrogen-containing gases, preferably one or more hydrofluorocarbon gases, to one or more fluorine-substituted hydrocarbon etch gases and a scavenger for fluorine, in a plasma etch process for etching oxide in preference to nitride, results in a high selectivity to nitride which is preserved regardless of the topography of the nitride portions of the substrate surface. In a preferred embodiment, one or more oxygen-bearing gases are also added to reduce the overall rate of polymer deposition on the chamber surfaces and on the surfaces to be etched, which can otherwise reduce the etch rate and cause excessive polymer deposition on the chamber surfaces. The fluorine scavenger is preferably an electrically grounded silicon electrode associated with the plasma.

Abstract: A practical photolithographic process for use in manufacturing isolation structures in semiconductor substrates at the 0.18 &mgr;m scale uses an inorganic anti-reflective coating (ARC) layer, particularly silicon oxynitride, under a silicon nitride mask layer to minimize substrate reflectivity. The same ARC layer increases latitude in process conditions in photolithographic patterning of both a first mask layer and a second planarization mask level. The silicon oxynitride layer additionally reduces edge/corner stress in isolation structures, improving gate oxide integrity in the device of which the isolation structure forms a part. Furthermore, because silicon oxynitride and silicon nitride respond to the same process conditions, a silicon oxynitride ARC layer can be introduced without increasing process complexity.

Abstract: A method for forming a high aspect ration (HAR>4:1) borderless contact hole is described. The method forms a contact/via hole in the silicon oxide layer by performing an etching process with an etchant, C4F8/C2F6,/Ar/CO or C4F8/Ar/CO, on an etcher. The etcher includes a ring, a roof, a chiller and a chamber. The etchant used in the etching process is controlled under conditions including a C4F8 flow of about 10 to 20 sccm, a CO flow of about 1 to 100 sccm, and an Ar flow of about 100 to 500 sccm. The flow of C2F6 is about 0.5 to 1.5 times that of C4F8. The conditions of the etcher include a roof temperature of about 150 to 300° C., a chiller temperature of about −20 to 20° C., a wall temperature of about 150 to 400° C., a ring temperature of about 150 to 400° C., and a pressure within the chamber of about 4 to 50 mtorr. By controlling the chamber pressure and the deposition rate of the polymer molecules, a properly profiled contact hole is obtained.

Abstract: A plasma etch process is described for the etching of oxide with a high selectivity to nitride, including nitride formed on uneven surfaces of a substrate, e.g., on sidewalls of steps on an integrated circuit structure. The addition of a hydrogen-bearing gas to C4F8 or C2F6 etch gases and a scavenger for fluorine, in a plasma etch process for etching oxide in preference to nitride, results in a high selectivity to nitride which is preserved regardless of the topography of the nitride portions of the substrate surface.

Abstract: A method for forming square shape images in a lithographic process is disclosed wherein a first plurality of lines running in a first direction is defined in a first, usually sacrificial, layer, and then a second resist is defined wherein the lines run in an intersecting pattern to those of the first layer, thereby creating cornered images wherever the first and second layer intersect and in the open areas between the lines. Methods are proposed for developing the square intersecting areas and the square angle areas defined by the openings. Additionally, a photomask is disclosed in which the length and width of the cornered images are independently patterned using the two-exposure process.

Abstract: A method for forming a contact hole in a silicon oxide layer formed over a silicon nitride layer and a substrate performs an etching process with an etchant, C4F8/Ar or C4F8/C2F6/Ar, on an inductively coupled plasma etcher. The inductively coupled plasma etcher contains a chamber, a ring, and a roof. The etchant used in the etching process is controlled by conditions that include a C4F8 flow of about 10 to 20 sccm, a CO flow of less than about 100 sccm, and an Ar flow of about 50 to 500 sccm. In the meantime, the conditions of the inductively coupled plasma etcher include a roof temperature of about 150 to 300 ° C., a ring temperature of about 150 to 400 ° C., and a pressure within the chamber of about 4 to 50 mtorr. By performing a plasma etching process under the foregoing conditions, a properly profiled contact hole is obtained.

Abstract: An improved photolithography technique is provided whereby the beneficial effects of using an anti-reflective coating may be realized while maintaining critical dimensions in each subsequent step. This improvement is realized by the treatment of the anti-reflective coating with a gaseous plasma or a solution of sulfuric acid and hydrogen peroxide. By treating the anti-reflective coating with gaseous plasma or solution of sulfuric acid and hydrogen peroxide, no “footing” results and the critical dimensions as set by the photoresist mask are preserved to provide an accurately patterned mask for subsequent steps.

Abstract: A process for etching a gate conductor material in the fabrication of MOS transistors is presented. A hard mask layer composed of silicon oxynitride is formed upon a gate conductor layer. The hard mask layer is preferably patterned using a resin layer. The patterned hard mask layer is preferably used to form a patterned gate conductor. The gate conductor is preferably composed of polycrystalline silicon or a silicon-germanium alloy.

Abstract: A method is provided for forming an unlanded via hole that substantially solves both the problems of high resistance and via profile loss due to etching. A patterned conductor layer on a first dielectric layer is provided firstly. A first insulating layer is then formed on the first dielectric layer and the conductor layer. A second dielectric layer is formed on the first insulating layer and subsequently etched back until the conductor layer is exposed. The following procedure is to form a second insulating layer on the second dielectric layer and the conductor layer. A third dielectric layer is formed on the second insulating layer. Thereafter, a patterned photoresist layer is formed on the third dielectric layer. Then the etching process is used to etch the third dielectric layer and the second insulating layer to form an unlanded via hole. Finally, the photoresist layer is removed. The unlanded via hole proposed in according with the present invention produces an unlanded via having a good profile.

Abstract: An Integrated Circuit Design which adds, to the standard conducting lines of the bulk metal layer, a pattern of a support structure which supports subsequent deposition in such a way that it eliminates previously experienced concavity or dishing of the subsequent deposition within areas which have a low density or absence of conducting lines. The dummy pattern enhances the deposition of filler material between conducting lines of the Integrated Circuit such that planarization of the bulk metal results in a smoother surface of the areas of the signal lines of the integrated circuit and within large open areas. Concurrently the present invention provides a means of successfully collecting data that are needed for Damascene processing.

Abstract: A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.

Abstract: A method of fabricating a semiconductor device includes the steps of forming a resist pattern on a conductor layer, exposing the resist pattern to any of a plasma of a rare gas, a plasma of a mixture of a rare gas and a fluorine-containing gas, and a plasma of N.sub.2, and applying a dry etching process to the conductor layer while using the resist pattern as a mask.

Abstract: In one embodiment, the present invention relates to a method of etching silicon nitride disposed over a copper containing layer by etching at least a portion of the silicon nitride using a nitride etch gas mixture comprising from about 5 sccm to about 15 sccm of CHF.sub.3, about 5 sccm to about 15 sccm of nitrogen and about 80 sccm to about 120 sccm of a carrier gas. In another embodiment, the present invention relates to a method of processing a semiconductor substrate comprising silicon nitride disposed over a copper containing layer, involving etching at least a portion of the silicon nitride using a nitride etch gas mixture comprising CHF.sub.3, nitrogen and Ar.

Abstract: The present invention is directed to methods of creating a cavity to contain an interconnect leading to a location within a substrate. The substrate has a first dielectric layer of a first etch rate over the location, and a semiconductor device containing the interconnect. One of the methods includes the steps of: forming a second dielectric layer on the first dielectric layer wherein the second dielectric layer has a second etch rate that is slower than the first etch rate, forming a photoresist layer on the second dielectric layer and etching into the first and second dielectric layers to form the cavity leading to the location. The second dielectric layer acts as a profile guiding layer to form a plug and runner simultaneously in a single etching step while controlling relative size of the plug and runner.

Abstract: A method for fabricating semiconductor devices that allows for the integration of anti-reflective coatings into the fabrication process. A method for removing an inorganic anti-reflective coating is disclosed that includes the step of exposing the layer of inorganic anti-reflective coating to atomic fluorine. An asher is used to generate fluorine atoms from NF.sub.3 precursor gas. The NF.sub.3 precursor gas is mixed with an inert carrier such as helium. In one embodiment, sequential etch steps are performed in an asher so as to sequentially remove both a layer of photoresist and a layer of inorganic anti-reflective coating.

Abstract: A method of forming local interconnects uses a dual damascene process. The process comprises the steps of first providing a substrate, and then forming a first insulating layer over the substrate. Then, a pillar-shaped second insulating layer is formed over the first insulating layer. Thereafter, a first conductive layer is formed over the first insulating layer and the second insulating layer, and then a third insulating layer is formed over the first conductive layer. In the subsequent step, a portion of the third insulating layer and the first conductive layer is polished away using a chemical-mechanical polishing operation, stopping at the surface of the second insulating layer. Next, a fourth insulating layer is formed over the third insulating layer, the second insulating layer and the first conductive layer, wherein the fourth insulating layer and the second insulating layer are made from the same material.

Abstract: A process for reducing dimensions of circuit elements in a semiconductor device. The process reduces feature sizes by using an intermediate etchable mask layer between a photo-resistive mask and a layer to be etched. The etchable mask layer below the photo-resistive mask is etched and portions remain which undercut the pattern on the photo-resistive mask. After removing the photo-resistive mask, the remaining mask portions are then used to mask the layer to be etched. By undercutting the photo-resistive mask, the mask portions form a pattern having features with widths that are less than widths of features in the photo-resistive mask. The layer to be etched can then be etched to provide circuit elements with reduced dimensions.

Abstract: A gate electrode of a MOS transistor wherein gate oxide 12 is placed over substrate 10. Boron-doped polysilicon gate electrode 14 is placed over gate oxide 12. Optionally, drain extender implants may be added to substrate 10. Low-temperature-deposited nitride layer 18 is placed over gate electrode 14 and gate oxide 12. The structure then undergoes a sidewall spacer etch to form sidewall spacers 20.

Abstract: To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.

Abstract: A method of forming a plurality of contact holes 70 in a semiconductor wafer uses a single step. The semiconductor wafer includes a dielectric layer 69 overlying a silicon substrate 51, a silicon nitride layer 67a, and a silicon oxynitride layer 63c. First, a photoresist 68 layer is developed on the dielectric layer. Prior to forming the dielectric layer, the silicon oxynitride layer is formed overlying a first conductive layer, and the silicon nitride layer is formed overlying a second conductive layer. Second, an etching step is performed to etch through the silicon oxynitride layer, the silicon nitride layer, a portion of the dielectric layer above the silicon oxynitride layer, and the silicon nitride layer to expose the silicon substrate 51, the first conductive layer 63a, and the second conductive layer 67c. The etching recipe includes a first chemistry and a second chemistry. The first chemistry includes C.sub.2 F.sub.6, C.sub.4 F.sub.8, CH.sub.3 F, and Ar.

Abstract: A method for etching a silicon layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a blanket silicon layer. There is then formed upon the blanket silicon layer a blanket silicon containing hard mask layer, where the blanket silicon containing hard mask layer is formed from a silicon containing material chosen from the group of silicon containing materials consisting of silicon oxide materials, silicon nitride materials, silicon oxynitride materials and composites of silicon oxide materials, silicon nitride materials and silicon oxynitride materials. There is then formed upon the blanket silicon containing hard mask layer a patterned photoresist layer. There is then etched through a first plasma etch method the blanket silicon containing hard mask layer to form a patterned silicon containing hard mask layer while employing the patterned photoresist layer as a first etch mask layer.

Abstract: A method for forming a contact hole in an active matrix substrate, the method comprising steps of: (a) depositing an insulating film covering a first electrode provided on a substrate and the substrate; (b) forming a contact hole by patterning said insulating film by means of dry etching; and (c) forming a second electrode, and contacting the second electrode with the first electrode; wherein in the step (b) after forming a contact hole by dry etching, a surface treatment by plasma etching or reactive ion etching with oxygen gas under a condition in which a pressure P is in a range of 100 Pa to 400 Pa is performed.

Abstract: The present invention intends to form multilayer interconnects without deteriorating the advantage of an organosiloxane film (an interlayer dielectric), i.e., the low dielectric constant. According to the present invention, an organosiloxane film, a silicon nitride film, an inorganic SOG film, and a photoresist pattern are formed on a first metal layer, in series. The inorganic SOG film is then etched with use of the photoresist pattern as a mask to transfer the photoresist pattern to the inorganic SOG film. The photoresist pattern is then removed by oxygen plasma treatment with use of the silicon nitride film as a protection mask for protecting the organosiloxane film. Subsequently thereto, the silicon nitride film and the organosiloxane film are etched with use of the inorganic SOG film to form a contact hole reaching the first metal layer. After removing the inorganic SOG film, a second metal layer is formed to contact with the first metal layer through the contact hole.

Abstract: A process for etching silicon nitride from a multilayer structure which uses an etchant gas including a fluorocarbon gas, a hydrogen source, and a weak oxidant. A power source, such as an RF power source, is applied to the structure to control the directionality of the high density plasma formed by exciting the etchant gas. The power source that controls the directionality of the plasma is decoupled from the power source used to excite the etchant gas. The fluorocarbon gas is selected from CF.sub.4, C.sub.2 F.sub.6, and C.sub.3 F.sub.8 ; the hydrogen source is selected from CH.sub.2 F.sub.2, CH.sub.3 F, and H.sub.2 ; and the weak oxidant is selected from CO, CO.sub.2, and O.sub.2.

Abstract: A method used during the formation of a semiconductor device including a semiconductor wafer assembly comprises a first step of forming a first mask over a front of the wafer assembly such that a portion of first and second layers are uncovered by the mask. Next, the uncovered portion of the second layer is etched to form at least one sidewall in the second layer. A film is formed over the sidewall and, subsequent to forming the film, at least a portion of a third layer on a back of the wafer assembly is removed. During this removal, the sidewall is protected by the film. After removing the third layer, a second mask is formed over a portion of the first and second layers and the first layer is exposed.

Abstract: Two approaches are proposed for forming an inter-metal dielectric layer with improved metal damage characteristics. This is of utmost importance for sub-quarter micron feature sizes, where thin metal lines are particularly susceptible to damage and where the HDP-CVD processes, which are used because of their excellent gap filling characteristics, are apt to cause metal damage. In approach one, a partially processed semiconductor wafer is provided containing a blanket layer of metal. A blanket dielectric layer is deposited. This layer could, for example, be silicone oxide, silicon nitride or silicone oxynitride; and the deposition process could be APCVD, LPCVD, 03-TEOS CVD or PECVD. The layer thickness could be in the range from about 0.01 microns to about 0.2 microns. Patterning and etching the blanket metal layer and protective dielectric layer results in the desired metal structure, except with a dielectric cap. The HDP-CVD insulating layer can now be deposited without concern for metal damage.

Abstract: A method for improving the patterning process of a conductive layer using a dual-layer cap of oxynitride and silicon nitride. The oxynitride layer acts as a BARC (Bottom Anti-Reflective Coating) to improve photolithography process performance. The oxynitride is formed by plasma-enhanced chemical vapor deposition.

Abstract: A process is disclosed for forming vias and trenches in two separate dielectric layers, which may be separated by an etch stop, while avoiding the etch mask stress complicated resist masks, or high aspect ratio openings of the prior art. A first dielectric layer 10 is formed over an integrated circuit structure 2 on a semiconductor substrate, and a thin second dielectric layer 20 is formed over the first dielectric layer. A first resist mask, is formed over the second dielectric layer, and the first and second dielectric layers are etched through to form one or more vias 18, 28 extending through both the first and second dielectric layers. The first resist mask is then removed and a third dielectric layer 70, having different etch characteristics than the second dielectric layer, is deposited over the structure.

Abstract: A method of patterning a polysilicon gate using an oxide hard mask using a novel 4 step insitu etch process. All 4 etch steps are performed insitu in a polysilicon high density plasma (TCP--transformer coupled plasma) etcher. A multi-layered semiconductor structure 35 (FIG. 1) is formed comprising: a substrate 10, a gate oxide layer 14, a polysilicon layer 18, a hard mask layer 22, and a bottom anti-reflective coating (BARC) layer 26 and a resist layer 30. The 4 step insitu etch process comprises:a) in STEP 1, etching the bottom anti-reflective coating (BARC) layer by flowing HBr and O.sub.

Abstract: The practice of forming self-aligned contacts in MOSFETs using a silicon nitride gate sidewall and a silicon nitride gate cap has found wide acceptance, particularly in the manufacture of DRAMs, where bitline contacts are formed between two adjacent wordlines, each having a nitride sidewall. The contact etch requires a an RIE etch having a high oxide/nitride selectivity. Current etchants rely upon the formation of a polymer over nitride surfaces which enhances oxide/nitride selectivity. However, for contact widths of less than 0.35 microns, as are encountered in high density DRAMs, the amount of polymer formation required to attain a high selectivity causes the contact opening to close over with polymer before the opening is completely etched. This results in opens or unacceptably resistive contacts. On the other hand, if the etchant is adjusted to produce too little polymer, the nitride cap and sidewalls are thinned or etched through, producing gate to source/drain shorts.

Abstract: An interconnection layer 3 in a floating state and an interlayer insulating film 6 are formed on a semiconductor substrate. A connection hole 4 penetrating the interlayer insulating film and the interconnection layer is formed by dry etching with fluorocarbon. Filled in the connection hole is a conductive member 5 which is electrically connected to the interconnection layer. Accordingly, an improved method for manufacturing a semiconductor device offering a reduced contact resistance even for an extremely small contact hole is obtained.

Abstract: The present disclosure pertains to a method for plasma etching a semiconductor patterning stack. The patterning stack includes at least one layer comprising either a dielectric-comprising antireflective material or an oxygen-comprising material. In many instances the dielectric-comprising antireflective material will be an oxygen-comprising material, but it need not be limited to such materials. In one preferred embodiment of the method, the chemistry enables the plasma etching of both a layer of the dielectric-comprising antireflective material or oxygen-comprising material and an adjacent or underlying layer of material. In another preferred embodiment of the method, the layer of dielectric-comprising antireflective material or oxygen-comprising material is etched using one chemistry, while the adjacent or underlying layer is etched using another chemistry, but in the same process chamber.

Abstract: A plasma etch method for forming a patterned silicon nitride layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket silicon nitride layer. There is then formed upon the blanket silicon nitride layer a patterned photoresist layer. Finally, there is etched through a plasma etch method while employing the patterned photoresist layer as an etch mask layer the blanket silicon nitride layer to form a patterned silicon nitride layer. The plasma etch method employs an etchant gas composition comprising a perfluorocarbon etchant gas, a hydrofluorocarbon etchant gas and an oxygen etchant gas at a perfluorocarbon etchant gas flow rate, a hydrofluorocarbon etchant gas flow rate and an oxygen etchant gas flow rate which yields substantially no plasma etch bias of the patterned silicon nitride layer with respect to the patterned photoresist layer.

Abstract: Contact holes through a dielectric are formed by forming a layer of polysilicon having a thickness between 0.02 um and 0.15 um inclusive on the dielectric, forming a layer of resist having a thickness between 0.4 um and 0.6 um inclusive on the layer of polysilicon, making a mask of the layer of resist, using it to form a mask in the layer of polysilicon and etching contact holes in the dielectric by exposing it to etching gasses through the apertures in the polysilicon mask. When the dielectric includes a layer of oxide adjacent the polysilicon mask and a layer of nitride between it and elements of the device, the resist mask is removed prior to etching the contact hole and a gas mixture of: C.sub.4 F.sub.8 ; one of Ar, H, F; CO; CF.sub.4 or C.sub.2 F.sub.6 is used.

Abstract: In a method for manufacturing a semiconductor device, an insulating layer is formed on a refractory metal layer, and a contact hole in the insulating layer by a dry etching process using an etching gas includes one of:a mixture gas of fluorocarbon and hydrogen;a mixture gas of hydrofluorocarbon and hydrogen;a gas of hydrofluorocarbon; anda fluorocarbon gas except for CF.sub.4.

Abstract: The invention comprises methods of forming contact openings and methods of forming contacts. In but one implementation, an inorganic antireflective coating material layer is formed over an insulating material layer. A contact opening is etched through the inorganic antireflective coating layer and into the insulating layer. Insulative material within the contact opening is etched and a projection of inorganic antireflective coating material is formed within the contact opening. The inorganic antireflective coating material is etched to substantially remove the projection from the contact opening. The preferred etching to remove the projection is facet etching, most preferably plasma etching. The preferred inorganic antireflective coating material is selected from the group consisting of SiO.sub.x where "x" ranges from 0.1 to 1.8, SiN.sub.y where "y" ranges from 0.1 to 1.2, and SiO.sub.x N.sub.y where "x" ranges from 0.2 to 1.8 and "y" ranges from 0.01 to 1.0, and mixtures thereof.

Abstract: An improved etching method allowing the formation of a silicon nitride film with an adequate film thickness at the sidewall portion of a pattern is disclosed. A silicon nitride film formed to cover a stepped pattern is dry-etched, employing plasma of mixed gases containing CH.sub.2 F.sub.2 and O.sub.2. As a result, a sidewall spacer of the silicon nitride film is formed at the sidewall of the pattern in a self-aligned manner.

Abstract: A novel anisotropic plasma etching process for forming patterned silicon nitride (Si.sub.3 N.sub.4) layers with improved critical dimension (CD) control while minimizing the Si.sub.3 N.sub.4 footing at the bottom edge of the Si.sub.3 N.sub.4 pattern is achieved. A pad oxide/silicon nitride layer is deposited on a silicon substrate. A patterned photoresist layer is used as an etching mask for etching the silicon nitride layer. By this invention, a chlorine (Cl.sub.2) breakthrough plasma pre-etch forms a protective polymer layer on the sidewalls of the patterned photoresist and removes residue in the open areas prior to etching the Si.sub.3 N.sub.4. The Si.sub.3 N.sub.4 is then aniso-tropically plasma etched using an etch gas containing SF.sub.6. The polymer layer, formed during the Cl.sub.2 pre-etch, reduces the lateral recessing of the photoresist when the Si.sub.3 N.sub.4 is etched, and results in improved patterned Si.sub.3 N.sub.4 profiles with reduced CD bias, and minimizes Si.sub.3 N.sub.

Abstract: A self-aligned contact etch and method for forming a self-aligned contact etch. In one embodiment, the present invention performs an oxide selective etch to form an opening originating at a top surface of a photoresist layer. The opening extends through an underlying oxide layer, and terminates at a top surface of a nitride layer which underlies the oxide layer. Next, the present invention performs a nitride selective etch to extend the opening through the nitride layer to an underlying contact layer. In the present invention, the nitride selective etch causes the photoresist layer to be etched/receded. The nitride selective etch of the present invention further causes the oxide layer to be etched at and near the opening at the interface between the photoresist layer and the oxide layer. As a result, the opening is rounded at the top edge thereof when the layer of photoresist is removed.

Abstract: A method for etching a semiconductor device (10) having BARC layer (22) and nitride layer (20) includes etching BARC layer (22) until reaching a first set point in the fabrication reaction chamber and then etching nitride layer (20) in-situ the fabrication reaction chamber immediately following etching BARC layer (22).

Abstract: A method for forming a gate structure used in borderless contact etching is disclosed including the steps described below. Forming a conductive layer on a substrate, followed by forming a first silicon nitride layer on the conductive layer. The next step is to pattern a gate electrode by etching all the layers formed in the steps mentioned previously. The following steps is to form a second silicon nitride layer on the surface of the gate electrode and the substrate. Finally, etching the second silicon nitride layer to form a nitride spacer on the side walls of the gate electrode. The altitude of the nitride spacer is higher than the altitude of the first silicon nitride layer.

Abstract: An oxide etch process that is highly selective to nitride, thereby being beneficial for a self-aligned contact etch of silicon dioxide to an underlying thin layer of silicon nitride. The process uses difluoromethane (CH.sub.2 F.sub.2) for its strong polymer forming and a greater amount of trifluoromethane (CHF.sub.3) for its strong etching, and with a high diluent fraction of argon (Ar). The etch process is performed at a low pressure of about 20 milliTorr in a high-density plasma etching chamber.

Abstract: An adjustable method for making trenches for a semiconductor IC device having eliminated top corners is disclosed. The adjustable method includes forming a masking layer on the surface of the silicon nitride layer covering the device substrate that has openings corresponding to the openings of the trenches formed. Dimension of the masking layer opening is relatively greater than the dimension of the opening of the corresponding trench. An anisotropic etching procedure is then performed against the portions of the device substrate exposed out of the coverage of the masking layer, and the anisotropic etching shapes the trench sidewalls into sloped ones having larger dimension at the opening than at the surface of the filling material inside the trenches. This eliminates the top corners at the edges of the trench opening, charge accumulation and consequent leakage current can thus be prevented.

Abstract: An etch process utilizing Cl.sub.2 /He chemistry for use in a silicon integrated circuit manufacturing process. The etch is a highly nitride selective, anisotropic etch. The manufacturing process in which the Cl.sub.2 /He etch is employed includes steps of oxidizing a surface of a silicon wafer; depositing a first polycrystalline silicon on the wafer surface; depositing a silicon nitride-silicon dioxide layer on the wafer surface; depositing a silicon nitride spacer on the wafer; etching with Cl.sub.2 /He chemistry to remove essentially all of the silicon nitride spacer except for bitline remnants (i.e., stringers) of the silicon nitride spacer atop silicon dioxide; depositing a second polycrystalline silicon atop the etched wafer; and selectively removing portions of said second polycrystalline silicon from the wafer. The bitline remnants of the silicon nitride, i.e., stringers, are not conductive. The Cl.sub.

Abstract: A method for forming a patterned silicon containing dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a silicon containing dielectric layer. There is then formed upon the silicon containing dielectric layer a hard mask layer, where the hard mask layer leaves exposed a portion of the silicon containing dielectric layer. There is then etched partially through a first plasma etch method the silicon containing dielectric layer to form a partially etched silicon containing dielectric layer. The first plasma etch method employs a first etchant gas composition comprising a first fluorocarbon etchant gas which predominantly forms a fluoropolymer layer upon at least the hard mask layer. Finally, there is then etched through a second plasma etch method the partially etched silicon containing dielectric layer to form a patterned silicon containing dielectric layer.

Abstract: A plasma etch method for forming a patterned silicon nitride layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket silicon nitride layer. There is then formed upon the blanket silicon nitride layer a patterned photoresist layer. Finally, there is etched through a plasma etch method while employing the patterned photoresist layer as an etch mask layer the blanket silicon nitride layer to form a patterned silicon nitride layer. The plasma etch method employs an etchant gas composition comprising a perfluorocarbon etchant gas, a hydrofluorocarbon etchant gas and an oxygen etchant gas at a perfluorocarbon etchant gas flow rate, a hydrofluorocarbon etchant gas flow rate and an oxygen etchant gas flow rate which yields substantially no plasma etch bias of the patterned silicon nitride layer with respect to the patterned photoresist layer.

Abstract: A modular semiconductor wafer processing system comprises a chamber with a wafer support and gas manifold structure that supplies reactive gases through a showerhead delivery system to one side of a wafer-being-processed and that exhausts both the reactive gases and a non-reactive gas flow. The other side of the wafer is protected from the reactive gases by evenly delivering the non-reactive gases from a platen close to the wafer. The gap between the wafer and platen, and the choice of non-reactive gas and its flow rate are adjusted to optimize the protection afforded to the wafer's one side while still allowing, for example, the stripping of a silicon nitride film from the wafer's other side.

Abstract: An integrated circuit includes a conductive structure (66) is formed with a top layer of silicon nitride (62) and silicon nitride (70) sidewalls on a semiconductor substrate. The layer of silicon nitride (70) covering the sidewalls of the conductive structure (66) intersect with the layer of silicon nitride on top of the conductive structure with a relatively square shoulder. A subsequently deposited conductor makes contact with the surface of the semiconductor substrate (56) without shorting to the conductive structure (66) on the semiconductor substrate.

Abstract: A process for controlling the etch of a silicon dioxide layer at a high etch rate and high selectivity with respect to silicon nitride, particularly in a multilayer structure, by maintaining various portions of the etch chamber at elevated temperatures.

Abstract: An RIE method and apparatus provides uniform and selective etching through silicon nitride material of a supplied workpiece such as a silicon wafer having silicon oxide adjacent to the SiN. A plasma-maintaining gas that includes N.sub.2 having an inflow rate of at least 10 sccm is used to provide etch-depth uniformity across the workpiece. The plasma-maintaining gas further includes HBr and one or both of NF.sub.3 and SF.sub.6.