Abstract: A tandem photovoltaic device includes a first cell and a second cell arranged in tandem. The first cell is configured to receive incident electromagnetic radiation and includes a first charge separating layer having a first semiconducting polymer adapted to create electric charge carriers generated by electromagnetic radiation. A second cell is configured to receive electromagnetic radiation passing out of the first cell in a light propagation path. The second cell includes a second charge separating layer having a second semiconducting polymer adapted to create electric charge carriers generated by electromagnetic radiation. A first titanium oxide layer is interposed between the first and second cells, wherein the first titanium oxide layer is substantially amorphous and has a general formula of TiOx where X being a number of 1 to 1.96.

Abstract: Various embodiments of the present invention are directed to a photodiode module including a structure configured to selectively couple light to a dielectric-surface mode of a photonic crystal of the photodiode module. In one embodiment of the present invention, a photodiode module includes a semiconductor structure having a p-region and an n-region. The photodiode module further includes a photonic crystal having a surface positioned adjacent to the semiconductor structure. A diffraction grating of the photodiode module may be positioned and configured to selectively couple light incident on the diffraction grating to a dielectric-surface mode associated with the surface of the photonic crystal. In another embodiment of the present invention, a photodiode apparatus includes multiple, stacked photodiode modules, each of which is configured to selectively absorb light at a selected wavelength or range of wavelengths.

Abstract: A photovoltaic (PV) device has at least one lower PV cell on a substrate, the cell having a metallic back contact, and a absorber, and a transparent conductor layer. An upper PV cell is adhered to the lower PV cell, electrically in series to form a stack. The upper PV cell has III-V absorber and junction layers, the cells are adhered by transparent conductive adhesive having filler of conductive nanostructures or low temperature solder. The upper PV cell has no substrate. An embodiment has at least one shape of patterned conductor making contact to both a top of the upper and a back contact of the lower cells to couple them together in series. In an embodiment, a shape of patterned conductor draws current from excess area of the lower cell to the upper cell, in an alternative embodiment shapes of patterned conductor couples I-III-VI cells not underlying upper cells in series strings, a string being in parallel with at least one stack.

Abstract: A stack-type photovoltaic element with improved conversion efficiency having an intermediate layer and a method of manufacturing the same are provided. A stack-type photovoltaic element according to the present invention includes a first photovoltaic element portion (a) and a second photovoltaic element portion from a substrate side, as well as at least one intermediate layer between the first photovoltaic element portion and the second photovoltaic element portion. The intermediate layer is formed from a metal oxide film having an oxygen atom concentration/metal atom concentration ratio not lower than 0.956 and not higher than 0.976.

Abstract: A method for large scale manufacture of photovoltaic devices includes loading a substrate into a load lock station and transferring the substrate in a controlled ambient to a first process station. The method includes using a first physical deposition process in the first process station to cause formation of a first conductor layer overlying the surface region of the substrate. The method includes transferring the substrate to a second process station, and using a second physical deposition process in the second process station to cause formation of a second layer overlying the surface region of the substrate. The method further includes repeating the transferring and processing until all thin film materials of the photovoltaic devices are formed. In an embodiment, the invention also provides a method for large scale manufacture of photovoltaic devices including feed forward control. That is, the method includes in-situ monitoring of the physical, electrical, and optical properties of the thin films.

Abstract: An image sensor and a method of manufacturing an image sensor. A method of manufacturing an image sensor may include forming an interconnection and/or an interlayer dielectric over a semiconductor substrate including circuitry connected to an interconnection. A method of manufacturing an image sensor may include forming a photodiode having a first doping layer and/or a second doping layer over an interlayer dielectric, and forming a via hole through a photodiode, which may expose a portion of a surface of an interconnection. A method of manufacturing an image sensor may include forming a barrier pattern over a via hole which may cover an exposed surface of a second doping layer, and a contact plug on and/or over a via hole, which may connect an interconnection and a first doping layer. An upper portion of a contact plug may be etched. An insulating layer may be formed over a contact plug.

Abstract: An image sensor and a method of manufacturing the same are provided. The image sensor includes a substrate having a sensor array area and a peripheral circuit area a first insulating film structure formed on the peripheral circuit area and including a plurality of first multi-layer wiring lines and a second insulating film structure formed on the sensor array area and including a plurality of second multi-layer wiring lines. The uppermost-layer wiring line of the plurality of first multi-layer wiring lines is higher than that of the uppermost-layer wiring line of the plurality of second multi-layer wiring lines. The first insulating film structure includes an isotropic etch-stop layer, and the second insulating film structure does not include the isotropic etch-stop layer.

Abstract: A method is provided for forming a tandem dye-sensitized solar cell (DSC) using a bonding process. The method forms a first photovoltaic (PV) cell including a cathode, a first dye, and an anode. A second PV cell is also formed including a cathode, a second dye, and an anode. The second PV cell anode is bonded to the first PV cell cathode, at a temperature of less than 100 degrees C., using a transparent conductive adhesive. In response to the bonding, an internal series electrical connection is formed between the first PV cell and the second PV cell. In one aspect, the second PV cell is formed from a first titanium oxide (TiO2) nanotube (TNT) layer anode.

Abstract: A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer.

Abstract: A Self-Synchronized Radio Frequency RF-Interconnect (SSRFI), based on capacitor coupling and peak detection, for vertically interconnecting active device layers in three-dimensional (3D) integrated circuits (IC), as well as wireless communication and RF signal transmission/receiving.

Abstract: A multi-junction group III-V compound semiconductor solar cell and fabrication method thereof forms a 2D photonic crystal structure in the topmost window layer of the stacked solar cell units by etching holes in the window layer. The 2D photonic crystal structure causes omni-directional reflection of the sunlight along any transverse plane of the 2D photonic crystal structure and directs the oblique sunlight to enter the bottom surface of the holes, thereby increasing the amount of incident light. By applying the property that the 2D photonic crystal structure causes a wider range of wavelengths to have higher transmission efficiency at the window layer to the multi-junction group III-V compound semiconductor solar cell, energy conversion efficiency may be effectively increased.

Abstract: A lateral p-i-n photodetector is provided that includes an array of vertical semiconductor nanowires of a first conductivity type that are grown over a semiconductor substrate also of the first conductivity type. Each vertically grown semiconductor nanowires of the first conductivity type is surrounded by a thick epitaxial intrinsic semiconductor film. The gap between the now formed vertically grown semiconductor nanowires-intrinsic semiconductor film columns (comprised of the semiconductor nanowire core surrounded by intrinsic semiconductor film) is then filled by forming an epitaxial semiconductor material of a second conductivity type which is different from the first conductivity type. In a preferred embodiment, the vertically grown semiconductor nanowires of the first conductivity type are n+ silicon nanowires, the intrinsic epitaxial semiconductor layer is comprised of intrinsic epitaxial silicon, and the epitaxial semiconductor material of the second conductivity type is comprised of p+ silicon.

Abstract: Two junction solar energy conversion devices, i.e. photovoltaic cells have a bottom silicon N+/P/P+ photovoltaic cell and an upper GaP N+/P/P+ photovoltaic cell containing quantum well layers which extend the wavelength range over which the GaP cell absorbs light. The quantum well layers are composed of materials other than Gallium Phosphide (GaP) and may be either pseudomorphic or metamorphic. Light trapping may be incorporated at the top surface of the GaP photovoltaic cell along with anti-reflective coatings, and light trapping may be incorporated on the bottom surface of the silicon cell. The bottom surface of the silicon photovoltaic cell is coated with a passivating dielectric layer and electrical contact to the silicon is made with conductive vias extending through the passivating layer.

Abstract: It is an object to provide an image sensor having a sufficiently-large ratio of a surface area of a light-receiving section to an overall surface area of one pixel.

Abstract: A light-emitting diode and the manufacturing method thereof are disclosed. The manufacturing method includes the steps of: sequentially forming a bonding layer, a geometric pattern layer, a reflection layer, an epitaxial structure and a first electrode on a permanent substrate, wherein the geometric pattern layer has a periodic structure; and forming a second electrode on one side of the permanent substrate.

Abstract: A multi-junction solar cell structure includes a supporting substrate, a Group IV element-based thin film, and a Group III-V element-based thin film sequentially stacked on the supporting substrate. When the multi-junction solar cell structure is active, the Group III-V element-based thin film contacts the light before the Group IV element-based thin film does. The Group IV element-based thin film includes a first solar cell and the Group III-V element-based thin film includes a second solar cell, wherein the band gap of the first solar cell is lower than the band gap of the second solar cell.

Abstract: Provided are embodiments of an image sensor. The image sensor can comprise a first substrate including a transistor circuit, a lower interconnection layer, an upper interconnection layer, and a second substrate including a vertical stacked photodiode. The lower interconnection layer is disposed on the first substrate and comprises a lower interconnection connected to the transistor circuit. The upper interconnection layer is disposed on the lower interconnection layer and comprises an upper interconnection connected with the lower interconnection. The vertical stacked photodiode can be disposed on the upper interconnection layer and connected with the upper interconnection through, for example, a single plug connecting a blue, green, and red photodiode of the vertical stack or a corresponding plug for each of the blue, green, and red photodiode of the vertical stack.

Abstract: The purpose is manufacturing a photoelectric conversion device with excellent photoelectric conversion characteristics typified by a solar cell with effective use of a silicon material. A single crystal silicon layer is irradiated with a laser beam through an optical modulator to form an uneven structure on a surface thereof. The single crystal silicon layer is obtained in the following manner; an embrittlement layer is formed in a single crystal silicon substrate; one surface of a supporting substrate and one surface of an insulating layer formed over the single crystal silicon substrate are disposed to be in contact and bonded; heat treatment is performed; and the single crystal silicon layer is formed over the supporting substrate by separating part of the single crystal silicon substrate fixed to the supporting substrate along the embrittlement layer or a periphery of the embrittlement layer.

Abstract: Provided are a high reliability stack module fabricated at low cost by using simplified processes, a card using the stack module, and a system using the stack module. In the stack module, unit substrates are stacked with respect to each other and each unit substrate includes a selection terminal. First selection lines are electrically connected to selection terminals of first unit substrates disposed in odd-number layers, pass through some of the unit substrates, and extend to a lowermost substrate of the unit substrates. Second selection lines are electrically connected to selection terminals of second unit substrates disposed in even-number layers, pass through some of the unit substrates, and extend to the lowermost substrate of the unit substrates. The selection terminal is disposed between the first selection lines and the second selection lines.

Abstract: A photo-detector comprising: a photo absorbing layer comprising an n-doped semiconductor exhibiting a valence band energy level; a barrier layer, a first side of the barrier layer adjacent a first side of the photo absorbing layer, the barrier layer exhibiting a valence band energy level substantially equal to the valence band energy level of the doped semiconductor of the photo absorbing layer; and a contact area comprising a doped semiconductor, the contact area being adjacent a second side of the barrier layer opposing the first side, the barrier layer exhibiting a thickness and a conductance band gap sufficient to prevent tunneling of majority carriers from the photo absorbing layer to the contact area and block the flow of thermalized majority carriers from the photo absorbing layer to the contact area. Alternatively, a p-doped semiconductor is utilized, and conductance band energy levels of the barrier and photo absorbing layers are equalized.

Abstract: More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.

Abstract: A method for large scale manufacture of photovoltaic devices includes loading a substrate into a load lock station and transferring the substrate in a controlled ambient to a first process station. The method includes using a first physical deposition process in the first process station to cause formation of a first conductor layer overlying the surface region of the substrate. The method includes transferring the substrate to a second process station, and using a second physical deposition process in the second process station to cause formation of a second layer overlying the surface region of the substrate. The method further includes repeating the transferring and processing until all thin film materials of the photovoltaic devices are formed. In an embodiment, the invention also provides a method for large scale manufacture of photovoltaic devices including feed forward control. That is, the method includes in-situ monitoring of the physical, electrical, and optical properties of the thin films.

Abstract: A multiple-wavelength opto-electronic device may include a substrate and a plurality of active optical devices carried by the substrate and operating at different respective wavelengths. Each optical device may include a superlattice comprising a plurality of stacked groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon.

Abstract: A photovoltaic solar cell including an upper electrode, a layer with light scattering and/or reflection properties, and a lower electrode. The layer with light scattering and/or reflection properties is located between the upper electrode and the lower electrode.

Abstract: The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.

Abstract: A semiconductor device where multiple chips of identical design can be stacked, and the spacer and interposer eliminated, to improve three-dimensional coupling information transmission capability. A first semiconductor circuit including a three-dimensional coupling circuit (three-dimensional coupling transmission terminal group and three-dimensional coupling receiver terminal group); and a second semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode (power supply via hole and ground via hole); and a third semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode are stacked on the package substrate.

Abstract: An organic/inorganic hybrid film represented by SiCxHyOz (x>0, y?0, z>0) is plasma-etched with an etching gas containing fluorine, carbon and nitrogen. During the etching, a carbon component is eliminated from the surface portion of the organic/inorganic hybrid film due to the existence of the nitrogen in the etching gas, to thereby reform the surface portion. The reformed surface portion is nicely plasma-etched with the etching gas containing fluorine and carbon.

Abstract: An embodiment of the present invention is a technique to construct a multi-die package. A stack of dice is formed from a base substrate in a package. The dice are positioned one on top of another and have copper plated segments for die interconnection. The dice are interconnected using copper plating to connect the copper plated segments.

Abstract: Fabrication of a three-dimensional semiconductor structure is provided by the present disclosure. A buffer oxide film, a nitride film, and an ONO dielectric layer are formed on a handle wafer. A semiconductor layer and an oxide film are formed on a donor wafer, which is turned over and is then bonded to a handle wafer. Silicon of the donor wafer is then removed. In the same manner, blue, green, and red diode layers, and a transistor layer are sequentially formed. A metal layer is formed on the transistor layer. Inter-elements contact and pixel separation processes are performed and a support layer is bonded. The whole device is turned over and the nitride film is etched using an etch-stop layer, thus removing the handle wafer. After the elements are separated, packaging is performed to complete the device. Therefore, a back illuminated image sensor of a multi-layer structure can be provided.

Abstract: A tandem photovoltaic cell. The tandem photovoltaic cell includes a bifacial top cell and a bottom cell. The top bifacial cell includes a top first transparent conductive oxide material. A top window material underlies the top first transparent conductive oxide material. A first interface region is disposed between the top window material and the top first transparent conductive oxide material. The first interface region is substantially free from one or more entities from the top first transparent conductive oxide material diffused into the top window material. A top absorber material comprising a copper species, an indium species, and a sulfur species underlies the top window material. A top second transparent conductive oxide material underlies the top absorber material. A second interface region is disposed between the top second transparent conductive oxide material and the top absorber material. The bottom cell includes a bottom first transparent conductive oxide material.

Abstract: CMOS image sensors and methods of fabricating the same. The CMOS image sensors include a pixel array region having an active pixel portion and an optical block pixel portion which encloses the active pixel portion. The optical block pixel portion includes an optical block metal pattern for blocking light. The optical block metal pattern may be connected to a ground portion.

Abstract: A thin-film solar cell including a substrate, a first conductive layer, a plurality of photovoltaic layers, a second conductive layer, a first passivation layer and a second passivation layer is provided. The first conductive layer is disposed on the substrate. The photovoltaic layers are stacked on the first conductive layer and in electrical tandem, wherein each photovoltaic layer is adapted for generating a photocurrent. The second conductive layer is disposed on the photovoltaic layers. The first passivation layer is disposed on the second conductive layer, and the second passivation layer is disposed on the first passivation layer. The first and second passivation layers are used for reflecting the light within a wavelength range into the photovoltaic layers, so as to make the photocurrent generated by the photovoltaic layers being matched. A manufacturing method of the thin-film solar cell is also provided.

Abstract: A multi junction photovoltaic device is disclosed. In certain examples, the device includes an upper photovoltaic cell comprising a first plurality of layers of films, including a first active layer of a chalcogenide having a first lattice constant and first energy band gap, and a lower photovoltaic cell disposed below the upper photovoltaic cell and adapted to receive photon radiation passing through the upper photovoltaic cell, and comprising a second plurality of layers of films, including an active second layer of a IB-IIIA-chalcogenide having a second lattice constant and a second energy band gap. The first lattice constant differs from the second lattice constant by no more than about 10%. The first energy band gap can be greater than the second energy band gap by at least about 0.5 eV, or 0.6 eV, or 0.7 eV.

Abstract: According to one embodiment, a solid-state imaging device with a plurality of light-receiving layers for acquiring different color signals stacked one on top of another in the optical direction. Each of the light-receiving layers includes a photoelectric conversion part that receives light entering the back side of the layer and generates signal charges and a read transistor that is provided on the front side of the layer and reads the signal charges generated at the photoelectric conversion part. A semiconductor layer is stacked via an insulating film on the front side of the top layer of the plurality of light-receiving layers. At the semiconductor layer, there is provided a signal scanning circuit which processes a signal read by each of the read transistors and outputs a different color signal from each of the light-receiving layers to the outside.

Abstract: In an image sensor chip package method, a transparent substrate having an upper surface, a lower surface, and through holes is provided. The through holes pass through the transparent substrate. Conductive posts are formed in the through holes. A sealing ring is formed on the lower surface of the transparent substrate. A chip having an active surface, an image sensitive area, and die pads is provided. The image sensitive area and the die pads are located on the active surface. Conductive bumps are formed and respectively disposed on the die pads for respectively connecting the conductive posts. At the time the active surface of the chip is turned to face toward the lower surface of the transparent substrate. The chip is assembled to the transparent substrate and electrically connected with the conductive posts via the die pads. The sealing ring surrounds the image sensitive area and the die pads.

Abstract: Embodiments relate to an image sensor and a method for manufacturing an image sensor. According to embodiments, a method may include forming a semiconductor substrate including a pixel part and a peripheral part, forming an interlayer dielectric film including a metal wire on and/or over the semiconductor substrate, forming photo diode patterns on and/or over the interlayer dielectric film and connected to the metal wire in the pixel part, forming a device isolation dielectric layer on and/or over the interlayer dielectric film including the photo diode patterns, forming a first via hole on and/or over the device isolation dielectric layer to partially expose the photo diode patterns, and forming a second via hole on and/or over the device isolation dielectric layer to expose the metal wire in the peripheral part. According to embodiments, vertical integration of transistor circuitry and a photo diode may be achieved.

Abstract: It is to provide a vapor phase growth method in which an epitaxial layer consisting of a compound semiconductor such as InAlAs, can be grown, with superior reproducibility, on a semiconductor substrate such as Fe-doped InP. In vapor phase growth method for growing an epitaxial layer on a semiconductor substrate, a resistivity of the semiconductor substrate at a room temperature is previously measured, a set temperature of the substrate is controlled depending on the resistivity at the room temperature such that a surface temperature of the substrate is a desired temperature regardless of the resistivity of the semiconductor substrate, and the epitaxial layer is grown.

Abstract: Methods and apparatus for forming a product from ultra thin layers of a base material are disclosed. Some embodiments provide a process that allows one to structure a silicon base material, like the ingot, and to transfer this structure into a respective silicon process step. Some embodiments provide a process that allows one to structure any complex structured layer stacks, where the layers can be applied on top of each other using, e.g., bonding technology.

Abstract: A thin-film solar cell having a first solar cell layer with a plurality of unit cells including a photoelectric conversion layer that are connected in series; a second solar cell layer with a plurality of unit cells including a photoelectric conversion layer that are connected in series, and that has band gap energy different from the first solar cell layer and a threshold voltage coincident with the first solar cell layer; and an electrode connector, that connects the first solar cell layer with the second solar cell layer in parallel.

Abstract: On a surface of a GaAs substrate, layers to be a top cell are formed by epitaxial growth. On the top cell, layers to be a bottom cell are formed. Thereafter, on a surface of the bottom cell, a back surface electrode is formed. Thereafter, a glass plate is adhered to the back surface electrode by wax. Then, the GaAs substrate supported by the glass plate is dipped in an alkali solution, whereby the GaAs substrate is removed. Thereafter, a surface electrode is formed on the top cell. Finally the glass plate is separated from the back surface electrode. In this manner, a compound solar battery that improves efficiency of conversion to electric energy can be obtained.

Abstract: A backside illuminated multi-junction solar cell module includes a substrate, multiple multi-junction solar cells, and a cell interconnection that provides a series connection between at least two of the multi-junction solar cells. The substrate may include a material that is substantially transparent to solar radiation. Each multi-junction solar cell includes a first active cell, grown over the substrate, for absorbing a first portion of the solar radiation for conversion into electrical energy and a second active cell, grown over the first active cell, for absorbing a second portion of the solar radiation for conversion into electrical energy. At least one of the first and second active cells includes a nitride.

Abstract: Photovoltaic modules, as well as related systems, methods and components are disclosed. In some embodiments, a photovoltaic module can include a first photovoltaic cell including an electrode, a second photovoltaic cell including an electrode, and an interconnect. The electrode of the first photovoltaic cell can overlap the electrode of the second photovoltaic cell. The interconnect can electrically connect the electrode of the first photovoltaic cell and the electrode of the second photovoltaic cell. The interconnect can mechanically couple the first and second photovoltaic cells.

Abstract: An image sensor including a first epitaxial layer formed over a semiconductor substrate; first photodiodes formed spaced apart in the first epitaxial layer; a first isolation region electrically isolating the first photodiodes from each other; a second epitaxial layer formed over the first epitaxial layer; second photodiodes formed spaced apart in the second epitaxial layer; and a second isolation region electrically isolating the second photodiodes from each other.

Abstract: Provided is a multi-well CMOS image sensor and a method of fabricating the same. The multi-well CMOS image sensor may include a plurality of photodiodes vertically formed in a region of a substrate, an n+ wall that vertically connects an outer circumference of the photodiodes, and a floating diffusion region that is connected to the photodiodes on a side of the n+ wall to receive charges from the photodiodes, wherein a p-type region is formed between the floating diffusion region and the n+ wall, and the plurality of photodiodes have a multi-potential well structure.

Abstract: A quantum-well photoelectric device, such as a quantum cascade laser, is constructed of monocrystalline nanoscale membranes physically removed from a substrate and mechanically assembled into a stack.

Abstract: Modules are disclosed. The modules can include a first photovoltaic cell including an electrode; and a second photovoltaic cell including an electrode having a bent end connected to the electrode of the first photovoltaic cell.

Abstract: Modules are disclosed. The modules can include a first photovoltaic cell including an electrode, a second photovoltaic cell including an electrode, and an interconnect disposed in the electrode of the first photovoltaic cell and disposed in the electrode of the second photovoltaic cell so that the electrode of the first photovoltaic cell and the electrode of the second photovoltaic cell are connected.

Abstract: A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and increases the capacitance of the photodiode by acting as a reflective barrier to photo-generated charge in the doped region of the second conductivity type of the photodiode. The deep implanted region also provides improved charge transfer from the charge collection region of the photodiode to a floating diffusion region adjacent the gate of the transfer transistor.

Abstract: An image sensor and manufacturing process thereof are provided. An image sensor according to an embodiment comprises a first wafer formed with a photodiode cell without a microlens and a second wafer formed with a circuit part including transistor and a capacitor. The first wafer is stacked on the second wafer such that a connecting electrode can be used to electrically connect the photodiode cell of the first wafer to the circuit part of the second wafer.

Abstract: A method of fabricating a vertical CMOS image sensor is disclosed, to improve the integration with the decrease in size of pixel by minimizing the lateral diffusion, in which phosphorous and arsenic ions are implanted while controlling the dose and energy, the method including forming a first photodiode in a semiconductor substrate; forming a first epitaxial layer on the semiconductor substrate; forming a first plug by sequentially implanting first and second ions in the first epitaxial layer; forming a second photodiode in the first epitaxial layer; forming a second epitaxial layer in the first epitaxial layer; forming an isolation area in the second epitaxial layer; and forming a third photodiode and a second plug in the second epitaxial layer.