Abstract: The present application relates to a method for producing a silica film, which includes a step of contacting a silica precursor layer formed of a silica precursor composition having a pH of 5 or less with a Lewis base, where the silica precursor composition includes a silica precursor formed from a silane compound and an acid catalyst. The present application can provide a method capable of forming a silica film having excellent resistance to a vertical load and a tangential load without going through expensive equipment or a high temperature process.

Abstract: There is included forming an oxide film on a substrate by alternately performing: forming the first oxide film containing an atom X by performing a first cycle including non-simultaneously performing forming a first layer including a component in which a first functional group is bonded to the atom X, and forming a second layer containing the atom X and oxygen by oxidizing the first layer; and forming the second oxide film containing the atom X by performing a second cycle including non-simultaneously performing forming a third layer including a component in which the first functional group is bonded to the atom X, and forming a fourth layer containing the atom X and oxygen by oxidizing the third layer, under a processing condition that an oxidizing power is higher than an oxidizing power when oxidizing the first layer.

Abstract: A method for manufacturing the semiconductor device includes: providing a layer to be etched; on a surface of the layer to be etched, forming a first sacrificial layer that is patterned and includes an opening for exposing the layer to be etched; forming a second sacrificial layer in the opening, the second sacrificial layer having a contact face contacted with the first sacrificial layer; forming a third sacrificial layer via a reaction between the first sacrificial layer and the second sacrificial layer at the contact face; removing at least one of at least part of an unreacted portion of the first sacrificial layer and the second sacrificial layer to form a patterned mask structure; etching the layer to be etched based on the patterned mask structure to form an etched pattern.

Abstract: A three-dimensional (3D) memory device includes a channel structure extending along a first direction and a control gate structure extending along a second direction around the channel structure. Preferably, channel structure includes a negative capacitance (NC) insulating layer, a charge trap structure, and a channel layer, in which the NC insulating layer includes HfZrOx and the charge trap structure includes a blocking layer, a charge trap layer, and a tunneling layer.

Abstract: Systems and methods for passivation of III-V semiconductors to create heterogeneous structures based on such semiconductors, to the structures themselves, and to devices using passivated III-V semiconductors, such as metal oxide-semiconductor field effect transistors (MOSFET) and Hall effect sensors using III-V semiconductors.

Abstract: A semiconductor device and a process of forming the semiconductor device are disclosed. The semiconductor device type of a high electron mobility transistor (HEMT) has double SiN films on a semiconductor layer, where the first SiN film is formed by the lower pressure chemical vapor deposition (LPCVD) technique, while, the second SiN film is deposited by the plasma assisted CVD (p-CVD) technique. Moreover, the gate electrode has an arrangement of double metals, one of which contains nickel (Ni) as a Schottky metal, while the other is free from Ni and covers the former metal. A feature of the invention is that the first metal is in contact with the semiconductor layer but apart from the second SiN film.

Abstract: A ferroelectric recording medium includes an electrode layer, a ferroelectric recording layer, and a protection layer formed in this order on a substrate, wherein the ferroelectric recording layer includes a ferroelectric layer, and a lattice constant of a material constituting the ferroelectric layer and a lattice constant of a material constituting the electrode layer or the substrate are lattice-matched within a range of ±10%.

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate that includes a chip region and an edge region around the chip region, and a semiconductor chip on the chip region of the redistribution substrate. The redistribution substrate includes a plurality of dielectric layers that are vertically stacked, a plurality of redistribution patterns on the chip region and in each of the dielectric layers, and a redistribution test pattern on the edge region and at a level the same as a level of at least one of the redistribution patterns.

Abstract: The present disclosure provides embodiments of improved area-selective deposition (ASD) processes and methods for selectively depositing polymer films on a variety of different target material. More specifically, the present disclosure provides improved ASD processes and related methods that use a cyclic vapor deposition process, which sequentially exposes a surface of a substrate to a polymer precursor followed by an initiator to selectively deposit a polymer thin film on a target material exposed on the substrate surface. The process of sequentially exposing the substrate surface to the precursor and the initiator can be repeated for one or more cycles of the cyclic vapor deposition process until a predetermined thickness of the polymer thin film is selectively deposited on the target material. In one embodiment, sequentially pulsed initiated chemical vapor deposition (spiCVD) is used to selectively deposit the polymer thin film on the target material.

Abstract: A substrate processing method for forming a nitride film on a substrate, includes: a raw material gas supply step of supplying a raw material gas containing an element to be nitrided; a hydrogen gas supply step of, after the raw material gas supply step, supplying a hydrogen gas activated by plasma; a thermal nitriding step of supplying a first nitriding gas containing nitrogen activated by heat and nitriding the element; and a plasma nitriding step of supplying a second nitriding gas containing nitrogen activated by plasma and nitriding the element.

Abstract: A Ga2O3-based semiconductor device includes a Ga2O3-based crystal layer including a donor, and an N-doped region formed in at least a part of the Ga2O3-based crystal layer.

Abstract: A method of depositing a coating and a layered structure is provided. A coating is deposited on a substrate to make a layered structure, such that an interface between the coating and the substrate is formed. The coating includes silicon, oxygen, and carbon, where the carbon doping in the coating increases between the interface and the top surface of the coating. The top surface of the coating is inherently hydrophobic and icephobic, and reduces the wetting of water or ice film on the layered structure, without requiring reapplication of the coating.

Abstract: A film deposition method is provided. In the method, chlorine gas is activated in a plasma generator, and an adsorption inhibitor group is formed by adsorbing the activated chlorine gas on a surface of a substrate in a processing chamber. A source gas containing chlorine and one of silicon and a metal is adsorbed on a region without the adsorption inhibitor group of the surface of the substrate, and a nitride film is deposited by supplying a nitriding gas to the surface of the substrate and causing the nitriding gas to react with the source gas. The substrate on which the nitride film is deposited is carried out of the processing chamber, and an inside of the plasma generator is purged with activated oxygen gas.

Abstract: A group-III nitride substrate includes: a base material part of a group-III nitride including a front surface, a back surface, and an inner layer between the front surface and the back surface, wherein the carbon concentration of the front surface of the base material part is higher than the carbon concentration of the inner layer.

Abstract: There are provided a plasma-curable multi-level substrate coating film-forming composition for forming a coating film having planarity on a substrate, wherein the composition can fill a pattern sufficiently.

Abstract: An interconnect structure includes an interconnect structure includes an etching stop layer; a dielectric layer and an insert layer on the etching stop layer, and a conductive feature in the dielectric layer, the insert layer and the etching stop layer. A material of the insert layer is different from the dielectric layer and the etching stop layer.

Abstract: An optical component with improved degradation resistance is provided. The optical component includes an optical material and a coating. The optical material has a native surface that is susceptible to degradation processes. The coating is a layer of an inorganic material and is applied so as to be substantially contiguous so that there are no continuous paths between fluid surrounding the optical component and the optical material.

Abstract: A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

Abstract: A method is for depositing silicon nitride by plasma-enhanced chemical vapour deposition (PECVD). The method includes providing a PECVD apparatus including a chamber and a substrate support disposed within the chamber, positioning a substrate on the substrate support, introducing a nitrogen gas (N2) precursor into the chamber, applying a high frequency (HF) RF power and a low frequency (LF) RF power to sustain a plasma in the chamber, introducing a silane precursor into the chamber while the HF and LF RF powers are being applied so that the silane precursor forms part of the plasma being sustained, and subsequently removing the LF RF power or reducing the LF RF power by at least 90% while continuing to sustain the plasma so that silicon nitride is deposited onto the substrate by PECVD.

Abstract: The invention relates to a substrate processing apparatus comprising a reaction chamber provided with a substrate rack for holding a plurality of substrates in the reaction chamber. The substrate rack may have a plurality of spaced apart substrate holding provisions configured to hold the plurality of substrates. The apparatus may have an illumination system constructed and arranged to irradiate radiation with a range from 100 to 500 nanometers onto a top surface of the substrates.

Abstract: A method of filling structures on a substrate uses a semi-dynamic reflow process. The method may include depositing a metallic material on the substrate at a first temperature, heating the substrate to a second temperature higher than the first temperature wherein heating of the substrate causes a static reflow of the deposited metallic material on the substrate, stopping heating of the substrate, and depositing additional metallic material on the substrate causing a dynamic reflow of the deposited additional metallic material on the substrate. RF bias power may be applied during the dynamic reflow to facilitate in maintaining the temperature of the substrate.

Abstract: An element 1 includes a pair of electrodes 2 and 3, and an intermediate layer 4 having deformability, arranged between the pair of electrodes 2 and 3, and containing, as a material, a silicon compound including an unpaired electron. The intermediate layer 4 may contain a particle including the unpaired electron. The intermediate layer 4 may have rubber elasticity. The intermediate layer 4 may have at least one peak at a g value between 2.070 and 2.001 when being measured at an environment temperature of ?150° C. by using an electron spin resonance (ESR) device. The intermediate layer 4 may have at least one peak at a g value between 2.070 and 2.001 when being measured at an environment temperature of ?150° C. by using the electron spin resonance (ESR) device.

Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.

Abstract: A method comprises providing a plurality of nanostructures comprising a base material. The plurality of nanostructures are exposed to a first material at a first deposition temperature. The plurality of nanoparticles are exposed to a second material at a second deposition temperature, and exposed to a Boron-10 (10B) containing material at a third deposition temperature so as to form a 10B-metal oxide based composite nanostructure.

Abstract: There is provided a method of forming a carbon film on a workpiece, which includes: loading the workpiece into a process chamber; supplying a gas containing a boron-containing gas into the process chamber to form a seed layer composed of a boron-based thin film on a surface of the workpiece; and subsequently, supplying a hydrocarbon-based carbon source gas and a pyrolysis temperature lowering gas containing a halogen element and which lowers a pyrolysis temperature of the hydrocarbon-based carbon source gas into the process chamber, heating the hydrocarbon-based carbon source gas to a temperature lower than the pyrolysis temperature to pyrolyze the hydrocarbon-based carbon source gas, and forming the carbon film on the workpiece by a thermal CVD.

Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.

Abstract: Techniques for deposition of high-density dielectric films for patterning applications are described. More particularly, a method of processing a substrate is provided. The method includes flowing a precursor-containing gas mixture into a processing volume of a processing chamber having a substrate positioned on an electrostatic chuck. The substrate is maintained at a pressure between about 0.1 mTorr and about 10 Torr. A plasma is generated at the substrate level by applying a first RF bias to the electrostatic chuck to deposit a dielectric film on the substrate. The dielectric film has a refractive index in a range of about 1.5 to about 3.

Abstract: A low pressure chemical vapor deposition (LPCVD) technique for nitride semiconductor materials includes steps of: setting a temperature in a furnace to be 750 to 900° C.; substituting an atmosphere in the furnace to ammonia (NH3); depositing a SiN film at an initial pressure by supplying di-chloro-silane (SiH2Cl2); and subsequently depositing the SiN film at a deposition pressure that is higher than the initial pressure. The invention has a feature that the initial pressure is at least higher than 60% of the deposition pressure.

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.

Abstract: There is provided a technique that includes arranging a plurality of substrates inside a process container in a vertical direction; and forming a film on each of the plurality of substrates by supplying a process gas into the process container. The act of forming the film includes: supplying the process gas into the process container; and performing pressure control such that a pressure inside the process container becomes a process pressure. A start timing of the act of supplying the process gas is adjusted with respect to a start timing of the act of performing the pressure control to adjust a thickness of a film formed on a substrate arranged on an upper portion of the plurality of substrates.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a first insulting layer on a substrate, forming a first conductor pattern in the first insulating layer, forming a second insulating layer on the first insulating layer, and forming a second wiring pattern and a contact via in the second insulating layer, wherein a top surface of the first insulating layer is higher than a top surface of the first conductor pattern.

Abstract: A method of forming a film on a substrate having silicon surfaces and dielectric surfaces includes precleaning the substrate; applying an inhibitor species to the dielectric surfaces; and exposing the substrate to a precursor while maintaining a temperature of less than about 600 degrees Celsius.

Abstract: A method of reducing an aberration of a lithographic apparatus, the method including measuring the aberration, taking the measured aberration into account, estimating a state of the lithographic apparatus, calculating a correction using the estimated state, and applying the correction to the lithographic apparatus.

Abstract: Disclosed are methods of depositing films of material on semiconductor substrates employing the use of a secondary purge. The methods may include flowing a film precursor into a processing chamber and adsorbing the film precursor onto a substrate in the processing chamber such that the precursor forms an adsorption-limited layer on the substrate. The methods may further include removing at least some unadsorbed film precursor from the volume surrounding the adsorbed precursor by purging the processing chamber with a primary purge gas, and thereafter reacting adsorbed film precursor while a secondary purge gas is flowed into the processing chamber, resulting in the formation of a film layer on the substrate. The secondary purge gas may include a chemical species having an ionization energy and/or a disassociation energy equal to or greater than that of O2. Also disclosed are apparatuses which implement the foregoing processes.

Abstract: Techniques are disclosed for methods and apparatuses for performing continuous-flow plasma enhanced atomic layer deposition (PEALD). Plasma gas, containing one or more component gases, is continuously flowed to a planar inductive coupled plasma source attached at an upper end of a cylindrical chamber. Plasma is separated from the ALD volume surrounding a wafer/substrate in the lower end of the chamber by a combination of a grounded metal plate and a ceramic plate. Each plate has a number of mutually aligned holes. The ceramic plate has holes with a diameter less than 2 Debye lengths and has a large aspect ratio. This prevents damaging plasma flux from entering the ALD volume into which a gaseous metal precursor is also pulsed. The self-limiting ALD reaction involving the heated substrate, the excited neutrals from the plasma gas, and the metal precursor produce an ultra-uniform, high quality film on the wafer. A batch configuration to simultaneously coat multiple wafers is also disclosed.

Abstract: Techniques are disclosed for methods and apparatuses for performing continuous-flow plasma enhanced atomic layer deposition (PEALD). Plasma gas, containing one or more component gases, is continuously flowed to a planar inductive coupled plasma source attached at an upper end of a cylindrical chamber. Plasma is separated from the ALD volume surrounding a wafer/substrate in the lower end of the chamber by a combination of a grounded metal plate and a ceramic plate. Each plate has a number of mutually aligned holes. The ceramic plate has holes with a diameter less than 2 Debye lengths and has a large aspect ratio. This prevents damaging plasma flux from entering the ALD volume into which a gaseous metal precursor is also pulsed. The self-limiting ALD reaction involving the heated substrate, the excited neutrals from the plasma gas, and the metal precursor produce an ultra-uniform, high quality film on the wafer. A batch configuration to simultaneously coat multiple wafers is also disclosed.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.

Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a substrate with an oxide film formed on a surface thereof; pre-processing a surface of the oxide film; and forming a nitride film containing carbon on the surface of the oxide film which has been pre-processed, by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas to the substrate; supplying a carbon-containing gas to the substrate; and supplying a nitrogen-containing gas to the substrate, or by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas to the substrate; and supplying a gas containing carbon and nitrogen to the substrate, or by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas containing carbon to the substrate; and supplying a nitrogen-containing gas to the substrate.

Abstract: An in-cell touch display apparatus which is proof against static electricity or the effects of its discharge includes a color filter structure, a thin film transistor (TFT) array structure with a touch electrode layer, and a ground portion. A liquid crystal layer is located between the color filter structure and the TFT array structure, a sealant is located between the color filter structure and the TFT array structure, and a protection layer is included. The protection layer directly contacts the sealant and the protection layer, the sealant, and the ground portion form a discharge path for discharging static electricity from the in-cell touch display apparatus.

Abstract: A semiconductor memory cell structure includes a substrate, a tunnel dielectric layer formed on the substrate, a blocking dielectric layer formed on the substrate, a control gate formed on the blocking dielectric layer, and a tri-layered charge-trapping layer sandwiched between the tunnel dielectric layer and the blocking dielectric layer. Furthermore, the tri-layered charge-trapping layer includes a bottom nitride layer formed on the substrate, a top nitride layer formed on the bottom nitride layer, and a middle nitride layer sandwiched between the bottom nitride layer and the top nitride layer. The bottom nitride layer includes a first nitride concentration, the top nitride layer includes a second nitride concentration, and the middle nitride layer includes a third nitride concentration. And the third nitride concentration is larger than the first nitride concentration and the second nitride concentration.

Abstract: Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa.

Abstract: A method of manufacturing a nitride semiconductor substrate includes providing a silicon substrate having a first surface and a second surface opposing each other, growing a nitride template on the first surface of the silicon substrate in a first growth chamber, in which a silicon compound layer is formed on the second surface of the silicon substrate in a growth process of the nitride template, removing the silicon compound layer from the second surface of the silicon substrate, growing a group III nitride single crystal on the nitride template in a second growth chamber, and removing the silicon substrate from the second growth chamber.

Abstract: A method of manufacturing a semiconductor device includes a process of forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes: supplying a precursor containing a predetermined element to the substrate; supplying a first reactant containing nitrogen and carbon to the substrate; supplying a second reactant containing nitrogen to the substrate; and supplying a third reactant containing oxygen to the substrate, wherein in the cycle, a supply amount of the second reactant is set to be smaller than a supply amount of the first reactant.

Abstract: A semiconductor device includes: a first nitride semiconductor layer, a second nitride semiconductor layer that is provided on the first nitride semiconductor layer and has a band gap larger than a band gap of the first nitride semiconductor layer, a gate electrode that is provided on the first nitride semiconductor layer, a first electrode that is electrically connected to the first nitride semiconductor layer, a second electrode disposed such that the gate electrode is positioned between the first electrode and the second electrode, and electrically connected to the first nitride semiconductor layer, and a first insulation layer that is provided between the gate electrode and the second electrode, disposed such that the second nitride semiconductor layer is positioned between the first nitride semiconductor layer and the first insulation layer, and including silicon oxide having an oxygen-to-silicon atomic ratio (O/Si) of 1.50 or more and 1.85 or less.

Abstract: A method for forming an electrically conductive oxide film (1) on a substrate (2), the method comprising the steps of, bringing the substrate (2) into a reaction space, forming a preliminary deposit on a deposition surface of the substrate (2) and treating the deposition surface with a chemical. The step of forming the preliminary deposit on the deposition surface of the substrate (2) comprises forming a preliminary deposit of transition metal oxide on the deposition surface and subsequently purging the reaction space. The step of treating the deposition surface with a chemical comprises treating the deposition surface with an organometallic chemical and subsequently purging the reaction space, to form oxide comprising oxygen, first metal and transition metal. The steps of forming the preliminary deposit and treating the deposition surface being alternately repeated such that a film (1) of electrically conductive oxide is formed on the substrate (2).

Abstract: A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, a gate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.

Abstract: A method for fabricating an electronic device that includes a metal-insulator-semiconductor (M-I-S) structure includes: providing a semiconductor layer; forming a primary insulation layer of a first thickness over the semiconductor layer; forming a reactive metal layer of a second thickness over the primary insulation layer, where the second thickness is greater than the first thickness; forming a primary capping layer of a third thickness over the reactive metal layer, where the third thickness is greater than the second thickness; and performing a thermal treatment.

Abstract: A method of integrating a silicon-oxide-nitride-oxide-silicon (SONOS) transistor into a complementary metal-oxide-silicon (CMOS) baseline process. The method includes the steps of forming the gate oxide layer of at least one metal-oxide-silicon (MOS) transistor prior to forming a non-volatile (NV) gate stack of the SONOS transistor.

Abstract: A method of manufacturing a semiconductor device, including forming a laminated film on a substrate by performing a cycle a first predetermined number of times. The cycle includes forming a first film which contains a predetermined element, boron, and nitrogen, and forming a second film which contains boron and nitrogen. A composition ratio of boron to nitrogen in the second film is different from that in the first film. The first film and the second film are laminated to form the laminated film.

Abstract: A method of manufacturing a semiconductor device, including forming a laminated film on a substrate by performing a cycle a first predetermined number of times. The cycle includes forming a first film which contains a predetermined element, boron, and nitrogen, and forming a second film which contains boron and nitrogen. A composition ratio of boron to nitrogen in the second film is different from that in the first film. The first film and the second film are laminated to form the laminated film.