In Atmosphere Containing Water Vapor (i.e., Wet Oxidation) Patents (Class 438/773)
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Patent number: 7153785Abstract: The present invention provides method of producing an annealed wafer wherein a silicon single crystal wafer produced by the Czochralski (CZ) method is subjected to a high temperature annealing in an atmosphere of an argon gas, a hydrogen gas, or a mixture gas thereof at a temperature of 1100–1350° C. for 10–600 minutes, during the annealing the silicon single crystal wafer is supported by a supporting jig only in a central side region of the wafer except for 5 mm or more from a peripheral end of the wafer, and before performing the high temperature annealing, a pre-annealing is performed at a temperature less than the temperature of the high temperature annealing to grow oxide precipitates. Thereby, there is provided a method of producing an annealed wafer wherein slip dislocations generated in a high temperature annealing can be suppressed even in the case of a silicon single crystal wafer having a large diameter of 300 mm or more, and provided the annealed wafer.Type: GrantFiled: August 23, 2002Date of Patent: December 26, 2006Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Norihiro Kobayashi, Masaro Tamatsuka, Takatoshi Nagoya, Wei Feig Qu
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Patent number: 7151060Abstract: A device for thermally treating semiconductor wafers having at least one silicon layer to be oxidized and a metal layer, preferably a tungsten layer, which is not to be oxidized. The inventive device comprises the following: at least one radiation source; a treatment chamber receiving the substrate, with at least one wall part located adjacent to the radiation sources and which is substantially transparent for the radiation of said radiation source; and at least one cover plate between the substrate and the wall part of the treatment chamber located adjacent to the radiation sources, the dimensions of said cover plate being selected such that it fully covers the transparent wall part of the treatment chamber in relation to the substrate in order to prevent material, comprising a metal, metal oxide or metal hydroxide such as tungsten, tungsten oxide or tungsten hydroxide, from said substrate from becoming deposited on or evaporating onto the transparent wall part of the treatment chamber.Type: GrantFiled: July 25, 2003Date of Patent: December 19, 2006Assignee: Mattson Thermal Products GmbHInventors: Georg Roters, Steffen Frigge, Sing Pin Tay, Yao Zhi Hu, Regina Hayn, Jens-Uwe Sachse, Erwin Schoer, Wilhelm Kegel
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Patent number: 7148103Abstract: Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit (1) and a second option technology electronic circuit (2) as functional parts of a system-on-chip, by: manufacturing the first electronic circuit (1) with a first conductive layer (6; 6) that is patterned by subjecting an exposed layer portion thereof to Reactive Ion Etching (RIE); manufacturing the second electronic circuit (2) with a second conductive layer (6; 8) that is patterned by subjecting an exposed layer portion thereof to RIE; providing a tile structure (25; 26); providing the tile structure (25; 26) with at least one dummy conductive layer (6; 8) produced in the same processing step as the second conductive layer (6; 8); and exposing the dummy conductive layer (6; 8), at least partially, to obtain an exposed dummy layer portion, and RIE-etching of that exposed portion too when the second (6; 8) conductive layer is subjected to RIE.Type: GrantFiled: October 16, 2002Date of Patent: December 12, 2006Assignee: Koninklijke Philips Electronics N.V.Inventors: Antonius Maria Petrus Johannes Hendriks, Guido Jozef Maria Dormans, Robertus Dominicus Joseph Verhaar
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Patent number: 7144766Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.Type: GrantFiled: August 8, 2005Date of Patent: December 5, 2006Assignee: Renesas Technology Corp.Inventors: Naoki Yamamoto, Hiroyuki Uchiyama, Norio Suzuki, Eisuke Nishitani, Shin'ichiro Kimura, Kazuyuki Hozawa
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Patent number: 7144826Abstract: The aim of the invention is the simple and economical production of a hydrogen-rich process gas from water vapour and hydrogen, whereby the proportion of water vapour to hydrogen may be precisely controllable and reproducible. Said aim is achieved, with a method and device for the production of a process gas for the treatment of substrates, in particular semiconductor substrates, in which the oxygen for formation of a process gas, comprising water vapour and hydrogen, is burnt in a hydrogen-rich environment in a combustion chamber.Type: GrantFiled: April 19, 2002Date of Patent: December 5, 2006Assignee: Mattson Thermal ProductsInventors: Georg Roters, Roland Mader, Helmut Sommer, Genrih Erlikh, Yehuda Pashut
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Patent number: 7125811Abstract: An oxidation method for a semiconductor process, which oxidizes a surface of a target substrate, includes heating a process container that accommodates the target substrate, and supplying hydrogen gas and oxygen gas into the process container while exhausting the process container. The oxidation method also includes causing the hydrogen gas and the oxygen gas to react with each other in the process container at a process temperature and a process pressure to generate water vapor, and oxidizing the surface of the target substrate by the water vapor. The process pressure is set at 2000 Pa (15 Torr) or more.Type: GrantFiled: August 25, 2004Date of Patent: October 24, 2006Assignee: Tokyo Electron LimitedInventors: Keisuke Suzuki, Toshiyuki Ikeuchi, Kazuhide Hasebe
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Patent number: 7122469Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improvedType: GrantFiled: August 4, 2005Date of Patent: October 17, 2006Assignee: Hitachi, Ltd.Inventors: Yoshikazu Tanabe, Isamu Asano, Makoto Yoshida, Naoki Yamamoto, Masayoshi Saito, Nobuyoshi Natsuaki
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Patent number: 7119033Abstract: Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.Type: GrantFiled: June 30, 2004Date of Patent: October 10, 2006Assignee: Micron Technology, Inc.Inventors: Li Li, Pai-Hung Pan
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Patent number: 7109131Abstract: The present invention relates generally to semiconductor fabrication. More particularly, the present invention relates to system and method of selectively oxidizing one material with respect to another material formed on a semiconductor substrate. A hydrogen-rich oxidation system for performing the process are provided in which innovative safety features are included to avoid the dangers to personnel and equipment that are inherent in working with hydrogen-rich atmospheres.Type: GrantFiled: June 6, 2003Date of Patent: September 19, 2006Assignee: Aviza Technology, Inc.Inventors: Robert B. Herring, Cole Porter, Travis Dodwell, Ed Nazareno, Chris Ratliff, Anindita Chatterji
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Patent number: 7094637Abstract: During a selective oxidation of gate structures that includes a polycrystalline silicon layer and a tungsten layer, which is known per se, a vapor deposition of tungsten oxide is prevented or at least greatly reduced by a special process. The gate structure is acted on by a hydrogen-containing, nonaqueous inert gas before and, if appropriate, after a treatment step with a hydrogen/water mixture.Type: GrantFiled: October 27, 2003Date of Patent: August 22, 2006Assignee: Infineon Technologies AGInventors: Olaf Storbeck, Wilhelm Kegel, Jens-Uwe Sachse, Michael Stadtmüller, Regina Hayn, Erwin Schoer, Georg Roters, Steffen Frigge
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Patent number: 7078354Abstract: After a first gate oxide film (302) is formed on a substrate (301), a nitride layer (303) is formed by a first oxynitriding process. The first gate oxide film is selectively removed from a thinner film part area of the substrate. A second gate oxide film forming process forms a second gate oxide film (305A) in the thinner film part area and a third gate oxide film (305B) in a thicker film part area. By executing second oxynitriding process, nitride layers (306A and 306B) are formed at the thinner and the thicker part areas.Type: GrantFiled: May 12, 2004Date of Patent: July 18, 2006Assignee: Elpida Memory, Inc.Inventor: Takayuki Kanda
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Patent number: 7071538Abstract: A semiconductor device includes a substrate that further includes source, drain and channel regions. The device may further include a bottom oxide layer formed upon the substrate, a charge storage layer formed upon the bottom oxide layer, and a steam oxide layer thermally grown upon the charge storage layer. The device may also include an alumina oxide layer formed upon the steam oxide layer and a gate electrode formed upon the alumina oxide layer.Type: GrantFiled: December 10, 2004Date of Patent: July 4, 2006Assignee: Spansion,LLCInventors: Hidehiko Shiraiwa, Harpreet K. Sachar, Mark Randolph, Wei Zheng
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Patent number: 7071120Abstract: Disclosed is a process of treating semiconductor substrates, including the production of pure water, a method of producing the pure water for semiconductor fabrication, and a water-producing apparatus. Ammonia is catalytically oxidized in a catalytic conversion reactor to form pure water. The water is then supplied to a semiconductor fabrication process. The water-producing apparatus comprises a housing surrounding a catalytic material for adsorbing ammonia, an ammonia and oxidant source, each in communication with the housing, and an outlet for reaction products. The outlet is connected to a semiconductor processing apparatus. According to preferred embodiments of the invention, the apparatus can be a catalytic tube reactor, a fixed bed reactor or a fluidized bed reactor.Type: GrantFiled: March 18, 2003Date of Patent: July 4, 2006Assignee: Micron Technology, Inc.Inventor: Don Carl Powell
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Patent number: 7053007Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: May 19, 2005Date of Patent: May 30, 2006Assignee: Renesas Technology Corp.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 7049187Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.Type: GrantFiled: October 31, 2001Date of Patent: May 23, 2006Assignee: Renesas Technology Corp.Inventors: Naoki Yamamoto, Hiroyuki Uchiyama, Norio Suzuki, Eisuke Nishitani, Shin'ichiro Kimura, Kazuyuki Hozawa
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Patent number: 7015111Abstract: A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The method comprises doping transistor source and drain regions to different doping levels, then performing a transistor sidewall oxidation using a particular process to modify the gate oxide thickness. The oxide forms at a faster rate along the source sidewall than along the drain sidewall. By using ranges within the oxidation environment described, a source side gate oxide having a variable and selectable thickness may be formed, while forming a drain-side oxide which has a single thickness where a thinner layer is desirable. This leads to improved optimization of key competing requirements of a flash memory cell, such as program and erase performance, while maintaining sufficient long-term data retention. The process may allow improved cell scalability, shortened design time, and decreased manufacturing costs.Type: GrantFiled: October 28, 2003Date of Patent: March 21, 2006Assignee: Micron Technology, Inc.Inventors: Paul J. Rudeck, Don C. Powell
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Patent number: 7008880Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: February 10, 2004Date of Patent: March 7, 2006Assignee: Renesas Technology Corp.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 7001851Abstract: This invention provides a steam oxidation method of a matter to be oxidized with proper controllability and reproducibility. It is provided a steam oxidation method, where a semiconductor substrate (a matter to be oxidized) is housed in a steam oxidation reactor and is subjected to: a first step of supplying N2 gas to the reactor housing the semiconductor substrate and substituting the inside of the reactor with N2 gas; a second step of stopping supply of the N2 gas and supplying a steam-accompanied N2 gas, in which the N2 gas is accompanied with steam, to the reactor; a third step of increasing a temperature of the semiconductor substrate to 450° C. (a steam oxidation temperature) while supplying the steam-accompanied N2 gas; and a fourth step of holding the semiconductor substrate for a predetermined time at 450° C.Type: GrantFiled: June 18, 2004Date of Patent: February 21, 2006Assignee: Sony CorporationInventors: Yoshiyuki Tanaka, Hironobu Narui, Yoshinori Yamauchi, Yuichi Kuromizu, Yoshiaki Watanabe
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Patent number: 6998326Abstract: The method for manufacturing a shallow trench isolation (STI) in a semiconductor device with an enhanced gap-fill property and without a detrimental effect of fluorine by introducing a two-stage thermal process. The method includes steps of: preparing a semiconductor substrate obtained by a predetermined process on which a pad oxide and a pad nitride are formed on predetermined locations thereof; forming a trench structure in the semiconductor substrate; forming a hydrogen (H2)-based high density plasma (HDP) oxide layer over a first resultant structure; forming a nitrogen trifluoride (NF3)-based HDP oxide layer into the trench structure with a predetermined depth; carrying out a two-stage thermal process for removing fluorine in the NF3-based HDP oxide layer; and forming a helium (He)-based HDP oxide layer over a second resultant structure.Type: GrantFiled: December 16, 2003Date of Patent: February 14, 2006Assignee: Hynix Semiconductor Inc.Inventor: Jae-Hong Kim
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Patent number: 6987069Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.Type: GrantFiled: April 12, 2004Date of Patent: January 17, 2006Assignee: Hitachi, Ltd.Inventors: Yoshikazu Tanabe, Isamu Asano, Makoto Yoshida, Naoki Yamamoto, Masayoshi Saito, Nobuyoshi Natsuaki
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Patent number: 6962881Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: February 10, 2004Date of Patent: November 8, 2005Assignee: Renesas Technology Corp.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 6962880Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: February 10, 2004Date of Patent: November 8, 2005Assignee: Renesas Technology Corp.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 6936550Abstract: A manufacturing method for a semiconductor integrated circuit device comprises forming, over a gate insulating film which has been formed over the main surface of a single crystal silicon substrate to have an effective film thickness less than 5 nm in terms of SiO2, a W film as a gate electrode material, and heat treating the silicon substrate in a water-vapor- and hydrogen-containing gas atmosphere having a water vapor/hydrogen partial pressure ratio set at a ratio permitting oxidation of silicon without substantial oxidation of the W film, whereby defects of the gate insulating film right under the W film are repaired. In this way, in a MISFET having a metal gate electrode formed over a ultra-thin gate insulating film having an effective film thickness less than 5 nm in terms of SiO2, defects of the gate insulating film can be repaired without oxidizing the metal gate electrode.Type: GrantFiled: January 21, 2004Date of Patent: August 30, 2005Assignee: Hitachi, Ltd.Inventors: Naoki Yamamoto, Yoshikazu Tanabe
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Patent number: 6905980Abstract: A semiconductor device is produced by forming a gate oxide film on a silicon substrate, forming a gate electrode on the gate oxide film, forming a nitrogen-containing oxide film on the silicon substrate and gate electrode in an N2O gas or an NO gas, forming a BPSG film on the nitrogen-containing oxide film, and carrying out a reflow process on the BPSG film in a water vapor atmosphere. During the reflow process, the nitrogen-containing oxide film that has no hydrogen atoms prevents the penetration and diffusion of oxygen and hydrogen atoms into the silicon substrate and gate electrode, thereby preventing the oxidization of the silicon substrate and gate electrode. No hydrogen atoms diffuse into the gate oxide film, and therefore, the reliability of the gate oxide film is secured.Type: GrantFiled: July 24, 2003Date of Patent: June 14, 2005Assignee: Kabushiki Kaisha ToshibaInventor: Mikio Wakamiya
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Patent number: 6900111Abstract: A method for forming a reliable and ultra-thin oxide layer, such as a gate oxide layer of an MOS transistor, comprises an annealing step immediately performed prior to oxidizing a substrate. The annealing step is performed in an inert gas ambient to avoid oxidation of the semiconductor surface prior to achieving a required low oxidizing temperature. Preferably, the annealing step and the oxidizing step are carried out as an in situ process, thereby minimizing the thermal budget of the overall process.Type: GrantFiled: April 19, 2002Date of Patent: May 31, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Karsten Wieczorek, Stephan Krügel, Falk Graetsch
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Patent number: 6900144Abstract: A film-forming surface reforming method includes the steps of bringing a gas or an aqueous solution containing ammonia, hydrazine, an amine, an amino compound or a derivative thereof into contact with the film-forming surface before an insulating film is formed on the film-forming surface, and bringing a gas or an aqueous solution containing Hydrogen peroxide, ozone, Oxygen, nitric acid, sulfuric acid or a derivative thereof into contact with the film-forming surface.Type: GrantFiled: March 15, 2001Date of Patent: May 31, 2005Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.Inventors: Kazuo Maeda, Setsu Suzuki, Takayoshi Azumi, Kiyotaka Sasaki
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Patent number: 6893980Abstract: According to the manufacturing method of the semiconductor device of the present invention, an oxide film is formed on a metal film formed on a main surface of a semiconductor substrate by exposing the metal film to the oxidizing gas. The oxide film is then reduced in a reducing atmosphere, and a protection film is formed on the surface of the metal film reduced in the reducing step. In this manner, the damage to the surface of the metal film can be prevented.Type: GrantFiled: November 8, 2000Date of Patent: May 17, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Yasushi Akasaka, Kazuaki Nakajima, Kiyotaka Miyano, Kyoichi Suguro
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Patent number: 6890867Abstract: A transistor gate is formed which comprises semiconductive material and conductive metal. Source/drain regions are formed proximate the transistor gate. In one implementation, the transistor gate and source/drain regions are exposed to a gas mixture comprising H2O, H2, a noble gas and N2 under conditions effective to oxidize outer surfaces of the source/drain regions. The N2 is present in the gas mixture at greater than 0% and less than or equal to 20.0% by volume. In one implementation, the transistor gate and source/drain regions are exposed to a gas mixture comprising H2O, H2, and an inert gas under conditions effective to oxidize outer surfaces of the source/drain regions. The conditions comprise a pressure of greater than room ambient pressure. Other aspects and implementations are contemplated.Type: GrantFiled: February 25, 2003Date of Patent: May 10, 2005Assignee: Micron Technology, Inc.Inventor: Don Carl Powell
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Patent number: 6887797Abstract: An apparatus and method of forming an oxynitride insulating layer on a substrate performed by putting the substrate at a first temperature within the main chamber of a furnace, exposing the substrate to a nitrogen containing gas at a second temperature which is higher than the first temperature, and growing the oxynitride layer on the substrate within the main chamber in the presence of post-combusted gases. The higher temperature nitrogen containing gases are combusted in a chamber outside the main chamber. The higher temperature is in the range of 800 to 1200° C., and preferably 950° C. In a second embodiment, distributed N2O gas injectors within the main chamber deliver the nitrogen containing gas. The nitrogen containing gas is pre-heated outside the chamber. The nitrogen containing gas is then delivered to a gas manifold that splits the gas flow and directs the gas to a number of gas injectors, preferably two to four injectors within the main process tube.Type: GrantFiled: July 19, 2002Date of Patent: May 3, 2005Assignee: International Business Machines CorporationInventors: Douglas A. Buchanan, Evgeni P. Gousev, Carol J. Heenan, Wade J. Hodge, Steven M. Shank, Patrick R. Varekamp
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Patent number: 6869892Abstract: A method of oxidizing work pieces according to the present invention comprises the steps of: containing a plurality of work pieces W in a processing vessel 22 which has a predetermined length and is capable forming a vacuum therein, oxidizing surfaces of the work pieces in an atmosphere including active oxygen species and active hydroxyl species which are generated by supplying an oxidative gas and a reductive gas into the processing vessel to interact the gases. The oxidative gas and the reductive gas are respectively supplied into the processing vessel in the longitudinal direction. Parts of the reductive gas are additionally supplied from at least two or more independently controlled gas nozzles located at separate locations in the longitudinal direction of the processing vessel. The gas flow rate through each nozzle is set depending on any combination of the work pieces composed of product wafers, dummy wafers, and monitor wafers in the processing vessel.Type: GrantFiled: January 30, 2004Date of Patent: March 22, 2005Assignees: Tokyo Electron Limited, Intel CorporationInventors: Keisuke Suzuki, Toshiyuki Ikeuchi, Kimiya Aoki, David Paul Brunco, Steven Robert Soss, Anthony Dip
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Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O and O3
Patent number: 6864125Abstract: This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous oxide (N2O) and ozone (O3). The presence of O3 in the oxidizing ambiance greatly enhances the oxidation rate compared to an ambiance in which N2O is the only oxidizing agent. In addition to enhancing the oxidation rate of silicon, it is hypothesized that the presence of O3 interferes with the growth of a thin silicon oxynitride layer near the interface of the silicon dioxide layer and the unreacted silicon surface which makes oxidation in the presence of N2O alone virtually self-limiting. The presence of O3 in the oxidizing ambiance does not impair oxide reliability, as is the case when silicon is oxidized with N2O in the presence of a strong, fluorine-containing oxidizing agent such as NF3 or SF6.Type: GrantFiled: August 18, 2003Date of Patent: March 8, 2005Assignee: Micron Technology, Inc.Inventors: Gurtej Singh Sandhu, Randhir P S Thakur -
Patent number: 6864191Abstract: The present invention provides a hydrogen barrier layer able to prevent diffusions of hydrogen into a capacitor and a method for fabricating a semiconductor device having the same. The inventive method includes the steps of: depositing a zirconium-titanium oxide layer containing zirconium, titanium and oxygen on a substrate; and performing a reforming process for densifying the zirconium-titanium oxide layer and for stuffing oxygen in a surface of the zirconium-titanium oxide layer.Type: GrantFiled: December 27, 2002Date of Patent: March 8, 2005Assignee: Hynix Semiconductor Inc.Inventor: Dong-Soo Yoon
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Patent number: 6855642Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: April 28, 2003Date of Patent: February 15, 2005Assignee: Renesas Technology Corp.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 6841432Abstract: A semiconductor device comprising at least two thin film transistors on a substrate having an insulating surface thereon, provided that the thin film transistors are isolated by oxidizing the outer periphery of the active layer of each of the thin film transistors to the bottom to provide an oxide insulating film.Type: GrantFiled: May 28, 1999Date of Patent: January 11, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yasuhiko Takemura, Hiroki Adachi
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Patent number: 6833330Abstract: A method of making a semiconductor structure includes sealing a gate layer by wet oxidation. The gate layer is on a substrate containing isolation regions. Semiconductor devices prepared from the semiconductor structure exhibits reduced inverse narrow width effects.Type: GrantFiled: December 18, 2003Date of Patent: December 21, 2004Assignee: Cypress Semiconductor CorporationInventors: Jeffrey T. Watt, Kedar Patel
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Patent number: 6831022Abstract: A system, apparatus and/or method is provided for removing water vapor from a wafer processing chamber generated as a byproduct of wafer processing. A water vapor trap is used to collect the water vapor byproduct from the processing chamber interior. The water vapor trap has at least a portion thereof in communication with an interior of the processing chamber for collection of the water vapor and another portion thereof in communication with an exterior of the processing chamber. The portions are movable with respect to the interior and exterior of the processing chamber such that the portions may switch places. This allows the processing chamber to be in at least a substantially continuous mode of operation while still providing for the removal of water vapor byproduct via the water vapor trap. The “used” portion of the water vapor trap is regenerated while the “clean” portion is collecting water vapor.Type: GrantFiled: June 26, 2003Date of Patent: December 14, 2004Assignee: LSI Logic CorporationInventors: Robert D. Broyles, Michael J. Berman
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Patent number: 6830973Abstract: Using a rapid thermal oxidation device, the top and side surfaces of a floating gate electrode are oxidized by In Situ Steam Generation (ISSG), wherein oxygen to which about 0.5 to 33% hydrogen has been added is introduced directly into a chamber with a temperature of approximately 900 to 1100° C. and a pressure of approximately 1,000 to 2,000 Pa, in order to generate water vapor from the introduced hydrogen and oxygen on a heated semiconductor substrate. Thus, an insulating film made of silicon oxide is formed on the surface of the floating gate electrode.Type: GrantFiled: September 11, 2002Date of Patent: December 14, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiromasa Fujimoto, Fumihiko Noro, Masataka Kusumi
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Patent number: 6824757Abstract: The invention relates to a method for generating ultrapure steam by oxidation of hydrogen in a closed torch with separate feed lines for hydrogen and oxygen and a discharge line for discharging the steam which is formed to a process chamber. The invention also relates to an arrangement for carrying out the method. The invention is intended to provide a method which is simple to implement and an arrangement for generating ultrapure steam which results in a significantly extended injector service life. For this purpose, oxygen and water are fed to the torch in a slightly superstoichiometric ratio, and pure additional oxygen is admixed with the steam formed during the combustion, when it enters the process chamber, in order to generate a considerable excess of oxygen in the steam. The associated device comprises a torch with feed lines for feeding hydrogen and oxygen to the closed torch and a discharge line leading to a process chamber. Each feed line being assigned a mass flow controller.Type: GrantFiled: March 14, 2003Date of Patent: November 30, 2004Assignee: Infineon Technologies AGInventor: Marcel Tognetti
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Publication number: 20040219800Abstract: A method for generating an oxide layer on a substrate such as a silicon wafer used for the manufacturing of microchips. The substrate is placed in an oven and an oxidising medium comprising oxygen is fed to the oven. To control the growth of the oxide layer the oxygen partial pressure in the exhaust is determined and, depending on the measured value, the feed of the components of the oxidising mediums are adjusted, so that the oxygen partial pressure in the oxygen gases is kept constant. The method allows the reproducible formation of oxide layers with a defined layer thickness.Type: ApplicationFiled: June 21, 2004Publication date: November 4, 2004Inventor: Marcel Tognetti
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Publication number: 20040209483Abstract: The aim of the invention is to stop the progression of a lateral oxidation of a layer of a multi-layer substrate at a defined point. To achieve this aim, the invention provides a method for thermally treating a substrate that comprises several layers, especially a semiconductor wafer, according to which a substrate layer that is covered from above and from below is oxidized from the lateral edges thereof to the center in such a manner that a defined center portion is not oxidized. The inventive method comprises the following steps: heating the substrate in a process chamber to a defined treatment temperature; introducing a hydrogen-rich water vapor into the process chamber for a defined period of time; and introducing dry oxygen or an oxygen-rich water vapor into the process chamber once the defined period of time has expired. The hydrogen-rich water vapor can be introduced into the process chamber either before, during and/or after the substrate is heated.Type: ApplicationFiled: February 18, 2004Publication date: October 21, 2004Inventors: Hin Yiu Chung, Georg Roters
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Patent number: 6806144Abstract: A method and apparatus for improving a uniformity of a thermally grown silicon dioxide layer including thermally growing a layer over the exposed silicon portions including silicon dioxide according to a thermal oxide growing process; exposing the gas reactant feed lines to reactant gases during at least one of the step of thermally growing a layer and a cleaning process following the step of thermally growing a layer; and, purging the gas flow pathways to bypass the reactor chamber with at least one purge gas source including an inert gas to remove residual reactant gas contaminants to improve a subsequently thermally grown silicon dioxide layer.Type: GrantFiled: August 13, 2002Date of Patent: October 19, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Pu-Fan Chen, Chao-Po Lu, Hsi-Shen Chuang, Yi-Jen Chen, Chin-Tsai Chen, Tsukada Kazunori
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Publication number: 20040198067Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.Type: ApplicationFiled: April 12, 2004Publication date: October 7, 2004Inventors: Yoshikazu Tanabe, Isamu Asano, Makoto Yoshida, Naoki Yamamoto, Masayoshi Saito, Nobuyoshi Natsuaki
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Patent number: 6797644Abstract: Using deuterium oxygen during stream oxidation forms an oxidizing vapor. Since deuterium is chemically similar to hydrogen, the oxidation process takes place normally and the silicon-silicon oxide interface is concurrently saturated with deuterium. Saturating the interface with deuterium reduces the interface trap density thereby reducing channel hot carrier degradation.Type: GrantFiled: July 16, 2001Date of Patent: September 28, 2004Assignee: Texas Instruments IncorporatedInventors: Victor Watt, Beth Walden, Brian K. Kirkpatrick, Edmund G. Russell
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Patent number: 6787479Abstract: Disclosed is a process of treating semiconductor substrates, including the production of pure water, a method of producing the pure water for semiconductor fabrication, and a water-producing apparatus. Ammonia is catalytically oxidized in a catalytic conversion reactor to form pure water. The water is then supplied to a semiconductor fabrication process. The water-producing apparatus comprises a housing surrounding a catalytic material for adsorbing ammonia, an ammonia and oxidant source, each in communication with the housing, and an outlet for reaction products. The outlet is connected to a semiconductor processing apparatus. According to preferred embodiments of the invention, the apparatus can be a catalytic tube reactor, a fixed bed reactor or a fluidized bed reactor.Type: GrantFiled: April 18, 2002Date of Patent: September 7, 2004Assignee: Micron Technology, Inc.Inventor: Don Carl Powell
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Patent number: 6784116Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.Type: GrantFiled: January 31, 2003Date of Patent: August 31, 2004Assignee: Hitachi, Ltd.Inventors: Yoshikazu Tanabe, Isamu Asano, Makoto Yoshida, Naoki Yamamoto, Masayoshi Saito, Nobuyoshi Natsuaki
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Patent number: 6770538Abstract: Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.Type: GrantFiled: August 22, 2001Date of Patent: August 3, 2004Assignee: Micron Technology, Inc.Inventors: Li Li, Pai-Hung Pan
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Publication number: 20040132316Abstract: An in-situ ultra dilute ammonia nitridation process and apparatus of the following ultra-thin chemically tailored gate dielectrics: DCE/O2 (Trans 1,2-Dichloroethylene) based ultra-thin gate dielectric; Nitric Oxide (NO) based ultra-thin gate dielectric that has been re-oxidized via a DCE/O2 (Trans 1,2-Dichloroethylene) process; “dry-wet” DCE (Trans 1,2-Dichloroethylene)/O2-H2O/O2) based ultra-thin gate dielectric; and ultra dilute, less than 1E-7 moles NH3/mm2, nitridation of an ultra-thin gate dielectric. A vertical diffusion furnace (VDF) is provided to process the same. The ultra-thin chemically tailored gate dielectrics generated in a VDF with ultra-dilute NH3, below 1E-7 moles NH3/mm2, in-situ nitridation show a performance comparable or better to traditional ex-situ rapid thermal anneal (RTA) processing techniques for 90 nm CMOS technology.Type: ApplicationFiled: January 8, 2003Publication date: July 8, 2004Inventors: Christine M. Finnie, Pauline N. Jacob, Nick Lindert, Keith M. Jackson, Kirk Althoff, Jack Hwang, Jack Kavalieros, James R. Mueller
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Publication number: 20040087093Abstract: In a semiconductor device using a silicon carbide substrate (1), the object of the present invention is to provide a method of manufacturing a semiconductor device that is a buried channel region type transistor having hot-carrier resistance, high punch-through resistance and high channel mobility. This is achieved by using a method of manufacturing a buried channel type transistor using a P-type silicon carbide substrate that includes a step of forming a buried channel region, a source region and a drain region, a step of forming a gate insulation layer after the step of forming the buried channel region, source region and drain region, and a step of exposing the gate insulation layer to an atmosphere containing water vapor at a temperature of 500° C. or more after the step of forming the gate insulation layer. The gate insulation layer is formed by a thermal oxidation method using dry oxygen.Type: ApplicationFiled: December 30, 2003Publication date: May 6, 2004Inventors: Kenji Fukuda, Kazuo Arai, Junji Senzaki, Shinsuke Harada, Ryoji Kosugi, Kazuhiro Adachi, Seiji Suzuki
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Patent number: 6723665Abstract: In a gas-phase treating process of a semiconductor wafer using hydrogen, there is provided a technique for safely eliminating the hydrogen in an exhaust gas discharged from a gas-phase treating apparatus. The profile at the end portions of the side walls of gate electrodes of a poly-metal structure is improved by forming the gate electrodes over a semiconductor wafer IA having a gate oxide film and then by supplying the semiconductor wafer 1A with a hydrogen gas containing a low concentration of water, as generated from hydrogen and oxygen by catalytic action, to oxidize the principal face of the semiconductor wafer 1A selectively. After this, the hydrogen in the exhaust gas, as discharged from an oxidizing furnace, is completely converted into water by causing it to react with oxygen by a catalytic method.Type: GrantFiled: April 2, 2003Date of Patent: April 20, 2004Assignees: Renesas Technology Corp., Hitachi Tokyo Electronics Co., Ltd.Inventors: Yoshikazu Tanabe, Toshiaki Nagahama, Nobuyoshi Natsuaki, Yasuhiko Nakatsuka
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Patent number: RE38674Abstract: A novel process for forming a robust, sub-100 Å oxide is disclosed. Native oxide growth is tightly controlled by flowing pure nitrogen during wafer push and nitrogen with a small amount of oxygen during temperature ramp and stabilization. First, a dry oxidation is performed in oxygen and 13% trichloroethane. Next, a wet oxidation in pyrogenic steam is performed to produce a total oxide thickness of approximately 80 Å. The oxide layer formed is ideally suited for use as a high integrity gate oxide below 100 Å. The invention is particularly useful in devices with advanced, recessed field isolation where sharp silicon edges are difficult to oxidize. For an oxide layer of more than 100 Å, a composite oxide stack is used which comprises 40-90 Å of pad oxide formed using the above novel process, and 60-200 Å of deposited oxide.Type: GrantFiled: September 14, 1995Date of Patent: December 21, 2004Assignee: Intel CorporationInventors: Robert S. K. Chau, William L. Hargrove, Leopoldo D. Yau