Reaction With Silicon Semiconductive Region (e.g., Oxynitride Formation, Etc.) Patents (Class 438/769)
  • Patent number: 11264253
    Abstract: There is provided a technique includes: a process chamber in which a substrate is processed; a plurality of microwave supply sources configured to supply predetermined microwaves for heating the substrate in the process chamber; and a controller configured to control the microwave supply sources such that while keeping constant a sum of outputs of the microwaves respectively supplied to the substrate from the plurality of microwave supply sources, at least one of the plurality of microwave supply sources is turned off, and periods in which the at least one of the plurality of microwave supply sources is turned off are different from each other.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 1, 2022
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Shinya Sasaki, Yukitomo Hirochi, Noriaki Michita
  • Patent number: 11205654
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yi Hu, Ramey M. Abdelrahaman, Narula Bilik, Daniel Billingsley, Zhenyu Bo, Joan M. Kash, Matthew J. King, Andrew Li, David Neumeyer, Wei Yeeng Ng, Yung K. Pak, Chandra Tiwari, Yiping Wang, Lance Williamson, Xiaosong Zhang
  • Patent number: 10790398
    Abstract: Kesterite photovoltaic devices having a back surface field layer are provided. In one aspect, a method of forming a photovoltaic device includes: forming a complete photovoltaic device having a substrate, an electrically conductive layer on the substrate, an absorber layer on the electrically conductive layer, a buffer layer on the absorber layer, and a transparent front contact on the buffer layer; removing the substrate and the electrically conductive layer from the complete photovoltaic device to expose a backside surface of the absorber layer; forming a passivating layer on the backside surface of the absorber layer; and forming a high work function back contact on the passivating layer. A photovoltaic device having a passivating layer is also provided.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Priscilla D. Antunez, Bruce A. Ek, Richard A. Haight, Ravin Mankad, Saurabh Singh, Teodor K. Todorov
  • Patent number: 10663818
    Abstract: A liquid crystal panel of a liquid crystal device as an electro-optic device includes a recessed portion provided in a pixel in a base substrate, a scanning line as a first light-shielding layer and a data line as a second light-shielding layer provided on the base substrate, the scanning line and the data line being disposed sequentially from a base substrate side in a thickness direction of the base substrate with a space between the scanning line and the data line, in a thickness direction of the base substrate, a transistor provided between the scanning line and the data line, a first insulation layer covering the data line, and disposed along the recessed portion, and a second insulation layer being in contact with the first insulation layer, and having a refractive index n2 that is higher than a refractive index n1 of the first insulation layer.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: May 26, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Mitsutaka Ohori
  • Patent number: 10541127
    Abstract: A material layer, a semiconductor device including the material layer, and methods of forming the material layer and the semiconductor device are provided herein. A method of forming a SiOCN material layer may include supplying a silicon source onto a substrate, supplying a carbon source onto the substrate, supplying an oxygen source onto the substrate, supplying a nitrogen source onto the substrate, and supplying hydrogen onto the substrate. When a material layer is formed according to a method of the present inventive concepts, a material layer having a high tolerance to wet etching and/or good electric characteristics may be formed, and may even be formed when the method is performed at a low temperature.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: January 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-suk Tak, Gi-gwan Park, Jin-bum Kim, Bon-young Koo, Ki-yeon Park, Tae-jong Lee
  • Patent number: 10475854
    Abstract: A method of manufacturing a display device, including: providing a display element layer on a substrate; forming a thin film encapsulation layer covering the display element layer; aging the thin film encapsulation layer by using a light source emitting artificial sunlight; and forming a window on the aged thin film encapsulation layer.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Heon Sik Ha, Kwang Hyun Kim, Sang Wook Lee
  • Patent number: 10403760
    Abstract: A novel oxide semiconductor film. An oxide semiconductor film with a small amount of defects. An oxide semiconductor film in which a peak value of the density of shallow defect states at an interface between the oxide semiconductor film and an insulating film is small. The oxide semiconductor film includes In, M (M is Al, Ga, Y, or Sn), Zn, and a region in which a peak value of a density of shallow defect states is less than 1E13 per square cm per volt.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: September 3, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kenichi Okazaki, Junichi Koezuka, Toshimitsu Obonai, Satoru Saito, Shunpei Yamazaki
  • Patent number: 10381241
    Abstract: There is provide a technique that includes preparing a substrate, in which an insulating film is formed on a pattern having an aspect ratio of 20 or greater and a process target film having a thickness of 200 ? or smaller is formed on the insulating film, in a process chamber; raising a temperature of the substrate to a first temperature with an electromagnetic wave; crystallizing the process target film for a first process time period while maintaining the first temperature; raising the temperature of the substrate to a second temperature, which is higher than the first temperature, with the electromagnetic wave, after the act of crystallizing the process target film; and repairing a crystal defect of the crystallized process target film for a second process time period, which is shorter than the first process time period, while maintaining the second temperature.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: August 13, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Kazuhiro Yuasa, Noriaki Michita
  • Patent number: 9978587
    Abstract: A technique includes forming a film containing a first element, a second element and carbon on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing supplying a first precursor having chemical bonds between the first elements to a substrate, supplying a second precursor having chemical bonds between the first element and carbon without having the chemical bonds between the first elements to the substrate, and supplying a first reactant containing the second element to the substrate.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: May 22, 2018
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Satoshi Shimamoto, Yoshiro Hirose, Ryuji Yamamoto
  • Patent number: 9502403
    Abstract: A method for fabricating a semiconductor device includes providing a semiconductor substrate, forming on the semiconductor substrate a dummy gate interface layer and a dummy gate of a core device and a gate interface layer and a dummy gate of an IO device, removing the dummy gates of the core and IO devices, removing the dummy gate interface layer of the core device, forming a gate interface layer in the original location of the removed dummy gate interface layer, forming a high-k dielectric layer each on the gate interface layer of the core and IO devices, and submitting the semiconductor substrate to a high-pressure fluorine annealing. The high-pressure fluorine annealing causes the gate interface layer and the high-k dielectric layer of the core and IO devices to be doped with fluoride ions.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: November 22, 2016
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Xinyun Xie
  • Patent number: 9355849
    Abstract: A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stochiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: May 31, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Fredrick B. Jenne, Sam G. Geha
  • Patent number: 9117661
    Abstract: A method for selective oxidation of silicon containing materials in a semiconductor device is disclosed and claimed. In one aspect, a rapid thermal processing apparatus is used to selectively oxidize a substrate by in-situ steam generation at high pressure in a hydrogen rich atmosphere. Other materials, such as metals and barrier layers, in the substrate are not oxidized.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: August 25, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yoshitaka Yokota, Norman L. Tam, Balasubramanian Ramachandran, Martin John Ripley
  • Patent number: 9111812
    Abstract: Disclosed is a flexible display device and method of manufacturing the same in which a method of manufacturing a flexible display device may include forming a sacrificial layer on a support substrate, the sacrificial layer including at least one barrier layer and a separation layer, the barrier layer having a higher hydrogen content than that of the separation layer; forming a first flexible substrate on the support substrate provided with the sacrificial layer; forming a plurality of device elements on the first flexible substrate; and irradiating a laser onto the sacrificial layer through the support substrate and separating the support substrate from the first substrate.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: August 18, 2015
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Yong Woo Yoo, Seung Hyun Lee
  • Patent number: 9093528
    Abstract: The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) stress compensation layers that reduce stress on one or more underlying semiconductor devices, and an associated method of formation. In some embodiments, the integrated chip has a semiconductor substrate with one or more semiconductor devices. A stressed element is located within a back-end-of-the-line stack at a position overlying the one or more semiconductor devices. A stressing layer is located over the stressed element induces a stress upon the stressed element. A stress compensation layer, located over the stressed element, provides a counter-stress to reduce the stress induced on the stressed element by the stressing layer. By reducing the stress induced on the stressed element, stress on the semiconductor substrate is reduced, improving uniformity of performance of the one or more semiconductor devices.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: July 28, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ming Peng, Chen-Chung Lai, Kang-Min Kuo, Bor-Zen Tien
  • Publication number: 20150147891
    Abstract: A thin film having a high resistance to HF and a low dielectric constant is formed with high productivity. A method of manufacturing a semiconductor device, includes performing a cycle a predetermined number of times, the cycle including: (a) supplying a source gas containing a predetermined element, carbon and a halogen element and having a chemical bond between the predetermined element and carbon to a substrate; and (b) supplying a reactive gas including a borazine compound to the substrate, wherein the cycle is performed under a condition where a borazine ring structure in the borazine compound and at least a portion of the chemical bond between the predetermined element and carbon in the source gas are preserved to form a thin film including the borazine ring structure and the chemical bond between the predetermined element and carbon on the substrate.
    Type: Application
    Filed: November 25, 2014
    Publication date: May 28, 2015
    Inventors: Atsushi SANO, Yoshiro HIROSE
  • Patent number: 9040411
    Abstract: A method of forming a carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. The dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: May 26, 2015
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Alfred Grill, Joshua L. Herman, Son Nguyen, E. Todd Ryan, Hosadurga K. Shobha
  • Patent number: 9029228
    Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: May 12, 2015
    Assignees: SunEdision Semiconductor Limited (UEN201334164H), Kansas State University Research Foundation
    Inventors: Michael R. Seacrist, Vikas Berry, Phong Tuan Nguyen
  • Patent number: 9006762
    Abstract: An organic light-emitting device including a substrate, an anode layer on the substrate, the anode layer including WOxNy (2.2?x?2.6 and 0.22?y?0.26), an emission structure layer on the anode layer, and a cathode layer on the emission structure layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 14, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chang-Ho Lee, Hee-Joo Ko, Il-Soo Oh, Hyung-Jun Song, Se-Jin Cho, Jin-Young Yun, Bo-Ra Lee, Young-Woo Song, Jong-Hyuk Lee, Sung-Chul Kim
  • Patent number: 8999811
    Abstract: An insulating layer containing a silicon peroxide radical is used as an insulating layer in contact with an oxide semiconductor layer for forming a channel. Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Toshinari Sasaki, Kosei Noda, Mizuho Sato
  • Publication number: 20150093913
    Abstract: A method of manufacturing a semiconductor device includes supplying a precursor gas to a substrate; supplying a reaction gas to a plasma generation region; supplying high frequency power to the plasma generation region; and generating plasma of the reaction gas by adjusting a pressure of the plasma generation region to a first pressure before the reaction gas is supplied and adjusting the pressure of the plasma generation region to a second pressure lower than the first pressure while the reaction gas and the high frequency power are supplied.
    Type: Application
    Filed: September 24, 2014
    Publication date: April 2, 2015
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Kazuyuki TOYODA, Yukitomo HIROCHI, Tetsuo YAMAMOTO, Kazuhiro MORIMITSU, Tadashi TAKASAKI
  • Patent number: 8993453
    Abstract: A method for fabricating a nonvolatile charge trap memory device and the device are described. In one embodiment, the method includes providing a substrate in an oxidation chamber, wherein the substrate comprises a first exposed crystal plane and a second exposed crystal plane, and wherein the crystal orientation of the first exposed crystal plane is different from the crystal orientation of the second exposed crystal plane. The substrate is then subjected to a radical oxidation process to form a first portion of a dielectric layer on the first exposed crystal plane and a second portion of the dielectric layer on the second exposed crystal plane, wherein the thickness of the first portion of the dielectric layer is approximately equal to the thickness of the second portion of the dielectric layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 31, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Jeong Byun, Sagy Levy
  • Patent number: 8975194
    Abstract: Disclosed a method for manufacturing an oxide layer, applicable to a manufacture procedure of a field oxide layer of a CMOS transistor in the field of semiconductor manufacturing, the method includes: injecting a first gas satisfying a first predetermined condition into a processing furnace in which a first CMOS transistor semi-finished product formed with an N-well and a P-well is placed, and dry-oxidizing the first CMOS transistor semi-finished product into a second CMOS transistor semi-finished product; and injecting a second gas satisfying a second predetermined condition different from the first predetermined condition into the processing furnace, and wet-oxidizing the second CMOS transistor semi-finished product into a third CMOS transistor semi-finished product.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: March 10, 2015
    Assignees: Peking University Founder Group Co., Ltd., Founder Microelectronics International Co., Ltd.
    Inventor: Jinyuan Chen
  • Patent number: 8940645
    Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.
    Type: Grant
    Filed: July 1, 2012
    Date of Patent: January 27, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Sagy Levy, Jeong Byun
  • Patent number: 8937022
    Abstract: A method of manufacturing a semiconductor device includes: housing a substrate into a processing chamber; and forming a metal nitride film on the substrate by supplying a source gas containing a metal element, a nitrogen-containing gas and a hydrogen-containing gas into the processing chamber; wherein in forming the metal nitride film, the source gas and the nitrogen-containing gas are intermittently supplied into the processing chamber, or the source gas and the nitrogen-containing gas are intermittently and alternately supplied into the processing chamber, or the source gas is intermittently supplied into the processing chamber in a state that supply of the nitrogen-containing gas into the processing chamber is continued, and the hydrogen-containing gas is supplied into the processing chamber during at least supply of the nitrogen-containing gas into the processing chamber.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: January 20, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Arito Ogawa
  • Patent number: 8912100
    Abstract: A manufacturing method of a complementary metal oxide semiconductor includes steps as following: providing a semiconductor substrate; forming a metal oxide semiconductor region having an oxide layer, which has a thickness greater than 1 micrometer, on a first surface of the semiconductor substrate; forming the oxide layer as an isolation region of the metal oxide semiconductor region and a heat-isolation region of a poly heater; forming a poly gate of the metal oxide semiconductor region as at least a portion of the poly heater; forming an interlayer dielectric layer; and processing a selenium etching. Under this circumstance, the oxide layer is applied so as to be the isolation region of the metal oxide semiconductor region and a heat-isolation region of the poly heater, the poly gate of the metal oxide semiconductor region is sufficiently utilized as the poly heater, and the heat-dissipation of the poly heater is optimized.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: December 16, 2014
    Assignee: Mosel Vitelic Inc.
    Inventors: Chyan-Huei Wang, Shiu-Fang Lo, Jack Jan
  • Patent number: 8877656
    Abstract: A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is heated in an atmosphere containing oxygen, so as to form a gate insulating film on and in contact with the silicon carbide substrate. The silicon carbide substrate having the gate insulating film is heated at 1250° C. or more in an atmosphere containing nitrogen and nitrogen monoxide. A value obtained by dividing partial pressure of the nitrogen monoxide by a total of partial pressure of the nitrogen and the partial pressure of the nitrogen monoxide in the second heating step is more than 3% and less than 10%. Accordingly, there can be provided a method for manufacturing a silicon carbide semiconductor device having high mobility.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: November 4, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hiromu Shiomi
  • Patent number: 8852966
    Abstract: A semiconductor wafer, on the surface of which a silicon dioxide base material and an amorphous silicon thin film are formed in this order, is carried into a chamber. An insulated gate bipolar transistor (IGBT) is connected with a power supply circuit to a flash lamp, and the IGBT makes an energization period to the flash lamp to be 0.01 millisecond or more and 1 millisecond or less, consequently making a flash light irradiation time to be 0.01 millisecond or more and 1 millisecond or less. Since a flash heat treatment is performed with a remarkably short flash light irradiation time, the excessive heating of the thin film of amorphous silicon is suppressed and harmful influence such as the exfoliation of the film is prevented.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: October 7, 2014
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Hiroki Kiyama, Kazuhiko Fuse, Shinichi Kato
  • Publication number: 20140291680
    Abstract: A silicon member and a method of producing the silicon member are provided. Cracking is suppressed in the silicon member even if the silicon member is used in a condition where it is heated. The silicon member 10 includes a coating layer 11 that coats a surface of the silicon member 10, wherein the coating layer 11 is composed of a product of silicon formed by reaction of the silicon on the surface, and a thickness of the coating layer is 15 nm or more and 600 nm or less. It is preferable that the coating layer is a silicon oxide film or a silicon nitride film.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 2, 2014
    Applicant: MITSUBISHI MATERIALS CORPORATION
    Inventor: Yoshinobu Nakada
  • Patent number: 8815694
    Abstract: Embodiments include semiconductor-on-insulator (SOI) substrates having SOI layers strained by oxidation of the base substrate layer and methods of forming the same. The method may include forming a strained channel region in a semiconductor-on-insulator (SOI) substrate including a buried insulator (BOX) layer above a base substrate layer and a SOI layer above the BOX layer by first etching the SOI layer and the BOX layer to form a first isolation recess region and a second isolation recess region. A portion of the SOI layer between the first isolation recess region and the second isolation recess region defines a channel region in the SOI layer. A portion of the base substrate layer below the first isolation recess region and below the second isolation recess region may then be oxidized to form a first oxide region and a second oxide region, respectively, that apply compressive strain to the channel region.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz, Pranita Kerber
  • Patent number: 8809203
    Abstract: It is an object to provide a method for manufacturing a semiconductor device that has a semiconductor element including a film in which mixing impurities is suppressed. It is another object to provide a method for manufacturing a semiconductor device with high yield. In a method for manufacturing a semiconductor device in which an insulating film is formed in contact with a semiconductor layer provided over a substrate having an insulating surface with use of a plasma CVD apparatus, after an inner wall of a reaction chamber of the plasma CVD apparatus is coated with a film that does not include an impurity to the insulating film, a substrate is introduced in the reaction chamber, and the insulating film is deposited over the substrate. As a result, an insulating film in which the amount of impurities is reduced can be formed.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Tetsuhiro Tanaka, Takashi Ohtsuki, Seiji Yasumoto, Kenichi Okazaki, Shunpei Yamazaki, Naoya Sakamoto
  • Patent number: 8778814
    Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: July 15, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tamotsu Owada, Shun-ichi Furuyama, Hirofumi Watantani, Kengo Inoue, Atsuo Shimizu
  • Patent number: 8735302
    Abstract: Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: May 27, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Amol Joshi, John Foster, Zhendong Hong, Olov Karlsson, Bei Li, Usha Raghuram
  • Patent number: 8716149
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure. An atomic layer deposition (ALD) process is performed to deposit a spacer around the gate structure. The ALD process includes alternating flowing ionized radicals of a first precursor across the semiconductor substrate and flowing a chlorosilane precursor across the semiconductor substrate to deposit the spacer.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: May 6, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Fabian Koehler, Sergej Mutas, Dina Triyoso, Itasham Hussain
  • Patent number: 8679922
    Abstract: The method includes a step of forming a mask having an opening, for forming an opening in multiple insulating films, above a semiconductor substrate on which a member becoming a first insulating film, a member becoming a second insulating film being different from the member becoming the first insulating film, a member becoming a third insulating film, and a member becoming a fourth insulating film being different from the member becoming the third insulating film are stacked in this order; a first step of continuously removing the member becoming the fourth insulating film and the member becoming the third insulating film at a portion corresponding to the opening of the mask; and a second step of removing the member becoming the second insulating film, after the first step, at a portion corresponding to the opening of the mask.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: March 25, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takaharu Kondo, Takashi Usui
  • Patent number: 8679961
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device which includes a MISFET, includes: forming a gate insulating film on a semiconductor substrate; forming a gate electrode on the gate insulating film; implanting nitrogen equal to or more than 5.0e14 atoms/cm2 and equal to or less than 1.5e15 atoms/cm2 in the semiconductor substrate by tilted ion implantation in a direction from an outside to an inside with respect to side surfaces of the gate electrode; depositing a metal film including nickel on areas in which nitrogen atoms are implanted, the areas are in a semiconductor substrate on both sides of the gate electrode; and performing first heat processing of reacting the metal film and the semiconductor substrate and forming metal semiconductor compound layers, the shapes of the layers are controlled by the nitrogen profiles of the areas.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keiji Ikeda
  • Patent number: 8673711
    Abstract: A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: WeonHong Kim, Dae-Kwon Joo, Hajin Lim, Jinho Do, Kyungil Hong, Moonkyun Song
  • Patent number: 8664109
    Abstract: A method of forming a carbon-rich silicon carbide-like dielectric film having a carbon concentration of greater than, or equal to, about 30 atomic % C and a dielectric constant of less than, or equal to, about 4.5 is provided. The dielectric film may optionally include nitrogen. When nitrogen is present, the carbon-rich silicon carbide-like dielectric film has a concentration nitrogen that is less than, or equal, to about 5 atomic % nitrogen.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: March 4, 2014
    Assignees: International Business Machines Corporation, Global Foundries, Inc.
    Inventors: Alfred Grill, Joshua L. Herman, Son Nguyen, E. Todd Ryan, Hosadurga K. Shobha
  • Patent number: 8664126
    Abstract: A method of selective deposition on silicon substrates having regions of bare silicon and regions of oxide formed thereon. The method includes placing the substrate on a wafer support inside a processing chamber, introducing a carbon-containing gas into the reactor, applying a bias to the substrate, generating a plasma from the hydrocarbon gas, implanting carbon ions into the regions of oxide on the substrate by a plasma doping process, and depositing a carbon-containing film on the bare silicon regions.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: March 4, 2014
    Assignee: Applied Materials, Inc.
    Inventor: Daping Yao
  • Patent number: 8580698
    Abstract: A method for fabricating the gate dielectric layer comprises forming a high-k dielectric layer over a substrate; forming an oxygen-containing layer on the high-k dielectric layer by an atomic layer deposition process; and performing an inert plasma treatment on the oxygen-containing layer.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: November 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yang Lee, Xiong-Fei Yu, Jian-Hao Chen, Cheng-Hao Hou, Da-Yuan Lee, Kuang-Yuan Hsu
  • Patent number: 8574985
    Abstract: Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: November 5, 2013
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Xiangxin Rui, Sunil Shanker, Sandra Malhotra, Imran Hashim, Edward Haywood
  • Patent number: 8575033
    Abstract: Provided are processes for the low temperature deposition of silicon-containing films using carbosilane precursors containing a carbon atom bridging at least two silicon atoms. Certain methods comprise providing a substrate; in a PECVD process, exposing the substrate surface to a carbosilane precursor containing at least one carbon atom bridging at least two silicon atoms; exposing the carbosilane precursor to a low-powered energy sourcedirect plasma to provide a carbosilane at the substrate surface; and densifying the carbosilanestripping away at least some of the hydrogen atoms to provide a film comprising SiC. The SiC film may be exposed to the carbosilane surface to a nitrogen source to provide a film comprising SiCN.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: November 5, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Timothy W. Weldman, Todd Schroeder
  • Patent number: 8563442
    Abstract: In order to provide a method for manufacturing a single crystal SiC substrate that can obtain an SiC layer with good crystallinity, an Si substrate 1 having a surface Si layer 3 of a predetermined thickness and an embedded insulating layer 4 is prepared, and when the Si substrate 1 is heated in a carbon-series gas atmosphere to convert the surface Si layer 3 into a single crystal SiC layer 6, the Si layer in the vicinity of an interface 8 with the embedded insulating layer 4 is left as a residual Si layer 5.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: October 22, 2013
    Assignee: Air Water Inc.
    Inventors: Keisuke Kawamura, Katsutoshi Izumi, Hidetoshi Asamura, Takashi Yokoyama
  • Patent number: 8557717
    Abstract: It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: October 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Koichi Muraoka, Koichi Kato, Yasushi Nakasaki, Yuichiro Mitani
  • Patent number: 8551891
    Abstract: Methods of treating the interior of a plasma region are described. The methods include a preventative maintenance procedure or the start-up of a new substrate processing chamber having a remote plasma system. A new interior surface is exposed within the remote plasma system. The (new) interior surfaces are then treated by sequential steps of (1) forming a remote plasma from hydrogen-containing precursor within the remote plasma system and then (2) exposing the interior surfaces to water vapor. Steps (1)-(2) are repeated at least ten times to complete the burn-in process. Following the treatment of the interior surfaces, a substrate may be transferred into a substrate processing chamber. A dielectric film may then be formed on the substrate by flowing one precursor through the remote plasma source and combining the plasma effluents with a second precursor flowing directly to the substrate processing region.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: October 8, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Jingmei Liang, Lili Ji, Nitin K. Ingle
  • Patent number: 8546270
    Abstract: An atomic layer deposition apparatus and an atomic layer deposition method increase productivity. The atomic layer deposition apparatus includes a reaction chamber, a heater for supporting a plurality of semiconductor substrates with a given interval within the reaction chamber and to heat the plurality of semiconductor substrates and a plurality of injectors respectively positioned within the reaction chamber and corresponding to the plurality of semiconductor substrates supported by the heater. The plurality of injectors are individually swept above the plurality of semiconductor substrates to spray reaction gas.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: October 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Hyun Kim, Ki-Vin Im, Hoon-Sang Choi, Moon-Hyeong Han
  • Patent number: 8546271
    Abstract: A method for selective oxidation of silicon containing materials in a semiconductor device is disclosed and claimed. In one aspect, a rapid thermal processing apparatus is used to selectively oxidize a substrate by in-situ steam generation at high pressure in a hydrogen rich atmosphere. Other materials, such as metals and barrier layers, in the substrate are not oxidized.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: October 1, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Yoshitaka Yokota, Norman Tam, Balasubramanian Ramachandran, Martin John Ripley
  • Patent number: 8546920
    Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar V. Singh, Jeffrey W. Sleight
  • Publication number: 20130252437
    Abstract: A method of manufacturing a semiconductor device includes forming a thin film on a substrate by performing a cycle a predetermined number of times. The cycle includes supplying a source gas to the substrate, and supplying excited species from each of a plurality of excitation units provided at a side of the substrate to the substrate. Each of the plurality of excitation units generates the excited species by plasma-exciting a reaction gas. In supplying the excited species from each of the plurality of excitation units, an in-plane distribution of the excited species supplied from at least one of the plurality of excitation units in the substrate differs from an in-plane distribution of the excited species supplied from another excitation unit, other than the at least one excitation unit, among the plurality of excitation units, in the substrate.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 26, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Atsushi SANO, Yoshiro HIROSE, Kiyohiko MAEDA, Kazuyuko OKUDA, Ryuji YAMAMOTO
  • Patent number: 8524395
    Abstract: The present invention relates to nonaqueous electrolyte secondary batteries and durable anode materials and anodes for use in nonaqueous electrolyte secondary batteries. The present invention also relates to methods for producing these anode materials. In the present invention, a metal-semiconductor alloy layer is formed on an anode material by contacting a portion of the anode material with a displacement solution. The displacement solution contains ions of the metal to be deposited and a dissolution component for dissolving a part of the semiconductor in the anode material. When the anode material is contacted with the displacement solution, the dissolution component dissolves a part of the semiconductor in the anode material thereby providing electrons to reduce the metal ions and deposit the metal on the anode material. After deposition, the anode material and metal are annealed to form a uniform metal-semiconductor alloy layer.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: September 3, 2013
    Assignee: Enovix Corporation
    Inventors: Murali Ramasubramanian, Robert Spotnitz
  • Patent number: RE45106
    Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method to manufacture a semiconductor structure includes forming a cavity in a substrate. A portion of the substrate is doped, or a doped material is deposited over a portion of the substrate. At least a portion of the doped substrate or at least a portion of the doped material is converted to a dielectric material to enclose the cavity. The forming of the cavity may occur before or after the doping of the substrate or the depositing of the doped material. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: September 2, 2014
    Assignee: Estivation Properties LLC
    Inventor: Bishnu Prasanna Gogoi