In Atmosphere Containing Halogen Patents (Class 438/774)
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Patent number: 6368949Abstract: Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices have been reduced or a minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include forming a sacrificial oxide and removing the sacrificial oxide to remove the carbonaceous residues and anneal out damage to the silicon substrate. Subsequently formed silicide regions on the source and drain regions have improved quality.Type: GrantFiled: September 21, 2000Date of Patent: April 9, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Susan H. Chen, Simon S. Chan
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Patent number: 6362114Abstract: A semiconductor processing method of forming an oxynitride film on a silicon substrate comprises placing a substrate in a reactor, the substrate having an exposed silicon surface, and combining nitrogen, oxygen, and fluorine in gaseous form in the reactor under temperature and pressure conditions effective to grow an oxynitride film on the exposed silicon surface. According to a preferred aspect, the nitrogen and the oxygen are provided in the reactor from decomposition of a compound containing atomic nitrogen and oxygen. A semiconductor processing method of forming a dielectric composite film on a silicon substrate is also described.Type: GrantFiled: February 28, 2000Date of Patent: March 26, 2002Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Pierre C. Fazan
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Patent number: 6355581Abstract: A method for fabricating a silicon oxide and silicon glass layers at low temperature using High Density Plasma CVD with silane or inorganic or organic silane derivatives as a source of silicon, inorganic compounds containing boron, phosphorus, and fluorine as a doping compounds, oxygen, and gas additives is described. RF plasma with certain plasma density is maintained throughout the entire deposition step in reactor chamber. Key feature of the invention's process is a silicon source to gas additive mole ratio, which is maintained depending on the used compound and deposition process conditions. Inorganic halide-containing compounds are used as gas additives. This feature provides the reaction conditions for the proper reaction performance that allows a deposition of a film with. good film integrity and void-free gap-fill within the steps of device structures.Type: GrantFiled: February 23, 2000Date of Patent: March 12, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Vladislav Vassiliev, John Leonard Sudijono, Yelehanka Ramachandramurthy Pradeep, Jie Yu
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Patent number: 6346487Abstract: An apparatus and method of forming an oxynitride insulating layer on a substrate performed by putting the substrate at a first temperature within the main chamber of a furnace, exposing the substrate to a nitrogen containing gas at a second temperature which is higher than the first temperature, and growing the oxynitride layer on the substrate within the main chamber in the presence of post-combusted gases. The higher temperature nitrogen containing gases are combusted in a chamber outside the main chamber. The higher temperature is in the range of 800 to 1200° C., and preferably 950° C. In a second embodiment, distributed N2O gas injectors within the main chamber deliver the nitrogen containing gas. The nitrogen containing gas is pre-heated outside the chamber. The nitrogen containing gas is then delivered to a gas manifold that splits the gas flow and directs the gas to a number of gas injectors, preferably two to four injectors within the main process tube.Type: GrantFiled: March 10, 2001Date of Patent: February 12, 2002Assignee: International Business Machines CorporationInventors: Douglas A. Buchanan, Evgeni P. Gousev, Carol J. Heenan, Wade J. Hodge, Steven M. Shank, Patrick R. Varekamp
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Publication number: 20020016083Abstract: It is an object of the invention to solve a problem that a gate breakdown voltage and RF characteristics of a field effect transistor, which is provided with a double recess composed of a wide recess and a narrow recess, is not satisfactory. This problem results from the fact that aAlGaAs layer is exposed on a surface of the wide recess. The method for fabricating the field effect transistor comprise the steps of successively forming the first active layer, the first stopper layer, the second active layer, the second stopper layer and the third active layer on a substrate, forming a wide recess by etching a predetermined part of the third active layer till the second stopper is exposed, exposing the second active layer by removing the second stopper layer exposed on the bottom surface of the wide recess, and forming a narrow recess, which has a smaller aperture area than that of the wide recess, by etching a predetermined part of the exposed second active layer till the first stopper layer is exposed.Type: ApplicationFiled: September 1, 1999Publication date: February 7, 2002Inventor: JUNKO MORIKAWA
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Patent number: 6331495Abstract: A semiconductor processing method is provided for making contact openings. It includes depositing several insulative layers and performing an anisotropic etch. One layer is a conformal oxide covering the contact area and adjacent structures. A second layer is a breadloafed oxide deposited over the contact area and adjacent structures. A third layer is a doped oxide deposited over the two lower layers. The anisotropic etch is performed through the oxide layers to the contact area located on a lower substrate. The etch is selectively more rapid in the third oxide than in the two other oxides. The breadloafed oxide provides additional protection and reduces the risk of etch-through to conductive structures adjacent the contact area. An alternate embodiment replaces the two lowest oxide layers by a breadloafed nitride layer. In this embodiment, the anisotropic etch is selectively more rapid in oxides than in nitrides.Type: GrantFiled: December 9, 1999Date of Patent: December 18, 2001Assignee: Micron Technology, Inc.Inventor: David S. Becker
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Patent number: 6316371Abstract: Method for the chemical treatment of a semiconductor substrate at a raised temperature, such as oxidization. To achieve a uniform treatment of comparatively large wafers in the radial direction, as well as to realize a uniform treatment during the simultaneous treatment of a number of semiconductor substrates placed one after each other, it is proposed, starting with an inert atmosphere, to gradually add oxygen and at the end of the treatment to gradually reduce the oxygen portion.Type: GrantFiled: March 30, 1999Date of Patent: November 13, 2001Assignee: ASM International N.V.Inventors: Theodorus Gerardus Maria Oosterlaken, Frank Huussen, Remco Van Der Berg
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Publication number: 20010031562Abstract: A method is disclosed for forming an ultrathin oxide layer of uniform thickness. The method is particularly advantageous for producing uniformly thin interfacial oxides beneath materials of high dielectric permittivity, or uniformly thin passivation oxides. Hydrofluoric (HF) etching of a silicon surface, for example, is followed by termination of the silicon surface with ligands larger than H or F, particularly hydroxyl, alkoxy or carboxylic tails. The substrate is oxidized with the surface termination in place. The surface termination and relatively low temperatures moderate the rate of oxidation, such that a controllable thickness of oxide is formed. In some embodiments, the ligand termination is replaced with OH prior to further deposition. The deposition preferably includes alternating, self-limiting chemistries in an atomic layer deposition process, though any other suitable deposition process can be used.Type: ApplicationFiled: February 22, 2001Publication date: October 18, 2001Inventors: Ivo Raaijmakers, Yong-Bae Kim, Marko Tuominen, Suvi P. Haukka
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Patent number: 6303522Abstract: The present invention is related to an efficient thermal oxidation process that allows the controlled growth of in-situ cleaned high quality thin oxides on a silicon-containing substrate. Said oxidation is performed in an ambient comprising at least the reaction products of a chloro-carbon precursor and ozone. This thermal oxidation is preferably executed at low temperatures, being preferably below 500° C., in order to limit the in-diffusion of metal surface contaminants is limited. The present invention is further related to the decomposition of organic chloro-carbon precursors at low temperatures by the introduction of ozone prior to the actual oxidation step.Type: GrantFiled: November 18, 1998Date of Patent: October 16, 2001Assignee: IMEC VZWInventors: Paul Mertens, Marc Heyns
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Patent number: 6291365Abstract: In a method for manufacturing a semiconductor device where a silicon substrate is loaded in an oxidation furnace whose temperature is a first value, the temperature of the oxidation furnace is raised to a second value, and an oxidation operation is performed upon the silicon substrate to grow an essential silicon oxide layer on the silicon, a thickness ratio of an initial silicon oxide layer grown before the oxidation operation performing step to a less than 40 Å thick gate silicon oxide layer formed by the initial silicon oxide layer and the essential silicon oxide layer is about 20 to 40 percent.Type: GrantFiled: February 10, 2000Date of Patent: September 18, 2001Assignee: NEC CorporationInventor: Fumihiro Koba
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Publication number: 20010018274Abstract: A semiconductor device is fabricated by a method comprising the steps of: selectively introducing a halogen element or argon into a device region 14 of a silicon substrate 10; and wet oxidizing the silicon substrate 10 in an ambient atmosphere which an H2O partial pressure is less than 1 atm to thereby form a silicon oxide film 22 in the device region 14 of the silicon substrate 10, and a silicon oxide film 24 thinner than the silicon oxide film 22 in a device region 16 of the silicon substrate 10. Whereby the silicon oxide film in a device region 14 with the halogen element or argon introduced can be selectively formed thick. The silicon oxide films are formed by the wet oxidation, whereby the gate insulation films can be more reliable than those formed by the dry oxidation.Type: ApplicationFiled: February 9, 2001Publication date: August 30, 2001Applicant: Fujitsu Limited and Kabushiki Kaisha ToshibaInventors: Taro Sugizaki, Toshiro Nakanishi, Kyoichi Suguro, Atsushi Murakoshi
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Patent number: 6277765Abstract: A low dielectric constant material, suitable for use as an interlayer dielectric in microelectronic structures includes a porous silicon oxide layer. In a further aspect of the present invention, a porous oxide of silicon is formed by the room temperature oxidation of porous silicon. The room temperature oxidation is achieved by exposing a porous silicon layer to a solution of hydrochloric acid, hydrogen peroxide, and water, in the presence of a metal catalyst.Type: GrantFiled: August 17, 1999Date of Patent: August 21, 2001Assignee: Intel CorporationInventors: Peng Cheng, Brian S. Doyle, Chien Chiang, Mark Thiec-Hien Tran
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Publication number: 20010012695Abstract: A method for manufacturing a bit line is disclosed. Such a method includes: forming a layer-insulation layer on the surface of a semiconductor substrate; forming a contact hole on a predetermined region of the layer-insulation layer; forming a first conductive layer on the upper surface of the layer-insulation layer and inside the contact hole, the first conductive layer being made of a metal; forming a second conductive layer on the upper surface of the first conductive layer, the second conductive layer being made of a metal; and patterning the first and the second conductive layers together. The bit line made of a metal is manufactured to be integrated with a plug. The first conductive layer is formed by sputtering while the second conductive layer is formed by chemical vapor deposition, thereby shortening the process and improving the characteristics of the bit line.Type: ApplicationFiled: February 7, 2001Publication date: August 9, 2001Inventors: Won-Hwa Jin, Keun-Su Kim
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Patent number: 6271152Abstract: Field oxide is formed using high pressure. Oxidation of field regions between active regions is accomplished in a two-step process. A first oxide layer is formed in the field region. Then, a second oxide layer is formed on the first oxide layer. The second oxide layer is formed at a pressure of at least approximately 5 atmospheres. In one embodiment, the first oxide layer is formed at atmospheric pressure using a conventional oxidation technique, such as rapid thermal oxidation (RTO), wet oxidation, or dry oxidation. In another embodiment, the first oxide layer is formed, at a pressure of approximately 1 to 5 atmospheres. Wet or dry oxidation is used for the oxidizing ambient. The first oxide layer is formed to a thickness of approximately 500 angstroms or less, and typically greater than 200 angstroms. Temperatures of approximately 600 to 1,100 degrees Celsius are used for the oxidation steps.Type: GrantFiled: May 16, 2000Date of Patent: August 7, 2001Assignee: Micron Technology, Inc.Inventors: Randhir P. S. Thakur, David L. Chapek
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Patent number: 6228751Abstract: A method of manufacturing a semiconductor device that forms laminate layers includes the steps of reducing contamination containing the single bond of carbon on at least one part of a surface on which the laminate films are formed by activated hydrogen before the laminate films are formed, and forming the laminate films on the surface on which the laminate films are formed.Type: GrantFiled: September 6, 1996Date of Patent: May 8, 2001Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Mitsunori Sakama, Takeshi Fukada
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Patent number: 6221790Abstract: A stable silicon oxide film for use as a thickness reference is prepared by oxidizing a silicon wafer, having a smooth surface, under carefully controlled conditions thereby growing a film of known thickness and refractive index. This is followed by the deposition of a layer of silicon nitride over said oxide film. The resulting structure may then be used as a reference standard when ellipsometry is routinely employed for measuring the thickness of, for example, gate oxides in field effect devices. It has been found that the thickness of the reference layer remains stable over extended time periods without the need for frequent cleaning.Type: GrantFiled: November 19, 1998Date of Patent: April 24, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventor: Chin-Te Huang
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Patent number: 6218317Abstract: Disclosed are multilevel interconnects for integrated circuit devices, especially copper/dual damascene devices, and methods of fabrication. Methylated-oxide type hardmasks are formed over polymeric interlayer dielectric materials. Preferably the hardmasks are materials having a dielectric constant of less than 3 and more preferably 2.7 or less. Advantageously, both the hardmask and the interlayer dielectric can be spincoated.Type: GrantFiled: April 19, 1999Date of Patent: April 17, 2001Assignee: National Semiconductor Corp.Inventors: Sudhakar Allada, Chris Foster
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Patent number: 6204199Abstract: A method and apparatus for producing a semiconductor device can provide a uniform film on a substrate. A substrate is introduced into a reaction chamber or tube (51) which has gas feed ports (52, 53) and gas exhaust ports (54, 55). The substrate in the reaction tube (51) is heated to substantially a film forming temperature while supplying a prescribed gas to the reaction tube (51) through the gas feed ports (52, 53) and exhausting the prescribed gas from the reaction tube (51) through all the exhaust ports (54, 55). A film-forming gas is supplied to the reaction tube (51) to form a film on the substrate. The substrate with the film formed thereon is taken out of the reaction tube (51). Moreover, after the film formation on the substrate, a prescribed gas is supplied to the reaction tube (51) from the gas feed ports (52, 53) while being exhausted from the reaction tube (51) through all the exhaust ports (54, 55), thereby removing a residual gas in the reaction tube.Type: GrantFiled: September 10, 1999Date of Patent: March 20, 2001Assignee: Kokusai Electric Co., Ltd.Inventors: Masanori Sakai, Masayuki Tsuneda, Naoko Matsuyama, Hideharu Itatani, Michihide Nakamure
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Patent number: 6177364Abstract: An interlayer dielectric for a damascene structure includes a first etch stop layer formed on a substrate. A first interlayer dielectric layer containing fluorine is formed on the first etch stop layer by deposition. A second etch stop layer is formed on the first interlayer dielectric layer. A second interlayer dielectric layer containing fluorine is formed on the second etch stop layer by deposition. The first and second interlayer dielectric layers and the first and second etch stop layers are etched to form at least one trench and at least one via. The at least one trench and the at least one via are treated with an H2/N2 plasma in-situ, wherein a fluorine-depleted region in the first and second interlayer dielectric layers is formed, and wherein a nitrided region is formed adjacent the fluorine-depleted region, with the nitrided region corresponding to a side surface of the at least one trench and the at least one via.Type: GrantFiled: December 2, 1998Date of Patent: January 23, 2001Assignee: Advanced Micro Devices, Inc.Inventor: Richard J. Huang
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Patent number: 6169035Abstract: A LOCOS method uses a reagent mixed of etchant and oxidizer to simultaneously perform the step of forming the FOX layer and the step of removing a mask layer of the conventional LOCOS method. The applied temperature is about 950-1150° C. The etchant. such as a HF acid solution, is used to remove the mask layer, and the oxidizer, such as O2, is used to form the FOX layer on a silicon substrate.Type: GrantFiled: October 14, 1998Date of Patent: January 2, 2001Assignee: United Microelectronic Corp.Inventors: Chuan H. Liu, Chin-Kun Lo, Mainn-Gwo Chen
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Patent number: 6162702Abstract: A silicon wafer 2 has an ultra thin central portion 2 that is supported by a circumferential rim 3 of thicker silicon. The central region is thinned by conventional means using conventional removal apparatus. As an alternative method, the central portion is removed using a photoresist mask or a combination of a photoresist mask and a hard mask.Type: GrantFiled: June 17, 1999Date of Patent: December 19, 2000Assignee: Intersil CorporationInventors: William R. Morcom, Stephen C. Ahrens, Jeffrey P. Spindler, Raymond T. Ford, Jeffrey E. Lauffer
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Patent number: 6140251Abstract: A method of processing a semiconductor substrate, comprising the steps of: heating a substance within a first chamber, at a selected temperature which is above the minimum decomposition temperature of the substance, to cause decomposition of the substance into a predetermined gas; cooling the gas to below the minimum decomposition temperature of the substance; transporting the gas from the first chamber to a second chamber; and exposing a semiconductor substrate, located in the second chamber, to the cooled gas.Type: GrantFiled: December 10, 1997Date of Patent: October 31, 2000Assignee: Intel CorporationInventors: Reza Arghavani, Robert S. Chau, Weimin Han
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Patent number: 6130164Abstract: A semiconductor device having a gate oxide layer formed by selective removal of the gate oxide layer and a process for manufacturing such a device is disclosed. A gate oxide layer is formed on a substrate. The gate oxide layer is selectively removed in a controlled ambient to reduce the thickness of the gate oxide layer. A gate electrode is disposed on the gate oxide layer. In accordance with one particular aspect of the process, the controlled ambient includes an NF.sub.3 bearing gas, which is flowed over the gate oxide layer to remove portions of the oxide layer.Type: GrantFiled: March 26, 1997Date of Patent: October 10, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, Mark C. Gilmer
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Patent number: 6114258Abstract: A system and method of forming an oxide in the presence of a nitrogen-containing material. A substrate having a nitrogen-containing material on a surface is placed in a reaction chamber. An oxygen-containing gas, or an oxygen-containing gas and a hydrogen-containing gas are provided to the chamber and reacted in the chamber. The reactive gases are used to oxidize the surface of the substrate and displace the nitrogen-containing material from the interface.Type: GrantFiled: October 19, 1998Date of Patent: September 5, 2000Assignee: Applied Materials, Inc.Inventors: Gary E. Miner, Guangcai Xing, David R. Lopes, Sathees Kuppurao
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Patent number: 6114257Abstract: A process for thermal oxidation of a semiconductor substrate comprising exposing the substrate to a chlorine plasma, and then heating the substrate in an oxidizing ambient. The substrate may comprise silicon, germanium, or a combination thereof. The heating step may further comprise heating at a temperature of between about 750.degree. C. and about 850.degree. C.Type: GrantFiled: September 16, 1998Date of Patent: September 5, 2000Assignee: International Business Machines CorporationInventor: Paul A. Ronsheim
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Patent number: 6103601Abstract: A fluorine-doped silicate glass (FSG) layer having a low dielectric constant and a method of forming such an insulating layer is described. The FSG layer is treated with a post-treatment step to make the layer resistant to moisture absorption and outgassing of fluorine atoms. In one embodiment, the post-treatment step includes forming a thin, undoped silicate glass layer on top of the FSG layer, and in another embodiment, the stability of the FSG film is increased by a post-treatment plasma step.Type: GrantFiled: June 10, 1999Date of Patent: August 15, 2000Assignee: Applied Materials, Inc.Inventors: Peter W. Lee, Stuardo Robles, Anand Gupta, Virendra V. S. Rana, Amrita Verma
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Patent number: 6066572Abstract: A method of removing carbon contamination. On a semiconductor substrate having carbon contamination thereon, a sacrificial oxide layer is formed. During the formation of the sacrificial oxide layer, an agent is introduced to help and improve the growth of the sacrificial oxide layer, and to trap the carbon contamination. The sacrificial oxide layer is then removed, and the carbon contamination is removed with the sacrificial oxide layer.Type: GrantFiled: February 1, 1999Date of Patent: May 23, 2000Assignee: United Semiconductor Corp.Inventors: Le-Yen Lu, Yau-Kae Sheu
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Patent number: 6037258Abstract: A method for fabricating a copper interconnect structure, in a damascene type opening, comprised a thick copper layer, obtained via an electro-chemical deposition procedure, and comprised of an underlying, copper seed layer, featuring a smooth top surface topography, has been developed. The smooth top surface topography, of the underlying copper seed layer, is needed to allow the voidless deposition of the overlying, thick copper layer, and is also needed to allow the deposition of the overlying thick copper layer to be realized, with a surface that can survive a chemical mechanical polishing procedure, without the risk of unwanted dishing or spooning phenomena. The desirable, copper seed layer, is obtained via a process sequence that features: a plasma vapor deposition of a first copper seed layer; an argon purge procedure; and a second plasma vapor deposition of a second copper seed layer.Type: GrantFiled: May 7, 1999Date of Patent: March 14, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chung-Shi Liu, Chen-Hua Yu
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Patent number: 5858844Abstract: The present invention comprises an innovative gate oxidation process after the disposition of the gate and prior to the disposition of the source and the drain by exposing the gate to oxygen at a predetermined temperature and for a predetermined time period for the optimized transistor performance. During the innovative gate oxidation process, oxygen penetrates into the interfaces of the gate conductive layer gate oxide and the gate dielectric layer silicon substrate and oxidizes portions of the gate conductive layer at the interfaces due to the oxygen smiling or the bird beak effect, which results in an increased effective thickness of the gate dielectric layer. Optionally, HCl can be introduced at a predetermined flowrate during the innovative gate oxidation process.Type: GrantFiled: June 7, 1995Date of Patent: January 12, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Hao Fang, Farrokh Omid-Zehoor, Todd Lukanc, Chris Schmidt
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Patent number: 5846888Abstract: A desirable impurity, such as reactive gases and inert gases, is safely introduced into a substrate/oxide interface during high pressure thermal oxidation. Desirable impurities include chlorine, fluorine, bromine, iodine, astatine, nitrogen, nitrogen trifluoride, and ammonia. In one embodiment, the desirable impurity is introduced into a processing chamber prior to the high pressure oxidation step. Then, the temperature is brought to or maintained at an oxidation temperature. In another embodiment, the desirable impurity is introduced into the processing chamber after the high pressure oxidation step, while the temperature is still sufficiently high for oxidation. In yet another embodiment, the desirable impurity is introduced into the processing chamber both before and after the high pressure oxidation step.Type: GrantFiled: September 27, 1996Date of Patent: December 8, 1998Assignee: Micron Technology, Inc.Inventors: David L. Chapek, Randhir P. S. Thakur
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Patent number: 5721176Abstract: A process of forming chlorine-doped silicon dioxide films on a silicon substrate comprising oxidizing said silicon substrate in the presence of a chlorine source, thereby forming said chlorine-doped silicon dioxide film on said silicon substrate, said chlorine source being oxalyl chloride.Type: GrantFiled: May 29, 1992Date of Patent: February 24, 1998Assignee: Olin CorporationInventors: Michael J. McGeary, Herman J. Boeglin
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Patent number: 5637528Abstract: A method of manufacturing a semiconductor device including the steps of: (a) forming a mask layer of a desired pattern on a silicon substrate surface or on an SiO.sub.2 strain absorbing layer formed on the silicon substrate surface; (b) selectively oxidizing the silicon substrate in a dry oxygen atmosphere by using the mask layer as an oxidation mask; and (c) selectively oxidizing the silicon substrate in an atmosphere of dry oxygen mixed with gas containing halogen element, wherein a field oxide film having a thickness of 100 nm or more is formed. The first and second oxidizing steps (b) and (c) are preferably performed at temperatures between 950.degree. C. and 1200.degree. C. A field oxide film with a short bird's beak can be formed while maintaining a relatively high oxidation speed and preventing generation of a white ribbon.Type: GrantFiled: August 22, 1996Date of Patent: June 10, 1997Assignee: Fujitsu LimitedInventors: Masaaki Higashitani, Kenichi Hikazutani