Using Electromagnetic Or Wave Energy Patents (Class 438/776)
-
Patent number: 7345001Abstract: The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielectric includes forming a gate dielectric layer (410) on a substrate (310), and subjecting the gate dielectric layer (410) to a nitrogen containing plasma process (510), wherein the nitrogen containing plasma process (510) has a ratio of helium to nitrogen of 3:1 or greater.Type: GrantFiled: June 24, 2004Date of Patent: March 18, 2008Assignee: Texas Instruments IncorporatedInventors: Hiroaki Niimi, Husam N. Alshareef, Rajesh Khamankar, Toan Tran
-
Publication number: 20080032510Abstract: A method of forming a layer comprising silicon and nitrogen on a substrate is provided. The layer may also include oxygen and be used as a silicon oxynitride gate dielectric layer. In one aspect, forming the layer includes exposing a silicon substrate to a plasma of nitrogen and a noble gas to incorporate nitrogen into an upper surface of the substrate, wherein the noble gas is argon, neon, krypton, or xenon. The layer is annealed and then exposed to a plasma of nitrogen to incorporate more nitrogen into the layer. The layer is then further annealed.Type: ApplicationFiled: June 17, 2007Publication date: February 7, 2008Inventor: Christopher Olsen
-
Patent number: 7279429Abstract: In one embodiment, the present invention relates to a method for increasing the ignition reliability of a plasma in a plasma reactor, the method comprising: supplying a source gas to the plasma reactor, the source gas comprising: (a) at least one reactive compound; and (b) at least one ignition gas, wherein the at least one ignition gas increases the ignitability of the source gas as compared to the ignitability of the source gas lacking the at least one ignition gas.Type: GrantFiled: October 1, 2004Date of Patent: October 9, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Calvin T. Gabriel, Tzu-Yen Hsieh
-
Patent number: 7250375Abstract: A method of processing a for an electronic device, comprising, at least: a nitridation step (a) of supplying nitrogen radicals on the surface of the electronic device substrate, to thereby form a nitride film on the surface thereof; and a hydrogenation step (b) of supplying hydrogen radicals to the surface of the electronic device substrate. By use of this method, it is possible to recover the degradation in the electric property of an insulating film due to a turnaround phenomenon which can occur at the time of nitriding an Si substrate, etc.Type: GrantFiled: August 2, 2002Date of Patent: July 31, 2007Assignee: Tokyo Electron LimitedInventors: Toshio Nakanishi, Takuya Sugawara, Seiji Matsuyama, Masaru Sasaki
-
Patent number: 7247582Abstract: A method of depositing tensile or compressively stressed silicon nitride on a substrate is described. Silicon nitride having a tensile stress with an absolute value of at least about 1200 MPa can be deposited from process gas comprising silicon-containing gas and nitrogen-containing gas, maintained in an electric field having a strength of from about 25 V/mil to about 300 V/mil. The electric field is formed by applying a voltage at a power level of less than about 60 Watts across electrodes that are spaced apart by a separation distance that is at least about 600 mils. Alternatively, silicon nitride having a compressive stress with an absolute value of at least about 2000 MPa can be formed in an electric field having a strength of from about 400 V/mil to about 800 V/mil.Type: GrantFiled: May 23, 2005Date of Patent: July 24, 2007Assignee: Applied Materials, Inc.Inventors: Lewis Stern, John Albright
-
Patent number: 7226874Abstract: A substrate processing method forming an oxynitride film by nitriding an oxide film formed on a silicon substrate includes a nitridation processing step that nitrides a surface of the oxide film by radicals or ions formed by exciting a nitrogen gas by microwave-excited plasma, the nitridation processing is conducted at a substrate temperature of 500° C. or less by setting an electron temperature of the microwave-excited plasma to 2 eV or less, and by setting the resident time of oxygen in the processing space in which the substrate to be processed is held, to two seconds or less.Type: GrantFiled: November 12, 2004Date of Patent: June 5, 2007Assignee: Tokyo Electron LimitedInventors: Seiji Matsuyama, Takuya Sugawara, Shigenori Ozaki, Toshio Nakanishi, Masaru Sasaki
-
Patent number: 7183143Abstract: A method for forming a nitrided tunnel oxide layer is described. A silicon oxide layer as a tunnel oxide layer is formed on a semiconductor substrate, and a plasma nitridation process is performed to implant nitrogen atoms into the silicon oxide layer. A thermal drive-in process is then performed to diffuse the implanted nitrogen atoms across the silicon oxide layer.Type: GrantFiled: October 27, 2003Date of Patent: February 27, 2007Assignee: Macronix International Co., Ltd.Inventor: Tzu-Yu Wang
-
Patent number: 7141514Abstract: A transistor gate selective re-oxidation process includes the steps of introducing into the vacuum chamber containing the semiconductor substrate a process gas that includes oxygen while maintaining a vacuum pressure in the chamber. An oxide insulating layer on the order of several Angstroms in thickness is formed by generating a plasma in a plasma generation region within the vacuum chamber during successive “on” times, and allowing ion energy of the plasma to decay during successive “off” intervals separating the successive “on” intervals, the “on” and “off” intervals defining a controllable duty cycle. During formation of the oxide insulating layer, the duty cycle is limited so as to limit formation of ion bombardment-induced defects in the insulating layer, while the vacuum pressure is limited so as to limit formation of contamination-induced defects in the insulating layer.Type: GrantFiled: February 2, 2005Date of Patent: November 28, 2006Assignee: Applied Materials, Inc.Inventor: Thai Cheng Chua
-
Patent number: 7129187Abstract: A method for low-temperature plasma-enhanced chemical vapor deposition of a silicon-nitrogen-containing film on a substrate. The method includes providing a substrate in a process chamber, exciting a reactant gas in a remote plasma source, thereafter mixing the excited reactant gas with a silazane precursor gas, and depositing a silicon-nitrogen-containing film on the substrate from the excited gas mixture in a chemical vapor deposition process. In one embodiment of the invention, the reactant gas can contain a nitrogen-containing gas to deposit a SiCNH film. In another embodiment of the invention, the reactant gas can contain an oxygen-containing gas to deposit a SiCNOH film.Type: GrantFiled: July 14, 2004Date of Patent: October 31, 2006Assignee: Tokyo Electron LimitedInventor: Raymond Joe
-
Patent number: 7098147Abstract: After a lower silicon oxide film is formed on a silicon region, a silicon film is formed on the lower silicon oxide film by, for example, a thermal CVD method. Subsequently, the silicon film is completely nitrided by a plasma nitriding method to be replaced by a silicon nitride film. Subsequently, a surface layer of the silicon nitride film is oxidized by a plasma oxidizing method to be replaced by an upper silicon oxide film. An ONO film as a multilayered insulating film composed of the lower silicon oxide film, the silicon nitride film, and the upper silicon oxide film is formed.Type: GrantFiled: August 20, 2003Date of Patent: August 29, 2006Assignee: Fujitsu Amd Semiconductor LimitedInventors: Hiroyuki Nansei, Manabu Nakamura, Kentaro Sera, Masahiko Higashi, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
-
Patent number: 7094641Abstract: A method is provided that is capable of forming a wiring pattern having an extremely flat surface and few convexo-concave shapes on a substrate on which the wiring pattern is formed. The method to form a wiring pattern includes a bank forming process, a conductive layer forming process and a transferring process. Here, a photothermal converting layer including a photothermal converting material that converts light energy to thermal energy and a sublimation layer including a sublimable material are stacked on a first substrate in this order. In the bank forming process, a first light irradiation is performed to a fixed region on a surface of the first substrate from the sublimation layer side so as to sublimate a part of the sublimation layer, thereby forming banks made of the sublimation layer to a region excluding the region for light irradiation. In the conductive layer forming process, a conductive layer is provided between the banks.Type: GrantFiled: July 30, 2004Date of Patent: August 22, 2006Assignee: Seiko Epson CorporationInventor: Naoyuki Toyoda
-
Patent number: 7045447Abstract: A semiconductor device producing method using a plasma processing apparatus including a processing chamber, a substrate-supporting body which supports a substrate in the processing chamber, and a cylindrical electrode and a magnetic lines of force-forming member disposed around the processing chamber, comprises forming an oxide film on the substrate, and thereafter, by changing a high frequency impedance of the substrate-supporting body, continuously forming an oxynitride film by nitriding the oxide film by activated species of nitrogen which are activated by plasma.Type: GrantFiled: March 26, 2003Date of Patent: May 16, 2006Assignee: Hitachi Kokusai Electric Inc.Inventors: Unryu Ogawa, Naoya Yamakado, Tadashi Terasaki, Shinji Yashima
-
Patent number: 7005389Abstract: Methods for forming a thin film on an integrated circuit device including providing energy to reactants in a deposition chamber to activate the reactants. The activated reactants are then deposited on the substrate to form a thin film on the substrate. The reactants selected may be selectively activated so that different thin films are formed in a single chamber thereby reducing processing time.Type: GrantFiled: March 31, 2004Date of Patent: February 28, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Hyun Ko, Ki-Hyun Hwang, Hyo-Jung Kim
-
Patent number: 7001855Abstract: A fabrication process of a flash memory device includes microwave excitation of high-density plasma in a mixed gas of Kr and an oxidizing gas or a nitriding gas. The resultant atomic state oxygen O* or hydrogen nitride radicals NH* are used for nitridation or oxidation of a polysilicon electrode surface. It is also disclosed the method of forming an oxide film and a nitride film on a polysilicon film according to such a plasma processing.Type: GrantFiled: February 7, 2003Date of Patent: February 21, 2006Assignee: Tadahiro OHMIInventors: Tadahiro Ohmi, Shigetoshi Sugawa
-
Patent number: 7000565Abstract: A plasma surface treatment system for irradiating a surface of a substrate to be treated with a nitrogen plasma excited by a high-frequency electric field to introduce nitrogen into the surface of the substrate comprises a pulse modulator for pulse modulation of the high-frequency electric field. By applying the high-frequency electric field in a pulsed form, it is possible to realize a nitriding by which the peak of nitrogen concentration is located at a shallower position and a desired nitrogen concentration can be obtained.Type: GrantFiled: March 17, 2004Date of Patent: February 21, 2006Assignee: Sony CorporationInventors: Seiichi Fukuda, Seiji Samukawa
-
Patent number: 6995097Abstract: An embodiment of the instant invention is a method of forming a dielectric layer on a silicon-containing structure, the method comprising the steps of: providing a nitrogen-containing gas; heating the silicon-containing structure to an elevated temperature which is greater than 700 C; and striking a plasma above the silicon-containing structure, wherein combination of the nitrogen-containing gas, the elevated temperature, and the plasma resulting in the thermal nitridation of a portion of the silicon-containing structure. Preferably, the elevated temperature is greater than 900 C (more preferably the elevated temperature is greater than 1000 C). The silicon-containing structure is, preferably, a silicon substrate or a bottom electrode of a storage capacitor of a memory device.Type: GrantFiled: May 27, 1998Date of Patent: February 7, 2006Assignee: Texas Instruments IncorporatedInventor: Richard Todd Goldberg
-
Patent number: 6992021Abstract: A method of forming a silicon nitride layer. The method comprises providing a substrate having a silicon surface thereon, performing an ion implant process on the silicon surface, implanting nitrogen atoms into the silicon surface, and performing a thermal nitridation process and forming a silicon nitride layer on the substrate, wherein the silicon nitride layer comprises the silicon nitride formed on the silicon surface by reaction of the silicon surface with the nitrogen atoms contained therein.Type: GrantFiled: July 16, 2003Date of Patent: January 31, 2006Assignee: Nanya Technology CorporationInventors: Shian-Jyh Lin, Hai-Han Hung, Chung-Yuan Lee
-
Patent number: 6933248Abstract: The instant invention describes a method for forming a dielectric film with a uniform concentration of nitrogen. The films are formed by first incorporating nitrogen into a dielectric film using RPNO. The films are then annealed in N2O which redistributes the incorporated species to produce a uniform nitrogen concentration.Type: GrantFiled: September 28, 2001Date of Patent: August 23, 2005Assignee: Texas Instruments IncorporatedInventor: Douglas T. Grider
-
Patent number: 6900092Abstract: The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.Type: GrantFiled: June 27, 2002Date of Patent: May 31, 2005Assignee: International Business Machines CorporationInventors: Atul C. Ajmera, Dominic J. Schepis, Michael D. Steigerwalt
-
Patent number: 6887798Abstract: A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.Type: GrantFiled: May 30, 2003Date of Patent: May 3, 2005Assignee: International Business Machines CorporationInventors: Sadanand V. Deshpande, Bruce B. Doris, Werner A. Rausch, James A. Slinkman
-
Patent number: 6855568Abstract: Disclosed are methods and apparatus for detecting defects in a partially fabricated semiconductor device with self-aligned contacts. The self-aligned contacts are formed from a first layer with a plurality of contact portions, a second layer with a plurality of conductive lines that are each aligned proximate to an associated underlying contact portion, and a third insulating layer formed over the conductive lines and their proximate underlying contact portions. The third insulating layer has a plurality of vias formed therein that are each formed alongside a one of the conductive lines and over its proximate underlying contact portion. A charged particle beam is scanned over a portion of the vias to form a voltage contrast image of each via. When a minority of the vias in the image have a significantly different brightness level than a majority of the vias, it is then determined that the minority of vias have defects.Type: GrantFiled: October 24, 2001Date of Patent: February 15, 2005Assignee: KLA-Tencor CorporationInventors: Kurt H. Weiner, Peter D. Nunan, Sanjay Tandon
-
Patent number: 6855644Abstract: The present invention provides a deposition method and deposition apparatus capable of forming a fluorine-containing silicon inorganic insulating film of stable film properties and a method of manufacturing a semiconductor device. Deposition apparatus 10 comprises parallel plate type electrodes 16, 22 arranged within reaction chamber 12, gas supply sources 20, 32, 34 for feeding process gas containing SiH4, SiF4 and oxygen source substance into reaction chamber 12, valves 36, 38, 40, gas mixing chamber 28 and power source 44 that supplies RF power for generating the plasma of the process gas. In this deposition apparatus 10, power source 44 is capable of supplying RF power of at least 1000 Watts to parallel plate type electrodes 16, 22. In this apparatus 10, fluorine-containing silicon oxide film is deposited on wafer 14 by generating the plasma of process gas containing SiH4, SiF4 and N2O.Type: GrantFiled: October 23, 2001Date of Patent: February 15, 2005Assignee: Applied Materials Inc.Inventors: Yoichi Suzuki, Tsutomu Shimayama
-
Patent number: 6852650Abstract: An insulation film is formed on a semiconductor substrate by vaporizing a silicon-containing hydrocarbon compound to provide a source gas, introducing a reaction gas composed of the source gas and an additive gas such as an inert gas and oxidizing gas to a reaction space of a plasma CVD apparatus. The residence time of the reaction gas in the reaction space is lengthened by reducing the total flow of the reaction gas in such a way as to form a siloxan polymer film with a low dielectric constant.Type: GrantFiled: November 5, 2002Date of Patent: February 8, 2005Assignee: ASM Japan K.K.Inventors: Nobuo Matsuki, Yasuyoshi Hyodo, Masashi Yamaguchi, Yoshinori Morisada, Atsuki Fukazawa, Manabu Kato
-
Patent number: 6849517Abstract: A method of fabricating an integrated circuit device having capacitors is provided. The capacitors can include a first electrode, a dielectric layer and a second electrode. An interlayer insulating layer is formed on the capacitor. The interlayer insulating layer is patterned to form a metal contact hole that exposes a region of the second electrode. The exposed region of the second electrode is reduced to remove excessive oxygen atoms that can exist in the second electrode.Type: GrantFiled: March 12, 2003Date of Patent: February 1, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hee Chung, Young-Sun Kim, Han-Mei Choi, Yun-Jung Lee
-
Publication number: 20040266214Abstract: An annealing furnace, includes a processing chamber configured to store a substrate; a susceptor located in the processing chamber so as to load the substrate and having an auxiliary heater for heating the substrate at 650° C. or less, the susceptor having a surface being made of quartz; a gas supply system configured to supply a gas required for a thermal processing on the substrate in parallel to a surface of the substrate; a transparent window located on an upper part of the processing chamber facing the susceptor; and a main heater configured to irradiate a pulsed light on the surface of the substrate to heat the substrate from the transparent window, the pulsed light having a pulse duration of approximately 0.1 ms to 200 ms and having a plurality of emission wavelengths.Type: ApplicationFiled: September 15, 2003Publication date: December 30, 2004Inventors: Kyoichi Suguro, Takayuki Ito, Takaharu Itani
-
Publication number: 20040259380Abstract: A plasma surface treatment system for irradiating a surface of a substrate to be treated with a nitrogen plasma excited by a high-frequency electric field to introduce nitrogen into the surface of the substrate comprises a pulse modulator for pulse modulation of the high-frequency electric field. By applying the high-frequency electric field in a pulsed form, it is possible to realize a nitriding by which the peak of nitrogen concentration is located at a shallower position and a desired nitrogen concentration can be obtained.Type: ApplicationFiled: March 17, 2004Publication date: December 23, 2004Inventors: Seiichi Fukuda, Seiji Samukawa
-
Publication number: 20040259379Abstract: A method of low-temperature nitridation of a silicon substrate includes placing a silicon wafer in a vacuum chamber on a heated chuck; maintaining the silicon wafer at a temperature of between about room temperature and 400° C.; introducing a nitrogen-containing gas into the vacuum chamber; dissociating the nitrogen-containing gas into nitrogen with a excimer lamp and flowing the nitrogen over the silicon wafer; and forming an silicon nitride layer on at least a portion of the silicon wafer.Type: ApplicationFiled: June 23, 2003Publication date: December 23, 2004Inventor: Yoshi Ono
-
Patent number: 6831021Abstract: Embodiments of the invention generally provide a method of forming a nitride gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via introduction of a nitrogen-containing processing gas into the processing chamber and the application of an ionizing energy to the processing gas, and pulsing the ionizing energy to maintain a mean temperature of electrons in the nitrogen-containing plasma of less than about 0.7 eV.Type: GrantFiled: June 12, 2003Date of Patent: December 14, 2004Assignee: Applied Materials, Inc.Inventors: Tal Cheng Chua, Philip Allan Kraus, John Holland
-
Publication number: 20040242021Abstract: A method and apparatus for forming a nitrided gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via a smooth-varying modulated RF power source to reduce electron temperature spike. Field effect transistor channel mobility and gate leakage current results are improved when the power source is smooth-varying modulated, as compared to square-wave modulated.Type: ApplicationFiled: April 6, 2004Publication date: December 2, 2004Applicant: Applied Materials, Inc.Inventors: Philip A. Kraus, Thai Cheng Chua
-
Patent number: 6825133Abstract: A method of forming a charge balanced, silicon dioxide layer gate insulator layer on a semiconductor substrate, with reduced leakage obtained via nitrogen treatments, has been developed. Prior to thermal growth of a silicon dioxide gate insulator layer, negatively charged fluorine ions are implanted into a top portion of a semiconductor substrate. The thermal oxidation procedure results in the growth of a silicon dioxide layer with incorporated, negatively charged fluorine ions. Subsequent nitrogen treatments, used to reduce gate insulator leakage, result in generation of positive charge in the exposed silicon dioxide layer, compensating the negatively charged fluorine ions and resulting in the desired charge balanced, silicon dioxide gate insulator layer.Type: GrantFiled: January 22, 2003Date of Patent: November 30, 2004Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mo-Chiun Yu, Shyue-Shyh Lin
-
Publication number: 20040227196Abstract: Part of a first oxide film formed by thermal oxidation is removed by etching. A second oxide film is formed in the part of substrate from which the first oxide film has been removed using heated nitric acid. The two oxide films are nitrided by a nitrogen plasma having a low energy so as to be first and second gate insulating films, i.e., oxynitride films, respectively.Type: ApplicationFiled: February 10, 2004Publication date: November 18, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Kenji Yoneda
-
Patent number: 6780719Abstract: An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% O2); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.Type: GrantFiled: June 20, 2001Date of Patent: August 24, 2004Assignee: Texas Instruments IncorporatedInventors: Hiroaki Niimi, Rajesh Khamankar, James J. Chambers, Sunil Hattangady, Antonio L. P. Rotondaro
-
Patent number: 6780720Abstract: A method of fabricating a gate dielectric layer. The method comprises: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; exposing the silicon dioxide layer to a plasma nitridation to convert the silicon dioxide layer into a silicon oxynitride layer; and performing a spiked rapid thermal anneal of the silicon oxynitride layer.Type: GrantFiled: July 1, 2002Date of Patent: August 24, 2004Assignee: International Business Machines CorporationInventors: Jay S. Burnham, Anthony I. Chou, Toshiharu Furukawa, Margaret L. Gibson, James S. Nakos, Steven M. Shank
-
Patent number: 6773999Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate, and a gate electrode formed on the gate insulating film. Nitrogen is introduced into the gate insulating film, and the nitrogen concentration distribution thereof has a peak near the surface of the gate insulating film or near the center of the gate insulating film in the thickness direction. The peak value of nitrogen concentration in the gate insulating film is equal to or greater than 10 atm % and less than or equal to 40 atm %.Type: GrantFiled: July 16, 2002Date of Patent: August 10, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Kenji Yoneda
-
Publication number: 20040132315Abstract: The present invention forms a nitrided dielectric layer without substantial harm to a semiconductor layer on which the dielectric layer is formed. The invention employs a multi-stage process in which dielectric sub-layers are individually nitrided before formation of a next dielectric sub-layer. The net result is a nitrided multi-layered dielectric layer comprised of a plurality of dielectric sub-layers wherein the sub-layers have been individually deposited and incorporated with nitrogen.Type: ApplicationFiled: January 3, 2003Publication date: July 8, 2004Inventors: James Joseph Chambers, Mark Visokay, Luigi Colombo
-
Patent number: 6737362Abstract: The present disclosure provides a method for forming a gate stack structure for semiconductor devices. The disclosed method comprises steps such as forming a dielectric layer on a substrate; applying a plasma nitridation process on the formed dielectric layer; applying a first anneal process on the deposited dielectric layer; etching the dielectric layer to a predetermined thickness using a diluted etchant; applying a second anneal process using an oxygen environment on the etched dielectric layer after the etching; and forming a gate electrode layer on top of the dielectric layer. The etching makes the top portion of the etched dielectric layer have a significantly higher concentration of nitrogen than the lower portion of the etched dielectric layer so as the leakage current is significantly reduced.Type: GrantFiled: February 28, 2003Date of Patent: May 18, 2004Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia Lin Chen, Chun-Lin Wu, Chi-Chun Chen, Tze Liang Lee, Shih-Chang Chen
-
Patent number: 6734113Abstract: The present invention provides a method for forming multiple gate oxide layers with different thickness in one chip by using a simple process. Particularly, a series of processes such as the first oxidation, the nitridation, the wet dip-out and the second oxidation contribute to form the gate oxide layer having different thicknesses. As a result, it is possible to integrate those various devices having different driving voltages into one chip. It is further possible to manufacture diverse products with improvements on layout design and device and process margins.Type: GrantFiled: June 24, 2003Date of Patent: May 11, 2004Assignee: Hynix Semiconductor Inc.Inventors: Heung-Jae Cho, Kwan-Yong Lim
-
Patent number: 6730550Abstract: To provide a laser apparatus and a laser annealing method with which a crystalline semiconductor film with a larger crystal grain size is obtained and which are low in their running cost. A solid state laser easy to maintenance and high in durability is used as a laser, and laser light emitted therefrom is linearized to increase the throughput and to reduce the production cost as a whole. Further, both the front side and the back side of an amorphous semiconductor film is irradiated with such laser light to obtain the crystalline semiconductor film with a larger crystal grain size.Type: GrantFiled: August 10, 2000Date of Patent: May 4, 2004Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hisashi Ohtani, Koichiro Tanaka, Kenji Kasahara, Ritsuko Kawasaki
-
Patent number: 6723595Abstract: The present invention discloses a method of fabricating a thin film in a chamber where a heater and a suscepter are located. The method includes the steps of disposing an object on the susceptor so as to form the thin film thereon; heating the object; a first sub-step of introducing a first gaseous reactant into the first chamber such that the first gaseous reactant is absorbed on the object to form an absorption layer; a second sub-step of introducing a second gaseous reactant into the first chamber such that the second gaseous reactant reacts with the absorption layer absorbed on the object; and a third sub-step of introducing a reducing gas into the first camber such that the reducing gas reduces by-products and impurities of the first and second gaseous reactants.Type: GrantFiled: February 1, 2002Date of Patent: April 20, 2004Assignee: Jusung Engineering Co., Ltd.Inventor: Chang-Boo Park
-
Patent number: 6723663Abstract: For aggressively scaled field effect transistors, nitrogen is incorporated into a base oxide layer, wherein, at an initial phase of a plasma nitridation process, the nitrogen ion density is maintained at a value so that incorporation of nitrogen into the channel region is minimized. Subsequently, when the thickness of the base oxide layer has increased, due to residual oxygen in the plasma ambient, the nitrogen ion density is increased, thereby increasing the nitridation rate. Preferably, the nitrogen ion density is controlled by varying the pressure of the plasma ambient. Moreover, a system is disclosed that allows control of the nitridation rate in response to an oxide layer thickness.Type: GrantFiled: May 22, 2003Date of Patent: April 20, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Karsten Wieczorek, Falk Graetsch, Lutz Herrmann
-
Patent number: 6713383Abstract: A surface of a copper (Cu) wiring layer formed over a semiconductor substrate is exposed to a plasma gas selected from the group consisting of an ammonia gas, a mixed gas of nitrogen and hydrogen, a CF4 gas, a C2F6 gas and a NF3 gas. The surface of the copper (Cu) wiring layer is then exposed to an atmosphere or a plasma of a gas selected from the group consisting of an ammonia gas, an ethylenediamine gas, a fÀ-diketone gas, a mixed gas consisting of the ammonia gas and a hydrocarbon gas (CxHy), and a mixed gas consisting of a nitrogen gas and the hydrocarbon gas (CxHy), and a Cu diffusion preventing insulating film is formed on the copper (Cu) wiring layer.Type: GrantFiled: July 30, 2002Date of Patent: March 30, 2004Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.Inventors: Yoshimi Shioya, Yuhko Nishimoto, Tomomi Suzuki, Shoji Ohgawara, Kazuo Maeda
-
Publication number: 20040053510Abstract: A system and method of a RAM cell write circuit of a multi-ported RAM cell, including a first Field Effect Transistor (FET) having a gate connected to a first port not write bitline, and a second FET having a gate connected to a first port write wordline and, clear logic controlled by the first bitline and first wordline, the clear logic setting the memory element to a first value when said first bitline and said first wordline are active.Type: ApplicationFiled: September 16, 2002Publication date: March 18, 2004Inventors: Casey J. Little, Reid J. Riedlinger
-
Publication number: 20040043570Abstract: With regard to a semiconductor apparatus thermally stable in a post process and suitable for fabricating a gate insulator having a laminated structure with various high permittivity oxides and a process of producing the same, in order to achieve high function formation of a gate insulator 8, a silicon nitride film specific inductive capacity of which is approximately twice as much as that of silicon oxide and which is thermally stable and is not provided with Si—H bond, is used as at least a portion of the gate insulator 8. Further, an effective thickness of a gate insulator forming a multilayered structure insulator laminated with a metal oxide having high dielectric constant, in conversion to silicon oxide, can be thinned to less than 3 nm while restraining leakage current.Type: ApplicationFiled: August 28, 2003Publication date: March 4, 2004Applicants: Hitachi, Ltd., Tokyo Institute of TechnologyInventors: Yoshihisa Fujisaki, Hiroshi Ishihara
-
Publication number: 20040038486Abstract: Embodiments of the invention generally provide a method of forming a nitride gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via introduction of a nitrogen-containing processing gas into the processing chamber and the application of an ionizing energy to the processing gas, and pulsing the ionizing energy to maintain a mean temperature of electrons in the nitrogen-containing plasma of less than about 0.7 eV.Type: ApplicationFiled: June 12, 2003Publication date: February 26, 2004Applicant: APPLIED MATERIALS, INC.Inventors: Thai Cheng Chua, Philip Allan Kraus, John Holland
-
Patent number: 6682979Abstract: The invention encompasses a method of forming an oxide region over a semiconductor substrate. A nitrogen-containing layer is formed across at least some of the substrate. After the nitrogen-containing layer is formed, an oxide region is grown from at least some of the substrate. The nitrogen of the nitrogen-containing layer is dispersed within the oxide region. The invention also encompasses a method of forming a pair of transistors associated with a semiconductor substrate. A substrate is provided. A first region of the substrate is defined, and additionally a second region of the substrate is defined. A first oxide region is formed which covers at least some of the first region of the substrate, and which does not cover any of the second region of the substrate. A nitrogen-comprising layer is formed across at least some of the first oxide region and across at least some of the second region of the substrate.Type: GrantFiled: September 12, 2001Date of Patent: January 27, 2004Assignee: Micron Technology, Inc.Inventor: John T. Moore
-
Publication number: 20040005788Abstract: Methods of forming thin nitride dielectric layers for semiconductor devices are provided. Additionally, methods of forming capacitor structures utilizing thin nitride dielectric layers are provided. The thin nitride layers are formed by nitridizing the surface of a doped or undoped semiconductor substrate using a remote plasma nitridization or a rapid thermal nitridization to form a first growth of silicon nitride. A self-limiting second growth of silicon nitride is formed using a remote plasma nitridization. The resulting silicon nitride layers exhibit improved dielectric and leakage characteristics.Type: ApplicationFiled: July 3, 2002Publication date: January 8, 2004Inventors: Fernando Gonzalez, John Zhang, Er-Xuan Ping
-
Publication number: 20040002226Abstract: A method of fabricating a gate dielectric layer. The method comprises: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; exposing the silicon dioxide layer to a plasma nitridation to convert the silicon dioxide layer into a silicon oxynitride layer; and performing a spiked rapid thermal anneal of the silicon oxynitride layer.Type: ApplicationFiled: July 1, 2002Publication date: January 1, 2004Applicant: International Business Machines CorporationInventors: Jay S. Burnham, Anthony I. Chou, Toshiharu Furukawa, Margaret L. Gibson, James S. Nakos, Steven M. Shank
-
Publication number: 20030235962Abstract: A method of manufacturing a semiconductor integrated circuit device comprising forming a silicon oxide film as thin as 5 nm or less on the surfaces of p type wells and n type wells by wet oxidizing a substrate, heating the substrate in an atmosphere containing about 5% of an NO gas to introduce nitrogen into the silicon oxide film so as to form a silicon oxynitride film, exposing the substrate to a nitrogen plasma atmosphere to further introduce nitrogen into the silicon oxynitride film in order to form a silicon oxynitride gate insulating film having a first peak concentration near the interface with the substrate and a second peak concentration near the surface thereof. Thereby, the concentration of nitrogen in the gate insulating film is increased without raising the concentration of nitrogen near the interface between the substrate and the gate insulating film to a higher level than required.Type: ApplicationFiled: June 20, 2003Publication date: December 25, 2003Inventors: Dai Ishikawa, Satoshi Sakai, Atsushi Hiraiwa
-
Patent number: 6660659Abstract: According to one aspect of the invention, a method is provided of processing a substrate, including locating the substrate in a processing chamber, creating a nitrogen plasma in the chamber, the plasma having an ion density of at least 1010 cm−3, and a potential of less than 20 V, and exposing a layer on the substrate to the plasma to incorporate nitrogen of the plasma into the layer.Type: GrantFiled: June 12, 2002Date of Patent: December 9, 2003Assignee: Applied Materials, Inc.Inventors: Philip Allan Kraus, Thai Cheng Chua, John Holland, James P. Cruse
-
Patent number: 6660658Abstract: The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer.Type: GrantFiled: July 26, 2002Date of Patent: December 9, 2003Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, John T. Moore, Neal R. Rueger