Microwave Gas Energizing Patents (Class 438/777)
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Patent number: 7176094Abstract: DPN (decoupled plasma nitridation) is used to improve robustness of ultra thin gate oxides. Conventionally, this is followed by an anneal in pure helium to remove structural defects in the oxide. However, annealing under these conditions has been found to cause a deterioration of the electrical performance of devices. This problem has been overcome by annealing, in a 1:4 oxygen-nitrogen mixture (1,050° C. at about 10 torr) instead of in helium or nitrogen oxide. This results in a gate oxide that is resistant to boron contamination without suffering any loss in its electrical properties.Type: GrantFiled: March 6, 2002Date of Patent: February 13, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Dong Zhong, Yun Ling Tan, Chew Hoe Ang, Jia Zhen Zheng
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Patent number: 7135416Abstract: A method of manufacturing a semiconductor device including a gallium nitride related semiconductor. The method include preparing a substrate having surface of a gallium nitride related semiconductor; contacting the surface with atomic nitrogen, which is obtained by decomposing a nitrogen-containing gas in a catalytic reaction, to nitride the surface; and forming, on the surface, a gate electrode and source and drain electrodes opposing each other across the gate electrode.Type: GrantFiled: February 25, 2004Date of Patent: November 14, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masahiro Totsuka, Tomoki Oku
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Patent number: 7129187Abstract: A method for low-temperature plasma-enhanced chemical vapor deposition of a silicon-nitrogen-containing film on a substrate. The method includes providing a substrate in a process chamber, exciting a reactant gas in a remote plasma source, thereafter mixing the excited reactant gas with a silazane precursor gas, and depositing a silicon-nitrogen-containing film on the substrate from the excited gas mixture in a chemical vapor deposition process. In one embodiment of the invention, the reactant gas can contain a nitrogen-containing gas to deposit a SiCNH film. In another embodiment of the invention, the reactant gas can contain an oxygen-containing gas to deposit a SiCNOH film.Type: GrantFiled: July 14, 2004Date of Patent: October 31, 2006Assignee: Tokyo Electron LimitedInventor: Raymond Joe
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Patent number: 7115530Abstract: A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing a dielectric layer on a substrate and subjecting the dielectric layer to a plasma to reduce top surface roughness in the dielectric layer.Type: GrantFiled: December 3, 2003Date of Patent: October 3, 2006Assignee: Texas Instruments IncorporatedInventors: Manuel A. Quevedo-Lopez, James J. Chambers, Luigi Colombo, Mark R. Visokay
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Patent number: 7098147Abstract: After a lower silicon oxide film is formed on a silicon region, a silicon film is formed on the lower silicon oxide film by, for example, a thermal CVD method. Subsequently, the silicon film is completely nitrided by a plasma nitriding method to be replaced by a silicon nitride film. Subsequently, a surface layer of the silicon nitride film is oxidized by a plasma oxidizing method to be replaced by an upper silicon oxide film. An ONO film as a multilayered insulating film composed of the lower silicon oxide film, the silicon nitride film, and the upper silicon oxide film is formed.Type: GrantFiled: August 20, 2003Date of Patent: August 29, 2006Assignee: Fujitsu Amd Semiconductor LimitedInventors: Hiroyuki Nansei, Manabu Nakamura, Kentaro Sera, Masahiko Higashi, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Patent number: 7091136Abstract: A process of forming a compound film includes formulating a nano-powder material with a controlled overall composition and including particles of one solid solution. The nano-powder material is deposited on a substrate to form a layer on the substrate, and the layer is reacted in at least one suitable atmosphere to form the compound film. The compound film may be used in fabrication of a radiation detector or solar cell.Type: GrantFiled: April 11, 2002Date of Patent: August 15, 2006Inventor: Bulent M. Basol
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Patent number: 7067415Abstract: A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide comprising interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the carbon comprising dielectric layer, it is exposed to a plasma comprising oxygen effective to reduce the dielectric constant to below what it was prior to said exposing. A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. In a chamber, an interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is plasma enhanced chemical vapor deposited over the substrate at subatmospheric pressure.Type: GrantFiled: July 25, 2002Date of Patent: June 27, 2006Assignee: Micron Technology, Inc.Inventors: Weimin Li, Zhiping Yin, William Budge
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Patent number: 7067414Abstract: A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide-comprising inter-level dielectric layer including carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the dielectric layer, it is exposed to a plasma including oxygen effective to reduce the dielectric constant to below what it was prior to the exposing. A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least patially formed thereon. In a chamber, an inter-level dielectric layer including carbon and having a dielectric constant no greater than 3.5 is plasma-enhanced chemical vapor deposited over the substrate at subatmospheric pressure.Type: GrantFiled: March 27, 2000Date of Patent: June 27, 2006Assignee: Micron Technology, Inc.Inventors: Weimin Li, Zhiping Yin, William Budge
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Patent number: 7056381Abstract: Concentration of metal element which promotes crystallization of silicon and which exists within a crystal silicon film obtained by utilizing the metal element is reduced. A first heat treatment for crystallization is implemented after introducing nickel to an amorphous silicon film 103. Then, laser light is irradiated to diffuse the nickel element concentrated locally. After that, another heat treatment is implemented within an oxidizing atmosphere at a temperature higher than that of the previous heat treatment. A thermal oxide film 106 is formed in this step. At this time, the nickel element is gettered to the thermal oxide film 106. Then, the thermal oxide film 106 is removed. Thereby, a crystal silicon film 107 having low concentration of the metal element and a high crystallinity can be obtained.Type: GrantFiled: January 16, 1997Date of Patent: June 6, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Teramoto, Jun Koyama, Yasushi Ogata, Masahiko Hayakawa, Mitsuaki Osame
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Patent number: 7056836Abstract: In a method for manufacturing a semiconductor device, a first silicon oxide film is formed on a semiconductor substrate. The first silicon oxide film is nitrided so that silicon oxynitride forms at an interface between the semiconductor substrate and the first silicon oxide film. The first silicon oxide film is removed from a portion of the semiconductor substrate using a chemical containing at least an ammonia-hydrogen peroxide solution so that the silicon oxynitride formed at the interface between the portion of the semiconductor substrate and the first silicon oxide film is completely removed. Thereafter, a second silicon oxide film is formed in the portion of the semiconductor substrate from which the first silicon oxide film and the silicon oxynitride have been removed.Type: GrantFiled: July 10, 2003Date of Patent: June 6, 2006Assignee: Seiko Instruments Inc.Inventor: Hitomi Watanabe
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Patent number: 7033958Abstract: A semiconductor apparatus is provided that is thermally stable in a post process and is suitable for fabricating a gate insulator having a laminated structure with various high permittivity oxides, and a process is provided for producing the same. In order to achieve a high function formation of a gate insulator, a silicon nitride film having a specific inductive capacity approximately twice as much as that of silicon oxide, and which is thermally stable, is not provided with a Si—H bond and is used as at least a portion of the gate insulator. Further, an effective thickness of a gate insulator forming a multilayered structure insulator laminated with a metal oxide having a high dielectric constant, in conversion to silicon oxide, can be thinned to less than 3 nm while restraining leakage current.Type: GrantFiled: August 28, 2003Date of Patent: April 25, 2006Assignees: Hitachi, Ltd., Tokyo Institute of Technology.Inventors: Yoshihisa Fujisaki, Hiroshi Ishihara
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Patent number: 7005389Abstract: Methods for forming a thin film on an integrated circuit device including providing energy to reactants in a deposition chamber to activate the reactants. The activated reactants are then deposited on the substrate to form a thin film on the substrate. The reactants selected may be selectively activated so that different thin films are formed in a single chamber thereby reducing processing time.Type: GrantFiled: March 31, 2004Date of Patent: February 28, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Hyun Ko, Ki-Hyun Hwang, Hyo-Jung Kim
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Patent number: 6967130Abstract: A method of forming dual gate insulator layers, each with a specific insulator thickness, featuring a HF type pre-clean procedure performed prior to formation of each of the gate insulator layers, has been developed. After a first HF type pre-clean procedure a silicon nitride layer is deposited on the native oxide free, semiconductor substrate followed by selective removal of silicon nitride layer from a second portion of the semiconductor substrate. After a second HF type pre-clean procedure a silicon dioxide gate insulator layer is formed on the second portion of the native oxide free, semiconductor substrate, with the silicon dioxide gate insulator layer comprised with a different thickness than the silicon nitride gate insulator layer, located on a first portion of the semiconductor substrate. The procedure used to form the silicon dioxide gate insulator layer also removes bulk traps in the silicon nitride gate insulator layer.Type: GrantFiled: June 20, 2003Date of Patent: November 22, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Chun Chen, Tzu-Liang Lee, Shih-Chang Chen
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Patent number: 6933248Abstract: The instant invention describes a method for forming a dielectric film with a uniform concentration of nitrogen. The films are formed by first incorporating nitrogen into a dielectric film using RPNO. The films are then annealed in N2O which redistributes the incorporated species to produce a uniform nitrogen concentration.Type: GrantFiled: September 28, 2001Date of Patent: August 23, 2005Assignee: Texas Instruments IncorporatedInventor: Douglas T. Grider
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Patent number: 6924239Abstract: The present invention is generally directed towards a method for removing hydrocarbon contamination from a substrate prior to a nitridation step, therein providing for a generally uniform nitridation of the substrate. The method comprises placing the substrate in a process chamber and flowing an oxygen-source gas into the process chamber. A first plasma is formed in the process chamber for a first predetermined amount of time, wherein the hydrocarbons combine with one or more species of the oxygen-source gas in radical form to form product gases. The gases are removed from the process chamber and a nitrogen-source gas is flowed into the process chamber. A second plasma is then formed in the process chamber for a second predetermined amount of time, therein nitriding the substrate in a significantly uniform manner.Type: GrantFiled: October 14, 2003Date of Patent: August 2, 2005Assignee: Texas Instruments IncorporatedInventors: Hiroaki Niimi, Husam N. Alshareef, Ajith Varghese
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Patent number: 6887798Abstract: A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.Type: GrantFiled: May 30, 2003Date of Patent: May 3, 2005Assignee: International Business Machines CorporationInventors: Sadanand V. Deshpande, Bruce B. Doris, Werner A. Rausch, James A. Slinkman
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Patent number: 6861366Abstract: The present invention provides a packaged semiconductor device that includes two semiconductor die. The first semiconductor die is attached to a package substrate using adhesive. A first set of wire bonds electrically connect the first semiconductor die to the package substrate. A first layer of encapsulant extends over the first semiconductor die and over the first set of wire bonds. A second semiconductor die is attached to the first layer of encapsulant using adhesive. A second set of wire bonds electrically connect the second semiconductor die to the package substrate. A second layer of encapsulant extends over the second semiconductor die and over the second set of wire bonds.Type: GrantFiled: August 27, 2003Date of Patent: March 1, 2005Assignee: Integrated Device Technology, Inc.Inventor: Anne T. Katz
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Patent number: 6855568Abstract: Disclosed are methods and apparatus for detecting defects in a partially fabricated semiconductor device with self-aligned contacts. The self-aligned contacts are formed from a first layer with a plurality of contact portions, a second layer with a plurality of conductive lines that are each aligned proximate to an associated underlying contact portion, and a third insulating layer formed over the conductive lines and their proximate underlying contact portions. The third insulating layer has a plurality of vias formed therein that are each formed alongside a one of the conductive lines and over its proximate underlying contact portion. A charged particle beam is scanned over a portion of the vias to form a voltage contrast image of each via. When a minority of the vias in the image have a significantly different brightness level than a majority of the vias, it is then determined that the minority of vias have defects.Type: GrantFiled: October 24, 2001Date of Patent: February 15, 2005Assignee: KLA-Tencor CorporationInventors: Kurt H. Weiner, Peter D. Nunan, Sanjay Tandon
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Patent number: 6780719Abstract: An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% O2); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.Type: GrantFiled: June 20, 2001Date of Patent: August 24, 2004Assignee: Texas Instruments IncorporatedInventors: Hiroaki Niimi, Rajesh Khamankar, James J. Chambers, Sunil Hattangady, Antonio L. P. Rotondaro
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Patent number: 6777346Abstract: A planarization process for filling spaces between patterned metal features formed over a surface of a semiconductor substrate. The patterned metal features are preferably coated with a dielectric barrier. The dielectric barrier is coated with an material that expands during oxidation or nitridization to a thickness about half the depth of the space between metallized features. The layer is then plasma oxidized using an RF or ECR plasma at low temperature with an oxygen ambient. Alternatively, the layer is plasma nitridized at low temperature. The plasma oxidation or nitridization is continued until the expandable material is converted to a dielectric and has expanded to fill the space between patterned metal features. Optionally, the process can be followed by a mechanical or chemical mechanical planarization step.Type: GrantFiled: April 14, 1998Date of Patent: August 17, 2004Assignee: Micron Technology, Inc.Inventor: Ravi Iyer
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Patent number: 6773999Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate, and a gate electrode formed on the gate insulating film. Nitrogen is introduced into the gate insulating film, and the nitrogen concentration distribution thereof has a peak near the surface of the gate insulating film or near the center of the gate insulating film in the thickness direction. The peak value of nitrogen concentration in the gate insulating film is equal to or greater than 10 atm % and less than or equal to 40 atm %.Type: GrantFiled: July 16, 2002Date of Patent: August 10, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Kenji Yoneda
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Publication number: 20040142577Abstract: A process for producing electronic device (for example, high-performance MOS-type semiconductor device) structure having a good electric characteristic, wherein an SiO2 film or SiON film is used as an insulating film having an extremely thin (2.5 nm or less, for example) film thickness, and poly-silicon, amorphous-silicon, or SiGe is used as an electrode. In the presence of process gas comprising oxygen and an inert gas, plasma including oxygen and the inert gas (or plasma comprising nitrogen and an inert gas, or plasma comprising nitrogen, an inert gas and hydrogen) is generated by irradiating a wafer W including Si as a main component with microwave via a plane antenna member SPA. An oxide film (or oxynitride film) is formed on the wafer surface by using the thus generated plasma, and as desired, an electrode of poly-silicon, amorphous-silicon, or SiGe is formed, to thereby form an electronic device structure.Type: ApplicationFiled: July 18, 2003Publication date: July 22, 2004Inventors: Takuya Sugawara, Toshio Nakanishi, Shigenori Ozaki, Seiji Matsuyama, Shigemi Murakawa, Yoshihide Tada
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Publication number: 20040043570Abstract: With regard to a semiconductor apparatus thermally stable in a post process and suitable for fabricating a gate insulator having a laminated structure with various high permittivity oxides and a process of producing the same, in order to achieve high function formation of a gate insulator 8, a silicon nitride film specific inductive capacity of which is approximately twice as much as that of silicon oxide and which is thermally stable and is not provided with Si—H bond, is used as at least a portion of the gate insulator 8. Further, an effective thickness of a gate insulator forming a multilayered structure insulator laminated with a metal oxide having high dielectric constant, in conversion to silicon oxide, can be thinned to less than 3 nm while restraining leakage current.Type: ApplicationFiled: August 28, 2003Publication date: March 4, 2004Applicants: Hitachi, Ltd., Tokyo Institute of TechnologyInventors: Yoshihisa Fujisaki, Hiroshi Ishihara
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Patent number: 6699796Abstract: A single chip pad oxide layer growth process is disclosed. First, a silicon chip is sent into a reaction chamber, which is filled with hydrogen and oxygen. A rapid thermal process is employed to increase the temperature inside the chamber to about 850° C. to 1100° C. to grow a SiO2 layer. The error on the final temperature after the rapid thermal process can be controlled to fluctuate within one to two degrees.Type: GrantFiled: June 14, 2002Date of Patent: March 2, 2004Assignee: Macronix International Co., Ltd.Inventor: Chin-Ta Su
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Publication number: 20030232491Abstract: A reduction of a leakage current as well as a decrease in the thickness of an insulating film is realized in a semiconductor device. To this end, a silicon oxide film and a silicon nitride film are formed on a substrate, which is then heated to a temperature within a range of 20° C.-600° C. so that a plasma nitridation process can be performed on the silicon nitride film. Further, a thermal process is performed in a non-oxide gas atmosphere. By performing these processes, the gate leakage current can be significantly reduced in the formed gate insulator, and the silicon oxide-equivalent thickness of the insulating film can be significantly decreased as well.Type: ApplicationFiled: January 27, 2003Publication date: December 18, 2003Applicant: FUJITSU LIMITEDInventor: Akihisa Yamaguchi
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Patent number: 6660658Abstract: The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer.Type: GrantFiled: July 26, 2002Date of Patent: December 9, 2003Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, John T. Moore, Neal R. Rueger
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Patent number: 6660657Abstract: The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer.Type: GrantFiled: August 7, 2000Date of Patent: December 9, 2003Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, John T. Moore, Neal R. Rueger
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Patent number: 6649535Abstract: A method for forming an ultra-thin (between about 15 to 20 Angstroms), silicon dioxide gate insulator layer, featuring a process sequence which widens the process window of the thermal oxidation procedure, and improves the quality of the ultra-thin silicon dioxide gate insulator layer, has been developed. After a series of wet clean procedures applied to a semiconductor substrate, a high temperature anneal procedure is performed in an inert ambient. The high temperature anneal removes organic, as well as inorganic material not removed during the wet clean procedures, and also removes native oxide formed during these same wet clean procedures. The removal of these materials allow the use of longer thermal oxidation times still resulting in silicon dioxide thickness equal to counterparts formed using shorter oxidation times, which were not subjected to the pre-oxidation high temperature anneal procedure.Type: GrantFiled: February 12, 2002Date of Patent: November 18, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Mo-Chiun Yu, Shih-Chang Chen
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Publication number: 20030207592Abstract: A method of forming a capacitor includes forming first and second capacitor electrodes over a substrate. A capacitor dielectric region is formed intermediate the first and second capacitor electrodes, and includes forming a silicon nitride comprising layer over the first capacitor electrode. A silicon oxide comprising layer is formed over the silicon nitride comprising layer. The silicon oxide comprising layer is exposed to an activated nitrogen species generated from a nitrogen-containing plasma effective to introduce nitrogen into at least an outermost portion of the silicon oxide comprising layer. Silicon nitride is formed therefrom effective to increase a dielectric constant of the dielectric region from what it was prior to said exposing. Capacitors and methods of forming capacitor dielectric layers are also disclosed.Type: ApplicationFiled: April 17, 2003Publication date: November 6, 2003Inventors: John T. Moore, Scott J. DeBoer
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Patent number: 6620702Abstract: Methods are presented for reducing the thermal budget in a semiconductor manufacturing process that include for instance, depositing high dielectric constant films to form MIS capacitors, where processes including plasma nitridation and oxidation and deposition processes including ALD and PVD are selectively employed to lower the overall thermal budget thereby allowing smaller structures to be reliably manufactured.Type: GrantFiled: June 25, 2001Date of Patent: September 16, 2003Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wong-Cheng Shih, Lan-Lin Chao
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Patent number: 6617260Abstract: The present invention provides a manufacturing method of a semiconductor device which does not give rise to peeling of a metal film caused by oxygen held in a interlayer insulating film even when the wafer is subjected to a heat treatment after the metal film is formed on the interlayer insulating film. After the formation of the interlayer insulating film, oxygen held in the interlayer insulating film is removed from the interlayer insulating film, then a metal film on the interlayer insulating film.Type: GrantFiled: October 2, 2001Date of Patent: September 9, 2003Assignee: NEC Electronics CorporationInventors: Takayuki Abe, Yasuhide Den
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Patent number: 6610614Abstract: A method of forming an ultra-thin dielectric layer, including the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density.Type: GrantFiled: June 20, 2001Date of Patent: August 26, 2003Assignee: Texas Instruments IncorporatedInventors: Hiroaki Niimi, Sunil Hattangady, Rajesh Khamankar
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Patent number: 6610615Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes nitridizing a thin silicon oxide film in a low power, direct plasma formed from nitrogen. A gas having a lower ionization energy than nitrogen, such as for example, helium, may be used in combination with nitrogen to produce a lower power plasma resulting in a steeper concentration curve for nitrogen in the silicon oxide film.Type: GrantFiled: November 15, 2000Date of Patent: August 26, 2003Assignee: Intel CorporationInventors: Robert McFadden, Jack Kavalieros, Reza Arghavani, Doug Barlage, Robert Chau
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Publication number: 20030052377Abstract: Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing silicon onto an oxide substrate as a thin layer, and then thermally annealing the silicon layer in a nitrogen-containing species or exposing the silicon to a plasma source of nitrogen to nitridize the silicon layer.Type: ApplicationFiled: September 6, 2002Publication date: March 20, 2003Applicant: Micron Technology Inc.Inventor: Ronald A. Weimer
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Patent number: 6534421Abstract: The invention grows SiO2 films over silicon at temperatures as low as room temperature and at pressures as high as 1 atmosphere. The lower temperature oxidation is made possible by creation of oxygen atoms and radicals by adding noble gas(es) along with oxidizing gas(es) and applying RF power to create plasma. The invention also fabricates silicon nitride films by flowing nitrogen containing gas(es) with noble gas(es) and applying RF power to create plasma at pressures as high as one atmosphere. In addition, the above processes can also be performed using microwave power instead of RF power to create plasma.Type: GrantFiled: August 27, 2001Date of Patent: March 18, 2003Assignee: Seiko Epson CorporationInventor: Ramesh H. Kakkad
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Patent number: 6528434Abstract: The present invention provides a method of forming different thickness” of a gate oxide layer simultaneously, by employing a pulse Nitrogen plasma implantation. The method provides a semiconductor substrate with the surface of the silicon in the semiconductor substrate separated into a first region and a second region at least. Then a thin surface on the surface of the silicon of the first region is implanted using a first predetermined concentration of the Nitrogen ions. The thin surface on the surface of the silicon in the second region is implanted using a second predetermined concentration of the Nitrogen ions. An oxidation process is subsequently performed. The first predetermined thickness and the second predetermined thickness of the silicon oxide layer are formed simultaneously on the surface of the silicon in the first region and in the second region. The Nitrogen ions are implanted in the surface of the silicon by forming the pulse nitrogen plasma in-situ.Type: GrantFiled: October 22, 2001Date of Patent: March 4, 2003Assignee: Macronix International Co. Ltd.Inventor: Wei-Wen Chen
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Patent number: 6518203Abstract: The present invention describes a method of processing a substrate. According to the present invention a dielectric layer is formed on the substrate. The dielectric layer is then exposed in a first chamber to activated nitrogen atoms formed in a second chamber to form a nitrogen passivated dielectric layer. A metal nitride film is then formed on the nitrogen passivated dielectric layer.Type: GrantFiled: October 18, 2001Date of Patent: February 11, 2003Assignee: Applied Materials, Inc.Inventors: Pravin Narwankar, Turgut Sahin
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Publication number: 20020142622Abstract: A metal wiring buried in an insulating layer is subjected to a reducing treatment prior to formation of a second insulating layer on the insulating layer under the condition that the total partial pressure of oxygen and water vapor is sufficiently low.Type: ApplicationFiled: March 28, 2002Publication date: October 3, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Tadashi Iijima, Tadayoshi Watanabe
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Patent number: 6436848Abstract: A nitrogen-rich silicon oxide layer is formed using an apparatus for oxidizing semiconductor substrates having a process zone or chamber fluidically coupled to a torch zone or chamber. Generally, a thin initial silicon oxide layer is formed on the substrate using common wet or dry oxidizing processing conditions. Subsequently, a nitridizing atmosphere is introduced to the semiconductor substrates causing a nitrogen-rich silicon oxide layer to be formed thereon. The nitridizing atmosphere is advantageously generated by an exothermic reaction within the torch zone. Once formed, the nitridizing atmosphere is directed to the process zone through the fluidic coupling. The advantageous exothermic reaction resulting from the introduction of nitrous oxide (N2O) to the torch zone at a temperature sufficiently high to induce such an exothermic reaction, generally between approximately 850 to 950 degrees Celsius. Semiconductor integrated circuits are formed using nitrogen-rich silicon oxide films of the current method.Type: GrantFiled: March 30, 1999Date of Patent: August 20, 2002Assignee: Cypress Semiconductor Corp.Inventor: Krishnaswamy Ramkumar
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Patent number: 6413881Abstract: A process for inhibiting the passage of dopant from a gate electrode into a thin gate oxide comprises nitridation of the upper surface of the thin gate oxide, prior to formation of the gate electrode over the gate oxide, to thereby form a barrier of nitrogen atoms in the upper surface region of the gate oxide adjacent the interface between the gate oxide and the gate electrode to inhibit passage of dopant atoms from the gate electrode into the thin gate oxide during annealing of the structure. In one embodiment, a selective portion of silicon oxide on a silicon substrate may be etched to thin the oxide to the desired thickness using a nitrogen plasma with a bias applied to the silicon substrate. Nitridation of the surface of the etched silicon oxide is then carried out in the same apparatus by removing the bias from the silicon substrate.Type: GrantFiled: March 9, 2000Date of Patent: July 2, 2002Assignee: LSI Logic CorporationInventors: Sheldon Aronowitz, John Haywood, James P. Kimball, Helmut Puchner, Ravindra Manohar Kapre, Nicholas Eib
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Publication number: 20020055270Abstract: The present invention describes a method of processing a substrate. According to the present invention a dielectric layer is formed on the substrate. The dielectric layer is then exposed in a first chamber to activated nitrogen atoms formed in a second chamber to form a nitrogen passivated dielectric layer. A metal nitride film is then formed on the nitrogen passivated dielectric layer.Type: ApplicationFiled: October 18, 2001Publication date: May 9, 2002Inventors: Pravin Narwankar, Turgut Sahin
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Method for forming composite gate dielectric layer equivalent to silicon oxide gate dielectric layer
Patent number: 6380104Abstract: A method for forming upon a semiconductor substrate employed within a microelectronics fabrication a composite gate insulating layer of MOS device comprising a silicon oxide dielectric layer and a high-K dielectric layer. The method employs thermal oxidation of a silicon semiconductor substrate to form an initial silicon oxide dielectric layer. A RPN plasma method is employed to form a layer of silicon nitride high-k dielectric material partly into the silicon oxide dielectric layer. The composite dielectric layer is dielectrically equivalent to the initial silicon oxide dielectric layer, with equivalent performance, reliability and manufacturability of the MOS device.Type: GrantFiled: August 10, 2000Date of Patent: April 30, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventor: Mo-Chiun Yu -
Publication number: 20020039835Abstract: In the fabrication of EDRAM/SDRAM silicon chips with ground rules beyond 0.18 microns, a Si3N4 barrier layer is deposited onto the patterned structure during the borderless polysilicon contact fabrication. It is required that this layer be conformal and has a high hydrogen atom content to prevent junction leakage. These objectives are met with the method of the present invention. In a first embodiment, the Si3N4 layer is deposited in a Rapid Thermal Chemical Vapor Deposition (RTCVD) reactor using a NH3/SiH4 chemistry at a temperature and a pressure in the 600-950° C. and 50-200 Torr ranges respectively. In a second embodiment, it is deposited in a Low Pressure Chemical Vapor Deposition (LPCVD) furnace using a NH3/SiH2Cl2 chemistry (preferred ratio 1:1) at a temperature and a pressure in the 640-700° C. and 0.2-0.8 Torr ranges respectively.Type: ApplicationFiled: June 27, 2001Publication date: April 4, 2002Applicant: International Business Machines CorporationInventors: Christophe Balsan, Corinne Buchet, Patrick Raffin, Stephane Thioliere
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Patent number: 6358808Abstract: In a method of manufacturing a semiconductor device, an insulating film is formed on a semiconductor substrate. A semiconductor film pattern is formed on the insulating film. A direct thermal nitriding method is performed to at least a portion of the semiconductor film pattern. The direct thermal nitriding method is performed by lamp annealing in a gas composed of nitrogen such that a thermally nitrided film has a film thickness of equal to or thicker than 1.5 nm. Thus, invasion of a hydrogen atom or ion into the semiconductor film pattern can be prevented.Type: GrantFiled: November 16, 2000Date of Patent: March 19, 2002Assignee: NEC CorporationInventor: Tatsuya Usami
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Patent number: 6337289Abstract: The present invention describes a method of processing a substrate. According to the present invention a dielectric layer is formed on the substrate. The dielectric layer is then exposed in a first chamber to activated nitrogen atoms formed in a second chamber to form a nitrogen passivated dielectric layer. A metal nitride film is then formed on the nitrogen passivated dielectric layer.Type: GrantFiled: September 24, 1999Date of Patent: January 8, 2002Assignee: Applied Materials. IncInventors: Pravin Narwankar, Turgut Sahin
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Patent number: 6294832Abstract: The present invention is related to a interconnection structure with Cu interconnects and low-k dielectric, in which a barrier dielectric liner made of a nitrogen-containing liquid-phase-deposition (LPD) fluorosilicate glass (FSG) film is used to replace a barrier metal layer and an oxide liner.Type: GrantFiled: April 10, 2000Date of Patent: September 25, 2001Assignee: National Science CouncilInventors: Ching-Fa Yeh, Yueh-Chuan Lee, Kwo-Hau Wu, Yuh-Ching Su
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Patent number: 6287889Abstract: An improved gas phase synthesized diamond, CBN, BCN, or CN thin film having a modified region in which strain, defects, color and the like are reduced and/or eliminated. The thin film can be formed on a substrate or be a free-standing thin film from which the substrate has been removed. The thin film can be stably and reproducibly modified to have an oriented polycrystal structure or a single crystal structure. The thin film is modified by being subjected to and heated by microwave irradiation in a controlled atmosphere. The thin film has a modified region in which a line width of the diamond spectrum evaluated by Raman spectroscopy of 0.1 microns or greater is substantially constant along a film thickness direction of the thin film, and the line width of the modified region is 85% or less of a maximum line width of the residual portion of the film thickness.Type: GrantFiled: January 26, 2000Date of Patent: September 11, 2001Assignee: Applied Diamond, Inc.Inventors: Shoji Miyake, Shu-Ichi Takeda
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Patent number: 6150226Abstract: In one aspect, the invention includes a method of densifying a silicon nitride layer comprising: after forming the silicon nitride layer, exposing the silicon nitride layer to atomic nitrogen, the exposing not increasing a thickness of the silicon nitride layer by more than about 10 Angstroms. In another aspect, the invention includes a method of densifying a silicon nitride layer comprising: after forming the silicon nitride layer, exposing the silicon nitride layer to atomic nitrogen in the substantial absence of a silicon-containing gas.Type: GrantFiled: February 3, 1998Date of Patent: November 21, 2000Assignee: Micron Technology, Inc.Inventor: Alan R. Reinberg
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Patent number: 6136654Abstract: An embodiment of the instant invention is a method of forming a dielectric layer, the method comprising the steps of: providing a semiconductor substrate (substrate 12), the substrate having a surface; forming an oxygen-containing layer (layer 14) on the semiconductor substrate; and subjecting the oxygen-containing layer to a nitrogen containing plasma (plasma 16) so that the nitrogen is either incorporated into the oxygen-containing layer (see regions 18, 19, and 20) or forms a nitride layer at the surface of the substrate (region 22). Using this embodiment of the instant invention, the dielectric layer can be substantially free of hydrogen. Preferably, the oxygen-containing layer is an SiO.sub.2 layer or it is comprised of oxygen and nitrogen (preferably an oxynitride layer). The plasma is, preferably, a high-density plasma. Preferably, a source of nitrogen is introduced to the plasma to form the nitrogen containing plasma. The source of nitrogen is preferably comprised of a material consisting of: N.sub.Type: GrantFiled: December 4, 1997Date of Patent: October 24, 2000Assignee: Texas Instruments IncorporatedInventors: Robert Kraft, Sunil Hattangady, Douglas T. Grider