Subsequent Heating Modifying Organic Coating Composition Patents (Class 438/781)
  • Patent number: 11905204
    Abstract: According to an embodiment, a cover glass includes a glass plate forming at least a portion of an electronic device, and a first coat layer deposited on a surface of the glass plate, the first coat layer at least partially including a network structure. The first coat layer includes silicon (Si), oxygen (O), and at least one impurity, and such that Si—O bonds are 80% or more by weight of the first coat layer. A polysilazane-applied coat is laid over one surface of the reinforced glass plate, providing an elegant haze glass cover.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wook-Tae Kim, In-Gi Kim, Ji-Won Lee, Chang-Soo Lee, Hyung-jin Lee, Gyu-Ha Jo, Yong-Hyun Cho
  • Patent number: 11739220
    Abstract: A Si-containing film forming composition comprising a catalyst and/or a polysilane and a N—H free, C-free, and Si-rich perhydropolysilazane having a molecular weight ranging from approximately 332 dalton to approximately 100,000 dalton and comprising N—H free repeating units having the formula [—N(SiH3)x(SiH2-)y], wherein x=0, 1, or 2 and y=0, 1, or 2 with x+y=2; and x=0, 1 or 2 and y=1, 2, or 3 with x+y=3. Also disclosed are synthesis methods and applications for using the same.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: August 29, 2023
    Assignees: L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude, American Air Liquide, Inc.
    Inventors: Antonio Sanchez, Gennadiy Itov, Manish Khandelwal, Cole Ritter, Peng Zhang, Jean-Marc Girard, Zhiwen Wan, Glenn Kuchenbeiser, David Orban, Sean Kerrigan, Reno Pesaresi, Matthew Damien Stephens, Yang Wang, Guillaume Husson, Grigory Nikiforov
  • Patent number: 11446699
    Abstract: Methods and apparatus for vapor deposition of an organic film are configured to vaporize an organic reactant at a first temperature, transport the vapor to a reaction chamber housing a substrate, and maintain the substrate at a lower temperature than the vaporization temperature. Alternating contact of the substrate with the organic reactant and a second reactant in a sequential deposition sequence can result in bottom-up filling of voids and trenches with organic film in a manner otherwise difficult to achieve.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: September 20, 2022
    Assignee: ASM IP HOLDING B.V.
    Inventors: Viljami J. Pore, Marko Tuominen, Hannu Huotari
  • Patent number: 11401384
    Abstract: According to the present invention, a siliceous film forming composition, which is capable of filling trenches having narrow widths and high aspect ratios and forming a thick film, can be provided. A siliceous film forming composition comprising: (a) a block copolymer comprising a linear and/or cyclic block A having a polysilane skeleton comprising 5 or more silicon and a block B having a polysilazane skeleton comprising 20 or more silicon, and (b) a solvent.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: August 2, 2022
    Assignee: MERCK PATENT GMBH
    Inventors: Takashi Fujiwara, Atsuhiko Sato
  • Patent number: 11389824
    Abstract: Methods and apparatus for vapor deposition of an organic film are configured to vaporize an organic reactant at a first temperature, transport the vapor to a reaction chamber housing a substrate, and maintain the substrate at a lower temperature than the vaporization temperature. Alternating contact of the substrate with the organic reactant and a second reactant in a sequential deposition sequence can result in bottom-up filling of voids and trenches with organic film in a manner otherwise difficult to achieve. Deposition reactors conducive to depositing organic films are provided.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: July 19, 2022
    Assignee: ASM IP HOLDING B.V.
    Inventors: Viljami J. Pore, Marko Tuominen, Hannu Huotari
  • Patent number: 11309180
    Abstract: The disclosure provides an ultra-low K dielectric layer and a manufacturing method thereof, the manufacturing method comprising: forming an ultra-low K dielectric layer on a substrate; forming a thin oxygen layer on the upper surface of the ultra-low K dielectric layer; performing plasma purge on the ultra-low K dielectric layer after forming the thin oxygen layer using oxygen; and the plasma purge lasts for more than 2 seconds. The ultra-low K dielectric layer manufactured according to the manufacturing method provided by the disclosure has a smooth surface, overcomes the original bump defects of the ultra-low K dielectric layer, and improves the performance of the ultra-low K dielectric layer. The manufacturing method of the ultra-low K dielectric layer provided by the disclosure has a simple process, is compatible with the manufacturing process of the existing ultra-low K dielectric layer, and has operability.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: April 19, 2022
    Assignee: Shanghai Huali Integrated Circuit Mfg. Co. Ltd
    Inventor: Yiqi Gong
  • Patent number: 11282699
    Abstract: There is provided a substrate processing apparatus including: a processing container having a vacuum atmosphere formed therein; a stage provided within the processing container and configured to place a substrate on the stage; a film-forming gas supply part configured to supply a film-forming gas for forming an organic film on the substrate placed on the stage; and a heating part configured to heat the substrate placed on the stage in a non-contact manner so as to remove a surface portion of the organic film.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: March 22, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Syuji Nozawa, Tatsuya Yamaguchi
  • Patent number: 11078569
    Abstract: Described herein are compositions and methods for forming silicon and oxygen containing films. In one aspect, the film is deposited from at least one precursor, wherein the at least one precursor selected from the group consisting of Formulae A and B: wherein R, R1, and R2-8 are as defined herein.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: August 3, 2021
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Xinjian Lei, Matthew R. MacDonald, Meiliang Wang
  • Patent number: 11037696
    Abstract: A transparent electrode including: a first layer including a thermosetting copolymer including a first repeating unit having an aromatic moiety as a pendant group or incorporated in a backbone of the copolymer and a second repeating unit capable of lowering a curing temperature, a combination of a first polymer including the first repeating unit and a second polymer including the second repeating unit, or a combination thereof; a second layer disposed directly on one side of the first layer, wherein the second layer includes graphene; and a third layer disposed on the second layer, wherein the third layer includes an electrically conductive metal nanowire.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeon Cheol Park, Youngjin Cho, Daejin Yang, Chan Kwak, Kwanghee Kim, Weonho Shin, Yun Sung Woo
  • Patent number: 11016386
    Abstract: A method of forming a photoresist pattern includes forming a protective layer over a photoresist layer formed on a substrate, and selectively exposing the protective layer and the photoresist layer to actinic radiation. The protective layer and the photoresist layer are developed to form a pattern in the photoresist layer, and the protective layer is removed. The protective layer includes a polymer having pendant fluorocarbon groups and pendant acid leaving groups.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Ren Zi, Chin-Hsiang Lin, Ching-Yu Chang
  • Patent number: 10968364
    Abstract: A plasma polymerized thin film having low dielectric constant prepared by depositing a first precursor material represented by the following Chemical Formula 1: wherein in the above Chemical Formula 1, R1 to R14 are each independently H or a substituted or non-substituted C1-C5 alkyl group, and when the R1 to R14 are substituted, their substituents comprise an amino group, a hydroxyl group, a cyano group, a halogen group, a nitro group, or a methoxy group.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 6, 2021
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Donggeun Jung, Wonjin Ban, Sungyool Kwon, Yoonsoo Park, Hyuna Lim, Younghyun Kim
  • Patent number: 10923560
    Abstract: A capacitor includes a first electrode; a second electrode facing the first electrode; and a dielectric layer which is disposed between the first electrode and the second electrode and which is in contact with the first electrode. The first electrode includes a first portion including an interface between the first electrode and the dielectric layer, the dielectric layer includes a second portion including the interface, and the first portion and the second portion each contain silicon. A concentration distribution of the silicon along a thickness direction of the first portion and the second portion includes a convex portion intersecting the interface.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: February 16, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takahiro Koyanagi, Yuuko Tomekawa, Takeshi Harada, Yoshio Kawashima
  • Patent number: 10814349
    Abstract: Methods and apparatus for vapor deposition of an organic film are configured to vaporize an organic reactant at a first temperature, transport the vapor to a reaction chamber housing a substrate, and maintain the substrate at a lower temperature than the vaporization temperature. Alternating contact of the substrate with the organic reactant and a second reactant in a sequential deposition sequence can result in bottom-up filling of voids and trenches with organic film in a manner otherwise difficult to achieve. Deposition reactors conducive to depositing organic films are provided.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: October 27, 2020
    Assignee: ASM IP HOLDING B.V.
    Inventors: Viljami J. Pore, Marko Tuominen, Hannu Huotari
  • Patent number: 10544170
    Abstract: Provided are an organosilicon compound capable of improving the storage stability of a composition (curability after long-term storage); and a method for producing the same. The organosilicon compound has, in one molecule, at least one carboxylic acid ester group represented by the following general formula (1) and at least one hydrolyzable silyl group represented by the following general formula (2): —OC(?O)CH2R1??(1) wherein R1 represents a hydrogen atom or a methyl group; —SiR23-nYn??(2) wherein R2 represents a substituted or unsubstituted monovalent hydrocarbon group having 1 to 12 carbon atoms, Y represents a hydrolyzable group, and n represents an integer satisfying 1?n?3.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: January 28, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Taiki Katayama, Isao Iwasaki, Takafumi Sakamoto
  • Patent number: 10483099
    Abstract: A method of forming a thermally stable organosilicon polymer includes: (i) depositing an organosilicon polymer whose backbone is composed of silicon atoms on a substrate using a silicon-containing precursor in a reaction space; and (ii) exposing the organosilicon polymer deposited in step (i) to a hydrogen plasma in the absence of the precursor in the reaction space in a manner increasing Si—H bonds and decreasing C—H bonds in the organosilicon polymer without depositing an organosilicon polymer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: November 19, 2019
    Assignee: ASM IP Holding B.V.
    Inventor: Timothee Julien Vincent Blanquart
  • Patent number: 10229879
    Abstract: An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Kevin J. Fischer, Christopher M. Pelto, Andrew W. Yeoh
  • Patent number: 10151981
    Abstract: Some embodiments include methods of forming structures supported by semiconductor substrates. Radiation-imageable material may be formed over a substrate and patterned into at least two separated features. A second material may be formed over the features and across one or more gaps between the features. At least one substance may be released from the features and utilized to alter a portion of the second material. The altered portion of the second material may be selectively removed relative to another portion of the second material which is not altered. Also, the features of radiation-imageable material may be selectively removed relative to the altered portion of the second material. The second material may contain one or more inorganic components dispersed in an organic composition. The substance released from the features of radiation-imageable material may be acid which forms cross-links within such organic composition, an hydroxyl, or any other suitable substance.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: December 11, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Anton deVilliers
  • Patent number: 10056460
    Abstract: A semiconductor device includes: a semiconductor layer; a first insulating film which covers a surface of the semiconductor layer; a first adhering film which is formed on a surface of the first insulating film and contains a carbonyl group; and a second insulating film which covers a surface of the first adhering film and has a lower dielectric constant than the first insulating film.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: August 21, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Naoya Okamoto
  • Patent number: 9911596
    Abstract: A modification processing method includes preparing a substrate having a silicon layer on which a damage layer is formed through plasma processing. The method further includes removing the damage layer formed on the silicon layer by processing the substrate with a first process gas containing a fluorine gas.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: March 6, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tamotsu Morimoto, Yusuke Muraki, Kazuaki Nishimura
  • Patent number: 9862595
    Abstract: A method for manufacturing a film support beam includes: providing a substrate having opposed first and second surfaces; coating a sacrificial layer on the first surface of the substrate, and patterning the sacrificial layer; depositing a dielectric film on the sacrificial layer to form a dielectric film layer, and depositing a metal film on the dielectric film layer to form a metal film layer; patterning the metal film layer, and dividing a patterned area of the metal film layer into a metal film pattern of a support beam portion and a metal film pattern of a non-support beam portion, wherein a width of the metal film pattern of the support beam portion is greater than a width of a final support beam pattern, and a width of the metal film pattern of the non-support beam portion is equal to a width of a width of a final non-support beam pattern at the moment; photoetching and etching on the metal film layer and the dielectric film layer to obtain the final support beam pattern, the final non-support beam patt
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: January 9, 2018
    Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.
    Inventor: Errong Jing
  • Patent number: 9721785
    Abstract: A method of manufacturing a silica layer includes: coating a pre-wetting liquid material including a carbon compound on a substrate; coating a composition for forming a silica layer on the substrate coated with the pre-wetting liquid material; and curing a substrate coated with the composition for forming a silica layer.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: August 1, 2017
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Jiho Lee, Kunbae Noh, Huichan Yun, Jin-Hee Bae, Wanhee Lim
  • Patent number: 9644127
    Abstract: A heating medium composition for solar thermal power generation system, the heating medium composition including a silane coupling agent represented by formula (1) shown below and a heating medium containing diphenyl ether: (1) wherein each of OR1, OR2 and OR3 may be the same or different, and represents an alkoxy group of 1 to 5 carbon atoms, and X is a group selected from a 3-glycidoxypropyl group, a 3-methacryloxypropyl group, a 3-aminopropyl group, an N-phenyl-3-aminopropyl group and an N-2-(aminoethyl)-3-aminopropyl group.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: May 9, 2017
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Takashi Ono, Yasuo Suzuki, Salvador Valenzuela Rubia, Hipolito Lobato Sanchez, Alfonso Rodriguez Sanchez, Cristina Prieto Rios
  • Patent number: 9443724
    Abstract: A modification processing method includes preparing a substrate having a silicon layer on which a damage layer is formed through plasma processing. The method further includes removing the damage layer formed on the silicon layer by processing the substrate with a first process gas containing a fluorine gas.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: September 13, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Tamotsu Morimoto, Yusuke Muraki, Kazuaki Nishimura
  • Patent number: 9405201
    Abstract: A method includes forming a patterned hard mask layer, with a trench formed in the patterned hard mask layer, dispensing a Bulk Co-Polymer (BCP) coating in the trench, wherein the BCP coating comprises a mix of a first material and a second material different from the first material. The method further includes treating the BCP coating with a chemical to form a first plurality of strips of the first material and a second plurality of strips of the second material, with the first plurality of strips and the second plurality of strips allocated in an alternating layout. The second plurality of strips is selectively etched, and the first plurality of strips is left in the trench.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Sheng Chang
  • Patent number: 9296132
    Abstract: The invention relates: to a process for forming a texture on a substrate, comprising: depositing a deformable layer on the substrate; bringing this deformable layer into contact with the textured face of a daughter stamp; introducing the coated substrate and the daughter stamp into a pouch made of an impermeable material; introducing the pouch and its contents into a hermetic vessel; evacuating air from the vessel until a pressure at most equal to 0.5 bar is reached; sealing the pouch before reintroducing air into the vessel; introducing the sealed pouch and its contents into an autoclave; applying a pressure comprised between 0.5 and 8 bar and a temperature comprised between 25 and 400° C.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 29, 2016
    Assignee: SAINT-GOBAIN GLASS FRANCE
    Inventors: Nicolas Chemin, Jeremie Teisseire, Elin Sondergard
  • Patent number: 9159559
    Abstract: The present disclosure provides a method for forming resist patterns. The method includes providing a substrate; forming a material layer including a plurality of quenchers on the substrate; forming a resist layer on the material layer; exposing the resist layer; and developing the resist layer to form a structure featuring resist remaining layer on an upper surface of the material layer, and a plurality of resist features on the resist remaining layer to improve the yield of lithography process.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Chieh Chien, Shu-Hao Chang, Jui-Ching Wu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9159913
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: October 13, 2015
    Assignee: Unity Semiconductor Corporation
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • Patent number: 9117666
    Abstract: A method is provided for activating an exposed surface of a porous dielectric layer, the method comprising the steps of: filling with a first liquid at least the pores present in a part of the porous dielectric layer, the part comprising the exposed surface, removing the first liquid selectively from the surface, activating the exposed surface, and removing the first liquid from the bulk part of the porous dielectric layer.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: August 25, 2015
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU Leuven R&D
    Inventors: Quoc Toan Le, Mikhail Baklanov, Yiting Sun, Silvia Armini
  • Patent number: 9059259
    Abstract: A method of fabricating an interconnect structure on a wafer and an interconnect structure are provided. A dielectric layer is provided on the wafer. An interconnect is formed by etching a recess into the dielectric layer, where the etching utilizes a hard mask that includes a first layer deposited over the dielectric layer. The interconnect is planarized using a chemical mechanical polishing (CMP) process, where the first layer remains on the dielectric layer at a completion of the CMP process. The first layer or a portion of the first layer is transformed into a nitride layer or an oxide layer after the CMP process.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: June 16, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Joung-Wei Liou, Han-Ti Hsiaw, Keng-Chu Lin
  • Patent number: 9048066
    Abstract: A method is for etching successive substrates on a platen in an inductively coupled plasma chamber in which the etching process results in carbonaceous deposits in the chamber. The method includes (a) interrupting the etching processing of substrates, (b) running an oxygen or oxygen containing plasma within the chamber and removing gaseous by-products, and (c) resuming the etch processing of substrates. The method is characterized in that it further includes the step of running an argon plasma in the chamber after step (b) with the platen biased.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: June 2, 2015
    Assignee: SPTS TECHNOLOGIES LIMITED
    Inventors: Stephen R Burgess, Alex Theodosiou
  • Publication number: 20150140837
    Abstract: The invention relates: to a process for forming a texture on a substrate, comprising: depositing a deformable layer on the substrate; bringing this deformable layer into contact with the textured face of a daughter stamp; introducing the coated substrate and the daughter stamp into a pouch made of an impermeable material; introducing the pouch and its contents into a hermetic vessel; evacuating air from the vessel until a pressure at most equal to 0.5 bar is reached; sealing the pouch before reintroducing air into the vessel; introducing the sealed pouch and its contents into an autoclave; applying a pressure comprised between 0.5 and 8 bar and a temperature comprised between 25 and 400° C.
    Type: Application
    Filed: May 14, 2013
    Publication date: May 21, 2015
    Applicant: SAINT-GOBAIN GLASS FRANCE
    Inventors: Nicolas Chemin, Jeremie Teisseire, Elin Sondergard
  • Patent number: 9029271
    Abstract: A method of patterning a block copolymer layer includes: providing a guide pattern on a surface of a substrate, the guide pattern including sidewalls each elongated in a longitudinal direction and spaced apart from each other, a trench defined by a bottom surface and facing surfaces of the sidewalls, and having a uniform width over an entire length thereof in the longitudinal direction, and a latitudinal wall perpendicular to the longitudinal direction of the trench; providing a block copolymer layer on the surface of the substrate; and annealing the block copolymer to cause self-assembly of the block copolymer and to direct the same in the trench. The block copolymer has a microphase-separation into anisotropic discrete domains aligned with a period ?o in the trench by the annealing.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youn Jung Park, Haeng Deog Koh, Mi-Jeong Kim, Seong-Jun Jeong
  • Patent number: 9029171
    Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao
  • Patent number: 9018107
    Abstract: A deposition for producing a porous organosilica glass film comprising: introducing into a vacuum chamber gaseous reagents including one precursor of an organosilane or an organosiloxane, and a porogen distinct from the precursor, wherein the porogen is aromatic in nature; applying energy to the gaseous reagents in the chamber to induce reaction of the gaseous reagents to deposit a film, containing the porogen; and removing substantially all of the organic material by UV radiation to provide the porous film with pores and a dielectric constant less than 2.6.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: April 28, 2015
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Mary Kathryn Haas, Raymond Nicholas Vrtis, Laura M. Matz
  • Patent number: 9018689
    Abstract: A substrate processing apparatus includes a source gas supply system including a source gas supply pipe connected to a source gas source and a source gas supply controller; a reactive gas supply system including a reactive gas supply pipe connected to a reactive gas source, a reactive gas supply controller, a plasma generation unit and an ion trap unit and an inert gas supply pipe whereat an inert gas supply controller is disposed; a processing chamber supplied with a source gas by the source gas supply system and a reactive gas by the reactive gas supply system; and a control unit configured to control the gas supply controllers. The inert gas supply pipe has a downstream side connected between the reactive gas supply controller and the plasma generation unit and an upstream side connected to an inert gas supply source.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: April 28, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yukitomo Hirochi, Naofumi Ohashi
  • Patent number: 9006019
    Abstract: A method for manufacturing a light-emitting device includes a step of forming an etching resistant protection layer on a substrate provided with an organic planarizing layer, a step of forming a plurality of electrodes on the etching resistant protection layer, a step of forming an organic compound layer on the substrate provided with the plurality of electrodes, a step of forming a resist layer on the organic compound layer formed on parts of electrodes among the plurality of electrodes using a photolithographic method, and a step of removing the organic compound layer in a region not covered with the resist layer by dry etching, wherein an entire surface of the organic planarizing layer on the substrate on which steps up to the step of forming the plurality of electrodes have been performed is covered with at least one of the etching resistant protection layer and the electrode.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 14, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Manabu Otsuka, Tomoyuki Hiroki
  • Patent number: 9000449
    Abstract: A semiconductor substrate that includes a semiconductor layer that exhibits high crystallinity includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine, and a semiconductor layer that is grown on the surface of the graphite layer, or includes a substrate that includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine on its surface, a buffer layer that is grown on the surface of the graphite layer, and a semiconductor layer that is grown on the surface of the buffer layer.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: April 7, 2015
    Assignees: The University of Tokyo, Tokai Carbon Co., Ltd., National Institute of Advanced Industrial Science and Technology
    Inventors: Hiroshi Fujioka, Tetsuro Hirasaki, Hitoshi Ue, Junya Yamashita, Hiroaki Hatori
  • Publication number: 20150091137
    Abstract: A method of forming nanostructures may include forming a block copolymer composition within a trench in a material on a substrate, wherein the block copolymer composition may comprise a block copolymer material and an activatable catalyst having a higher affinity for a first block of the block copolymer material compared to a second block of the block copolymer material; self-assembling the block copolymer composition into first domains comprising the first block and the activatable catalyst, and second domains comprising the second block; generating catalyst from the activatable catalyst in at least one portion of the first domains to produce a structure comprising catalyst-containing domains and the second domains, the catalyst-containing domains comprising the first block and the catalyst; and reacting a metal oxide precursor with the catalyst in the catalyst-containing domains to produce a metal oxide-containing structure comprising the first block and metal oxide.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Nicholas Hendricks, Adam L. Olson, William R. Brown, Ho Seop Eom, Xue Chen, Kaveri Jain, Scott Schuldenfrei
  • Patent number: 8993708
    Abstract: A carbazole polymer including a repeating unit represented by Formula 1 and having excellent one electron oxidation-state stability, wherein, in Formula 1, R1-R4 each independently represents an alkyl group having 1-60 carbon atoms, a haloalkyl group having 1-60 carbon atoms, or similar, Cz represents a divalent group including a carbazole skeleton represented by Formula 2, and Ar represents a divalent aromatic ring or similar; wherein, in Formula 2, R5 represents a hydrogen atom, an alkyl group having 1-60 carbon atoms, or similar, R6-R11 each independently represents a hydrogen atom, a halogen atom, or similar, and m represents an integer 1-10.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: March 31, 2015
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Yuki Shibano, Takuji Yoshimoto
  • Publication number: 20150072536
    Abstract: A photoresist pattern used for forming a pattern of a block copolymer is formed on a substrate, and then an acid solution is supplied and an alkaline solution is further supplied to the photoresist pattern so as to slim and smooth the photoresist pattern. A block copolymer solution is applied to the substrate on which the smoothed photoresist pattern has been formed, to form a film of the block copolymer, and the film is heated.
    Type: Application
    Filed: April 15, 2013
    Publication date: March 12, 2015
    Inventors: Makoto Muramatsu, Takahiro Kitano, Tadatoshi Tomita, Keiji Tanouchi
  • Patent number: 8975110
    Abstract: In a composition of forming a passivation layer, the composition includes about 30 to about 60 percent by weight of a mixed polymer resin formed by blending polyamic acid and polyhydroxy amide, about 3 to about 10 percent by weight of a photoactive compound, about 2 to about 10 percent by weight of a cross-linking agent and an organic solvent. The passivation layer formed by using the composition has superior mechanical and physical properties, in which disadvantages of polyimide and polybenzoxazole are compensated by mixing both materials.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: March 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-Young Kim, Chang-Ho Lee, Su-Min Park
  • Patent number: 8969219
    Abstract: The present invention relates to a method for preparation of an ultraviolet (UV)-curable inorganic-organic hybrid resin containing about or less than 4% volatiles and less than 30% organic residues. The UV-curable inorganic-organic hybrid resin obtained according to this method can be UV-cured within a markedly very short time and enables, upon curing, the formation of a transparent shrink-and crack-free glass-like product having high optical quality, high thermal stability and good bonding properties. In view of these properties, this hybrid resin can be used in various applications such as electro-optic, microelectronic, stereolithography and biophotonic applications.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: March 3, 2015
    Assignee: Soreq Nuclear Research Center
    Inventor: Raz Gvishi
  • Publication number: 20150056819
    Abstract: Methods and apparatus for processing a substrate are described herein. A vacuum multi-chamber deposition tool can include a degas chamber with both a heating mechanism and a variable frequency microwave source. The methods described herein use variable frequency microwave radiation to increased quality and speed of the degas process without damaging the various components.
    Type: Application
    Filed: July 2, 2014
    Publication date: February 26, 2015
    Inventors: Loke Yuen WONG, Ke CHANG, Yueh Sheng OW, Ananthkrishna JUPUDI, Glen T. MORI, Aksel KITOWSKI, Arkajit Roy BARMAN
  • Patent number: 8962494
    Abstract: The present invention provides method of manufacturing dual gate oxide devices. The method comprises coating photoresist on the substrate which is deposited by an oxide thin film; removing some of the photoresist by exposure and development to divide the oxide thin film into a first area to be etched and a second area coated by the remained photoresist; coating RELACS material on the remained photoresist and heating to form a protective film based on the crosslinking reaction between the RELACS material and the high molecular compounds in the photoresist; performing UV radiation to strengthen and cure the protective film; removing the oxide thin film in the first area by etching and removing the remained photoresist; and depositing again an oxide firm to form an oxide layer of different thickness in the first area and the second area so as to form a dual gate oxide structure.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: February 24, 2015
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Jun Huang, Zhibiao Mao, Ermin Chong
  • Publication number: 20150048487
    Abstract: The present invention relates to a plasma polymerized thin film having high hardness and a low dielectric constant and a manufacturing method thereof, and in particular, relates to a plasma polymerized thin film having high hardness and a low dielectric constant for use in semiconductor devices, which has improved mechanical strength properties such as hardness and elastic modulus while having a low dielectric constant, and a manufacturing method thereof.
    Type: Application
    Filed: February 11, 2014
    Publication date: February 19, 2015
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Dong Geun JUNG, Hoon Bae KIM, Hyo Jin OH, Chae Min LEE
  • Patent number: 8956981
    Abstract: A stabilizing solution for treating photoresist patterns and methods of preventing profile abnormalities, toppling and resist footing are disclosed. The stabilizing solution comprises a non-volatile component, such as non-volatile particles or polymers, which is applied after the photoresist material has been developed. By treating the photoresist with the solution containing a non-volatile component after developing but before drying, the non-volatile component fills the space between adjacent resist patterns and remains on the substrate during drying. The non-volatile component provides structural and mechanical support for the resist to prevent deformation or collapse by liquid surface tension forces.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: February 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jon Daley, Yoshiki Hishiro
  • Patent number: 8951922
    Abstract: The present invention relates to a method for fabricating an interlayer, and particularly relates to a method for fabricating an interlayer PCBM which is difficult to be dissolved in organic solvents. The solubility of the interlayer (PCBM) in organic solvents is decreased by polymerization of the interlayer (PCBM). Therefore, the thickness of the interlayer (PCBM) can be efficiently controlled, and the yield rate and efficiency of photoelectric devices can be improved.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: February 10, 2015
    Assignee: National Taiwan University
    Inventors: Ching-Fuh Lin, Kuei-Yu Cian, Shao-Hsuan Kao
  • Patent number: 8945305
    Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 8940648
    Abstract: A method for depositing a silicon containing film on a substrate using an organoaminosilane is described herein. The organoaminosilanes are represented by the formulas: wherein R is selected from a C1-C10 linear, branched, or cyclic, saturated or unsaturated alkyl group with or without substituents; a C5-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, or a silyl group in formula C with or without substituents, R1 is selected from a C3-C10 linear, branched, cyclic, saturated or unsaturated alkyl group with or without substituents; a C6-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, a hydrogen atom, a silyl group with substituents and wherein R and R1 in formula A can be combined into a cyclic group and R2 representing a single bond, (CH2), chain, a ring, C3-C10 branched alkyl, SiR2, or SiH2.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: January 27, 2015
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Manchao Xiao, Xinjian Lei, Heather Regina Bowen, Mark Leonard O'Neill
  • Publication number: 20150024607
    Abstract: Organoaluminum coating compositions are used to deposit films on various substrates, which films are subsequently cured to form oxide films useful in a variety of manufacturing applications, particularly where a gas barrier may be used.
    Type: Application
    Filed: July 22, 2013
    Publication date: January 22, 2015
    Inventors: Deyan WANG, Kathleen M. O'CONNELL, Peter TREFONAS, III