Subsequent Heating Modifying Organic Coating Composition Patents (Class 438/781)
  • Patent number: 8623741
    Abstract: In one exemplary embodiment, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to an exposed surface of the first layer; heating the structure to a first temperature to enable the filling material to homogeneously fill the plurality of pores; after filling the plurality of pores, performing at least one process on the structure; and after performing the at least one process, removing the filling material from the plurality of pores by heating the structure to a second temperature to decompose the filling material.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Sampath Purushothaman, Geraud Jean-Michel Dubois, Teddie P. Magbitang, Willi Volksen, Theo J. Frot
  • Patent number: 8623745
    Abstract: There is provided a novel composition for forming a gate insulating film taking into consideration also electrical characteristics after other processes such as wiring by irradiation with an ultraviolet ray and the like during the production of an organic transistor using a gate insulating film. A composition for forming a gate insulating film for a thin-film transistor comprising: a component (i): an oligomer compound or a polymer compound containing a repeating unit having a structure in which a nitrogen atom of a triazine-trione ring is bonded to a nitrogen atom of another triazine-trione ring through a hydroxyalkylene group; and a component (ii): a compound having two or more blocked isocyanate groups in one molecule thereof.
    Type: Grant
    Filed: November 26, 2009
    Date of Patent: January 7, 2014
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Shinichi Maeda, Takahiro Kishioka
  • Patent number: 8618536
    Abstract: A planarization film is formed as a silicon oxide monolayer using, for instance, a spin coat method, through, for example, applying a silicon-containing organic solvent to an upper portion of a TFT layer and planarizing an upper surface of a resist film made up of a silicon-containing organic solvent, heating a predetermined processing fluid, e.g., peroxymonosulfuric acid, and discharging the processing fluid heated to, for example, 150° C., onto the planarized upper surface of the resist film such that organic components of the resist film are dissolved while silicon in the resist film is oxidized by the processing fluid.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 31, 2013
    Assignee: Panasonic Corporation
    Inventor: Kou Sugano
  • Patent number: 8603922
    Abstract: A method is described for manufacturing a semiconductor device that comprises the steps of providing on a substrate a layer of a conducting material in a pattern comprising isolated elements having a first set of edges. The method further includes providing, on the substrate, a series of wall structures for forming one or more cavities there between. The wall structures have a second set of edges cooperating with the first set of edges. The second set of edges is positioned outside the first set of edges by a pre-defined distance. The method furthermore includes depositing a liquid material in the cavities. A display and an electronic apparatus incorporating the above described features is also disclosed.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: December 10, 2013
    Assignee: Creator Technology B.V.
    Inventors: Christoph Wilhelm Sele, Nicolaas Aldegonda Jan Maria van Aerle, Eduard Jacobus Antonius Lassauw
  • Patent number: 8603923
    Abstract: This invention relates to a dipping solution used in a process for producing a siliceous film. The present invention provides a dipping solution and a siliceous film-production process employing the solution. The dipping solution enables to form a homogeneous siliceous film even in concave portions of a substrate having concave portions and convex portions. The substrate is coated with a polysilazane composition, and then dipped in the solution before fire. The dipping solution comprises hydrogen peroxide, a foam-deposit inhibitor, and a solvent.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: December 10, 2013
    Inventor: Masanobu Hayashi
  • Publication number: 20130316545
    Abstract: A method of forming a polyimide film on a surface of a substrate by dehydration condensation of a first monomer including a bifunctional acid anhydride and a second monomer including a bifunctional amine is disclosed. The method includes loading the substrate into a processing chamber, heating the substrate at a temperature at which a polyimide film is formed, and performing a cycle a predetermined number of times. The cycle comprises supplying a first processing gas containing the first monomer to the substrate, supplying a second processing gas containing the second monomer to the substrate. The method further includes supplying a replacement gas in the processing chamber between supplying the first processing gas and supplying the second processing gas thereby replacing atmosphere in the processing chamber by the replacement gas, and evacuating the first and/or the second processing gas out of the processing chamber.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 28, 2013
    Inventors: Tatsuya YAMAGUCHI, Reiji NIINO
  • Patent number: 8592261
    Abstract: A semiconductor device may be designed in the following manner. A stacked layer of a silicon oxide film and an organic film is provided over a substrate, deuterated water is contained in the organic film, and then a conductive film is formed in contact with the organic film. Next, an inert conductive material that does not easily generate a deuterium ion or a deuterium molecule is selected by measuring the amount of deuterium that exists in the silicon oxide film.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: November 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kaoru Hatano, Satoshi Seo
  • Publication number: 20130299953
    Abstract: A multilayer structure comprises: a substrate; and, a plurality of polymerizable layers successively deposited on the substrate, with each successive layer having a greater dielectric polarizability than the preceding layer(s), so that each successive layer will absorb microwave energy preferentially to the preceding layer(s). In this way, successive layers can be cured without over-curing the preceding layers. The individual layers are preferably materials from a single chemical family (e.g., epoxies, polyimides, PBO, etc.) and have similar properties after curing. The dielectric polarizabilities may be adjusted by modifying such factors as chain endcap dipole strength, cross-linker dipole strength, promoter, solvent, and backbone type. The invention is particularly suitable for producing various polymer layers on silicon for electronic applications. An associated method is also disclosed.
    Type: Application
    Filed: May 11, 2012
    Publication date: November 14, 2013
    Inventors: Robert L. Hubbard, Iftikhar Ahmad
  • Publication number: 20130302990
    Abstract: The invention provides an organic film composition comprises (A) a heat-decomposable polymer, (B) an organic solvent, and (C) an aromatic ring containing resin, with the weight reduction rate of (A) the heat-decomposable polymer from 30° C. to 250° C. being 40% or more by mass. There can be provided an organic film composition having not only a high dry etching resistance but also an excellent filling-up or flattening characteristics.
    Type: Application
    Filed: April 30, 2013
    Publication date: November 14, 2013
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Takeru WATANABE, Seiichiro TACHIBANA, Toshihiko FUJII, Kazumi NODA, Toshiharu YANO, Takeshi KINSHO
  • Patent number: 8574953
    Abstract: The present invention provides a process for preparing a melt-processed organic-inorganic hybrid material including the steps of maintaining a solid organic-inorganic hybrid material at a temperature above the melting point but below the decomposition temperature of the organic-inorganic hybrid material for a period of time sufficient to form a uniform melt and thereafter, cooling the uniform melt to an ambient temperature under conditions sufficient to produce the melt-processed organic-inorganic hybrid material.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Patrick W. DeHaven, David R. Medeiros, David B. Mitzi
  • Patent number: 8575040
    Abstract: Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: November 5, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Janos Fucsko, John A. Smythe, III, Li Li, Grady S. Waldo
  • Publication number: 20130280921
    Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes forming a film containing carbon on a substrate by repeating a cycle plural times. The cycle includes: in a state in which a substrate housed in a processing chamber is heated, supplying an organic-based gas into the processing chamber and confining the organic-based gas inside the processing chamber; maintaining a state in which the organic-based gas is confined inside the processing chamber; and exhausting an inside of the processing chamber.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 24, 2013
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Tsuyoshi TAKEDA, Taketoshi SATO, Minoru KOHASHI
  • Patent number: 8563443
    Abstract: A method of forming a dielectric film having at least Si—N, Si—C, or Si—B bonds on a semiconductor substrate by atomic layer deposition (ALD), includes: supplying a precursor in a pulse to adsorb the precursor on a surface of a substrate; supplying a reactant gas in a pulse over the surface without overlapping the supply of the precursor; reacting the precursor and the reactant gas on the surface; and repeating the above steps to form a dielectric film having at least Si—N, Si—C, or Si—B bonds on the substrate. The precursor has at least one Si—C or Si—N bond, at least one hydrocarbon, and at least two halogens attached to silicon in its molecule.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: October 22, 2013
    Assignee: ASM Japan K.K.
    Inventor: Atsuki Fukazawa
  • Patent number: 8530268
    Abstract: An organic light-emitting display device includes a pixel electrode and a pixel defining layer which are formed by using one mask process. A method for manufacturing the display includes thermally reflowing a remaining portion of a photo-sensitive organic film that is used as a mask to form the pixel electrode to be the pixel defining layer.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: September 10, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventor: Bong-Ju Kim
  • Patent number: 8530003
    Abstract: A polybenzoxazole precursor is represented by the following formula (1): wherein R1a to R4a, R1b to R4b, X1, Y1 and m are defined in the specification.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: September 10, 2013
    Assignee: FUJIFILM Corporation
    Inventors: Kenichiro Sato, Tsukasa Yamanaka
  • Patent number: 8530361
    Abstract: A method for depositing a silicon containing film on a substrate using an organoaminosilane is described herein. The organoaminosilanes are represented by the formulas: wherein R is selected from a C1-C10 linear, branched, or cyclic, saturated or unsaturated alkyl group with or without substituents; a C5-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, or a silyl group in formula C with or without substituents, R1 is selected from a C3-C10 linear, branched, cyclic, saturated or unsaturated alkyl group with or without substituents; a C6-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, a hydrogen atom, a silyl group with substituents and wherein R and R1 in formula A can be combined into a cyclic group and R2 representing a single bond, (CH2)n chain, a ring, C3-C10 branched alkyl, SiR2, or SiH2.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: September 10, 2013
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Manchao Xiao, Xinjian Lei, Heather Regina Bowen, Mark Leonard O'Neill
  • Patent number: 8524615
    Abstract: Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: September 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Hoon Ahn, Byung-Hee Kim, Sang-Don Nam, Kyu-Hee Han, Gil-heyun Choi, Jang-Hee Lee, Jong-Min Baek, Kyoung-Hee Kim
  • Publication number: 20130224957
    Abstract: A resist underlayer film forming composition for lithography includes: as a component (I), a fluorine-containing highly branched polymer obtained by polymerizing a monomer A having two or more radical polymerizable double bonds in the molecule thereof, a monomer B having a fluoroalkyl group and at least one radical polymerizable double bond in the molecule thereof, and a monomer D having a silicon atom-containing organic group and at least one radical polymerizable double bond in the molecule thereof, in the presence of a polymerization initiator C in a content of 5% by mole or more and 200% by mole or less, based on the total mole of the monomer A, the monomer B, and the monomer D; and as a component (II), a hydrolyzable silane compound, a hydrolysis product thereof, a hydrolysis-condensation product thereof, or a silicon-containing compound that is a combination of these compounds.
    Type: Application
    Filed: October 20, 2011
    Publication date: August 29, 2013
    Applicant: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Yuta Kanno, Makoto Nakajima, Tomoko Misaki, Motonobu Matsuyama, Masayuki Haraguchi
  • Patent number: 8518738
    Abstract: A method for forming a semiconductor body, the method comprising: forming a mixture of an organic semiconducting material and a binder material; causing the semiconducting material to at least partially solidify; and causing the binder material to crystallize in such a way as to cause the semiconducting material to at least partially segregate from the binder material.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: August 27, 2013
    Assignees: Cambridge Enterprise Limited, Technische Universiteit Eindhoven, Eidgenoessische Technische Hochschule Zurich
    Inventors: Henning Sirringhaus, Shalom Goffri, Rene A. J. Janssen, Christopher Paul Radano, Paul Smith, Christian Muller, Pascal Wolfer, Natalie Stingelin-Stutzmann
  • Patent number: 8518837
    Abstract: Nanopatterned surfaces are prepared by a method that includes forming a block copolymer film on a substrate, annealing and surface reconstructing the block copolymer film to create an array of cylindrical voids, depositing a metal on the surface-reconstructed block copolymer film, and heating the metal-coated block copolymer film to redistribute at least some of the metal into the cylindrical voids. When very thin metal layers and low heating temperatures are used, metal nanodots can be formed. When thicker metal layers and higher heating temperatures are used, the resulting metal structure includes nanoring-shaped voids. The nanopatterned surfaces can be transferred to the underlying substrates via etching, or used to prepare nanodot- or nanoring-decorated substrate surfaces.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: August 27, 2013
    Assignee: The University of Massachusetts
    Inventors: Thomas P. Russell, Soojin Park, Jia-Yu Wang, Bokyung Kim
  • Publication number: 20130217237
    Abstract: A Spin-On Dielectric (SOD) method with multi stage ramping temperature for coating a dielectric material onto a substrate, comprising the steps of: (a) placing the substrate on a chill plate to decrease the temperature; (b) fixing the chilled substrate on a spinning device; (c) rotating the spinning device to drive the substrate rotating; (d) injecting the dielectric material onto the center of the substrate; (e) spreading the dielectric material on the upper surface of the substrate by spinning; (f) baking the substrate and the dielectric material by a heat plate to achieve multi stages ramping temperature, where the temperature of each stage has a steady state temperature for a predetermined time and the posterior stage has higher temperature than the anterior stage; (g) placing the substrate on the chill plate for cooling down; (h) spreading a film of dielectric material and finishing the coating.
    Type: Application
    Filed: April 27, 2012
    Publication date: August 22, 2013
    Applicant: INOTERA MEMORIES, INC.
    Inventors: Kuen-Shin HUANG, Chiuan-Heng DU, Yao-Jen CHANG, Yau Ying TZENG, Ming-Tai CHIEN, Chun-Yu LEE
  • Patent number: 8513142
    Abstract: A method of manufacturing non-photosensitive polyimide passivation layer is disclosed. The method includes: spin-coating a non-photosensitive polyimide layer over a wafer and baking it; depositing a silicon dioxide thin film thereon; spin-coating a photoresist layer over the silicon dioxide thin film and baking it; exposing and developing the photoresist layer to form a photoresist pattern; etching the silicon dioxide thin film by using the photoresist pattern as a mask; removing the patterned photoresist layer; dry etching the non-photosensitive polyimide layer by using the patterned silicon dioxide thin film as a mask; removing the patterned silicon dioxide thin film; and curing to form a imidized polyimide passivation layer. The method addresses issues of the traditional non-photosensitive polyimide process, including aluminum corrosion by developer, tapered profile of non-photosensitive polyimide layer and generation of photoresist residues.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: August 20, 2013
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventor: Xiaobo Guo
  • Patent number: 8507665
    Abstract: A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si—H and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: August 13, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung Kyu Min, Ja Chun Ku, Sang Tae Ahn, Chai O Chung, Hyeon Ju An, Hyo Seok Lee, Eun Jeong Kim, Chan Bae Kim
  • Patent number: 8502334
    Abstract: Disclosed is an image sensor including a photo-sensing device, a color filter positioned on the photo-sensing device, a microlens positioned on the color filter, and an insulation layer positioned between the photo-sensing device and the color filter, and including a trench exposing the photo-sensing device and a filler filled in the trench. The filler has light transmittance of about 85% or more at a visible ray region, and a higher refractive index than the insulation layer. A method of manufacturing the image sensor is also provided.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: August 6, 2013
    Assignee: Cheil Industries Inc.
    Inventors: Kil-Sung Lee, Jae-Hyun Kim, Chang-Min Lee, Eui-June Jeong, Min-Soo Kim, Hwan-Sung Cheon, Tu-Won Chang
  • Publication number: 20130189533
    Abstract: There is provided a resist underlayer film forming composition for forming a resist underlayer film providing heat resistance properties and hardmask characteristics. A resist underlayer film forming composition for lithography, comprising: a polymer containing a unit structure of Formula (1): ?O—Ar1???Formula (1) (in Formula (1), Ar1 is a C6-50 arylene group or an organic group containing a heterocyclic group), a unit structure of Formula (2): ?O—Ar2—O—Ar3-T-Ar4???Formula (2) (in Formula (2), Ar2, Ar3, and Ar4 are individually a C6-50 arylene group or an organic group containing a heterocyclic group; and T is a carbonyl group or a sulfonyl group), or a combination of the unit structure of Formula (1) and the unit structure of Formula (2). The organic groups of Ar1 and Ar2 containing arylene group may be organic groups containing a fluorene structure.
    Type: Application
    Filed: October 7, 2011
    Publication date: July 25, 2013
    Applicant: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Hiroaki Okuyama, Yasunobu Someya, Masakazu Kato, Tetsuya Shinjo, Keisuke Hashimoto
  • Patent number: 8492293
    Abstract: Methods for selectively placing carbon nanotubes on a substrate surface by using functionalized carbon nanotubes having an organic compound that is covalently bonded to such carbon nanotubes. The organic compound comprises at least two functional groups, the first of which is capable of forming covalent bonds with carbon nanotubes, and the second of which is capable of selectively bonding metal oxides. Such functionalized carbon nanotubes are contacted with a substrate surface that has at least one portion containing a metal oxide. The second functional group of the organic compound selectively bonds to the metal oxide, so as to selectively place the functionalized carbon nanotubes on the at least one portion of the substrate surface that comprises the metal oxide.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Hongsik Park, George S. Tulevski
  • Patent number: 8492192
    Abstract: A composition for forming a semiconducting device includes an organic semiconducting material, an agent capable of inhibiting and/or preventing dewetting, and an additional substance, wherein the additional substance is provided in an amount capable of preventing initial crystallization of the composition and reducing the melting point or glass transition temperature of the composition below the melting point or glass transition temperature of the organic semiconducting material. The additional substance may be naphthalene, phenylnaphthalene, anthrance, or diphenylanthrance.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: July 23, 2013
    Assignee: Creator Technology B.V.
    Inventors: Sepas Setayesh, Dagobert M. De Leeuw, Natalie Stutzmann-Stingelin
  • Patent number: 8470720
    Abstract: A wall surface of a film forming container is heated to or above a vaporization temperature of a material monomer, which is used to form an organic film, by using an external heater formed along the wall surface of the film forming container, substrates are heated to a thermal polymerization reaction temperature by using an internal heater that is disposed apart from the external heater and near a substrate-supporting container in which the substrates are received, and the organic film is formed through thermal polymerization occurring on the substrates by supplying the material monomer into the film forming container.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: June 25, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Ken Nakao, Muneo Harada
  • Patent number: 8465991
    Abstract: A method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric and associated apparatus enables process induced damage repair. The methods of the invention are particularly applicable in the context of damascene processing to recover lost low-k property of a dielectric damaged during processing, either pre-metallization, post-planarization, or both. UV treatments can include an exposure of the subject low-k dielectric to a constrained UV spectral profile and/or chemical silylating agent, or both.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: June 18, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Bhadri N. Varadarajan, Kevin M. McLaughlin, Bart van Schravendijk
  • Patent number: 8455373
    Abstract: The present invention provides ink-jet printing ink for organic semiconductors, and, more particularly, provides ink-jet printing ink for organic semiconductors, which can be used to form a uniform crystalline thin film. The ink-jet printing ink of the present invention includes a mixed solvent composed of a first solvent and a second solvent having a higher boiling point and lower surface tension than the first solvent, thus forming a uniform crystalline thin film in a volatilization process. Further, the present invention provides a circular organic thin film transistor having a high field-effect mobility of about 0.12 cm2V1S?1.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: June 4, 2013
    Assignee: Postech Academy-Industry Foundation
    Inventors: Kil Won Cho, Hwa Sung Lee, Ji Hwang Lee, Wi Hyoung Lee, Jung Ah Lim, Yeong Don Park
  • Patent number: 8455366
    Abstract: An organic planarizing layer (OPL) is formed atop a semiconductor substrate which includes a plurality of gate lines thereon. Each gate line includes at least a high k gate dielectric and a metal gate. A patterned photoresist having at least one pattern formed therein is then positioned atop the OPL. The at least one pattern in the photoresist is perpendicular to each of the gate lines. The pattern is then transferred by etching into the OPL and portions of each of the underlying gate lines to provide a plurality of gate stacks each including at least a high k gate dielectric portion and a metal gate portion. The patterned photoresist and the remaining OPL layer are then removed utilizing a sequence of steps including first contacting with a first acid, second contacting with an aqueous cerium-containing solution, and third contacting with a second acid.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Nicholas C. M. Fuller, Pratik P. Joshi, Mahmoud Khojasteh, Rajiv M. Ranade, George G. Totir
  • Patent number: 8431464
    Abstract: A silicic coating of 2.4 g/cm3 or higher density, obtained by forming a silicic coating precursor with the use of at least one type of silane compound having a photosensitive functional group and thereafter irradiating the silicic coating precursor with at least one type of light. This silicic coating can be used as a novel barrier film or stopper film for semiconductor device.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: April 30, 2013
    Assignee: Fujitsu Limited
    Inventors: Yasushi Kobayashi, Kouta Yoshikawa, Yoshihiro Nakata, Tadahiro Imada, Shirou Ozaki
  • Publication number: 20130101825
    Abstract: The present invention provides a method for preparing a nanoporous ultra-low dielectric thin film including a high-temperature ozone treatment and nanoporous ultra-low dielectric thin film prepared by the same method. The method includes preparing a mixture of an organic silicate matrix-containing solution and a reactive porogen-containing solution; coating the mixture on a substrate to form a thin film; and heating the thin film with an ozone treatment. The prepared nanoporous ultra-low dielectric thin film could have a dielectric constant of about 2.3 or less and a mechanical strength of about 10 GPa or more by improving a pore size and a distribution of pores in the thin film by performing an ozone treatment with high temperature and optimization of the ozone treatment temperature.
    Type: Application
    Filed: August 9, 2012
    Publication date: April 25, 2013
    Applicant: Industry-University Cooperation Foundation Sogang University
    Inventors: Hee Woo RHEE, Bo Ra SHIN, Kyu Yoon CHOI, Bum Suk KIM
  • Patent number: 8394727
    Abstract: Methods for selectively placing carbon nanotubes on a substrate surface by using functionalized carbon nanotubes having an organic compound that is covalently bonded to such carbon nanotubes. The organic compound comprises at least two functional groups, the first of which is capable of forming covalent bonds with carbon nanotubes, and the second of which is capable of selectively bonding metal oxides. Such functionalized carbon nanotubes are contacted with a substrate surface that has at least one portion containing a metal oxide. The second functional group of the organic compound selectively bonds to the metal oxide, so as to selectively place the functionalized carbon nanotubes on the at least one portion of the substrate surface that comprises the metal oxide.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: March 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Hongsik Park, George S. Tulevski
  • Patent number: 8394728
    Abstract: A film deposition method includes the steps of: coating a solution containing a polysilane compound on a substrate to form a coating film and then carrying out a first thermal treatment in an inert atmosphere, thereby forming the coating film into a silicon film; forming a coating film containing a polysilane compound on the silicon film and then carrying out a second thermal treatment in an inert atmosphere or a reducing atmosphere, thereby forming the coating film into a silicon oxide precursor film; and carrying out a third thermal treatment in an oxidizing atmosphere, thereby forming the silicon oxide precursor film into a silicon oxide film and simultaneously densifying the silicon film.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: March 12, 2013
    Assignee: Sony Corporation
    Inventors: Hirotaka Akao, Yuriko Kaino, Takahiro Kamei, Masaki Hara, Kenichi Kurihara
  • Patent number: 8382997
    Abstract: A method of patterning a substrate is described. The method includes preparing a film stack on a substrate, wherein the film stack comprises a spin-on layer, and heating the spin-on layer to a cure temperature less than a thermal decomposition temperature of the spin-on layer and exceeding about 200 degrees C. to increase mechanical strength of the spin-on layer. The method further includes forming a feature pattern without pattern collapse in the spin-on layer, wherein the feature pattern is characterized by a critical dimension less than 35 nm (nanometers) and an aspect ratio relating a height of the feature pattern to the critical dimension exceeding 5:1.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: February 26, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Andrew W. Metz
  • Publication number: 20130045608
    Abstract: In one embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, includes operations comprising: providing a structure comprising a first layer overlying a substrate, where the first layer comprises a dielectric material having a plurality of pores; applying a filling material to a surface of the first layer, where the filling material comprises a polymer and at least one additive, where the at least one additive comprises at least one of a surfactant, a high molecular weight polymer and a solvent (e.g., a high boiling point solvent); and after applying the filling material, heating the structure to enable the filling material to at least partially fill the plurality of pores uniformly across an area of the first layer, where heating the structure results in residual filling material being uniformly left on the surface of the first layer.
    Type: Application
    Filed: October 19, 2012
    Publication date: February 21, 2013
    Applicant: International Business Machines Corporation
    Inventor: International Business Machines Corporation
  • Patent number: 8377818
    Abstract: The present invention is an aftertreatment method further applied to an amorphous carbon film to which a treatment including heating is performed after the film has been formed on a substrate. The treatment of preventing oxidation of the amorphous carbon film is performed immediately after the treatment including heating.
    Type: Grant
    Filed: July 4, 2007
    Date of Patent: February 19, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Hiraku Ishikawa
  • Patent number: 8378489
    Abstract: A semiconductor device of this invention has a copper wiring layer, of which a layer, to which a composition including at least one substance selected from the group consisting of ammonia and organic bases is applied, and a silicon-containing insulating film are sequentially superimposed on the copper wiring layer. Accordingly, semiconductor devices having insulating layers which adheres well to the copper serving as the wiring material can be obtained.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: February 19, 2013
    Assignee: Fujitsu Limited
    Inventors: Shiro Ozaki, Yoshihiro Nakata, Yasushi Kobayashi, Ei Yano
  • Patent number: 8365385
    Abstract: There is provided a work processing apparatus including a plurality of work conveyance lines on which works are to be moved, a stopping unit to stop a work in a predetermined processing position on each of the work conveyance lines, a processing unit to make a desired process on the work stopped by the stopping unit, and a moving unit to move the processing unit between the work conveyance lines. Works are sequentially processed on the plurality of work conveyance lines. While a work is being processed in the processing position on one of the work conveyance lines, another work can be carried in to the other work conveyance line. Therefore, immediately after a work is completely processed on the one work conveyance line, processing of another work can be started. As a result, the production rate is higher and the apparatus can be designed smaller in size.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: February 5, 2013
    Assignee: Musashi Engineering, Inc.
    Inventor: Kazumasa Ikushima
  • Patent number: 8367556
    Abstract: An organic planarizing layer (OPL) is formed atop a semiconductor substrate which includes a plurality of gate lines thereon. Each gate line includes at least a high k gate dielectric and a metal gate. A patterned photoresist having at least one pattern formed therein is then positioned atop the OPL. The at least one pattern in the photoresist is perpendicular to each of the gate lines. The pattern is then transferred by etching into the OPL and portions of each of the underlying gate lines to provide a plurality of gate stacks each including at least a high k gate dielectric portion and a metal gate portion. The patterned photoresist and the remaining OPL layer are then removed utilizing a sequence of steps including first contacting with a first acid, second contacting with an aqueous cerium-containing solution, and third contacting with a second acid.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Nicholas C. M. Fuller, Pratik P. Joshi, Mahmoud Khojasteh, Rajiv M. Ranade, George G. Totir
  • Patent number: 8361909
    Abstract: A conductive paste including conductive particles each of which has a size of greater than or equal to 0.1 ?m and less than or equal to 10 ?m, a resin, and a solvent is placed over a first conductor and the solvent is vaporized. In this manner, a second conductor having the conductive particles and a memory layer including the resin between the first conductor and the conductive particles is formed.
    Type: Grant
    Filed: November 26, 2011
    Date of Patent: January 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takaaki Nagata
  • Patent number: 8354350
    Abstract: A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si—H and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: January 15, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung Kyu Min, Ja Chun Ku, Sang Tae Ahn, Chai O Chung, Hyeon Ju An, Hyo Seok Lee, Eun Jeong Kim, Chan Bae Kim
  • Patent number: 8354339
    Abstract: Methods of fabricating a self-aligned permanent on-chip interconnect structure are provided. In one embodiment, the method includes forming a patterned photoresist having at least one opening on a surface of a substrate. A dielectric sidewall structure is then formed on each sidewall of the patterned photoresist and within the at least one opening. A narrowed width opening is present between neighboring dielectric sidewall structures. The patterned photoresist is then removed and thereafter each dielectric sidewall structure is converted into a permanent patterned dielectric structure which is self-aligned and double patterned. At least an electrically conductive material is formed within the narrowed width openings.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: January 15, 2013
    Assignee: International Business Machines Corporation
    Inventor: Qinghuang Lin
  • Patent number: 8350246
    Abstract: A structure of a porous low-k layer is described, comprising a bottom portion and a body portion of the same atomic composition, wherein the body portion is located on the bottom portion, and the bottom portion has a density higher than the density of the body portion. An interconnect structure is also described, including the above porous low-k layer, and a conductive layer filling up a damascene opening in the porous low-k layer.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: January 8, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Mei-Ling Chen, Kuo-Chih Lai, Su-Jen Sung, Chien-Chung Huang, Yu-Tsung Lai
  • Patent number: 8349629
    Abstract: A semiconductor light-emitting element includes a first semiconductor layer having a first conduction type, a second semiconductor layer having a second conduction type, an active layer provided between the first and second semiconductor layers, a polarity inversion layer provided on the second semiconductor layer, and a third semiconductor layer having the second conduction type provided on the polarity inversion layer. Crystal orientations of the first through third semiconductor layers are inverted, with the polarity inversion layer serving as a boundary. The first and third semiconductor layers have uppermost surfaces made from polar faces having common constitutional elements. Hexagonal conical protrusions arising from a crystal structure are formed at outermost surfaces of the first and third semiconductor layers. The first through third semiconductor layers are made from a wurtzite-structure group III nitride semiconductor, and are layered along a C-axis direction of the crystal structure.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: January 8, 2013
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Yusuke Yokobayashi, Satoshi Tanaka, Masahiko Moteki
  • Publication number: 20120329286
    Abstract: A semiconductor device manufacturing method includes: accommodating a substrate in a processing chamber; and supplying a silicon-based gas and an amine-based gas into the processing chamber that is heated to form a film including silicon and carbon on the substrate. The forming of the film including silicon and carbon includes: supplying the silicon-based gas and the amine-based gas into the processing chamber and confining the silicon-based gas and the amine-based gas in the processing chamber; maintaining a state in which the silicon-based gas and the amine-based gas are confined in the processing chamber, and exhausting an inside of the processing chamber.
    Type: Application
    Filed: June 21, 2012
    Publication date: December 27, 2012
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Tsuyoshi TAKEDA, Taketoshi SATO
  • Publication number: 20120329287
    Abstract: A porous SiCOH dielectric film in which the stress change caused by increased tetrahedral strain is minimized by post treatment in unsaturated Hydrocarbon ambient. The p-SiCOH dielectric film has more —(CHx) and less Si—O—H and Si—H bonding moieties. Moreover, a stable pSiOCH dielectric film is provided in which the amount of Si—OH (silanol) and Si—H groups at least within the pores has been reduced by about 90% or less by the post treatment. A p-SiCOH dielectric film is produced that is flexible since the pores include stabilized crosslinking —(CHx)— chains wherein x is 1, 2 or 3 therein. The dielectric film is produced utilizing an annealing step subsequent deposition that includes a gaseous ambient that includes at least one C—C double bond and/or at least one C—C triple bond.
    Type: Application
    Filed: September 4, 2012
    Publication date: December 27, 2012
    Applicant: International Business Machines Corporation
    Inventors: Stephen M. Gates, Alfred Grill, Son Nguyen, Satyanarayana V. Nitta, Thomas M. Shaw
  • Publication number: 20120301674
    Abstract: The present disclosure includes a method for organizing a block copolymer (BCP) comprising contacting a substrate with the block copolymer, and exposing the BCP-coated substrate to a suitable energy source under conditions sufficient to induce substrate heating and organize the block copolymer.
    Type: Application
    Filed: February 7, 2011
    Publication date: November 29, 2012
    Inventors: Jillian Buriak, Xiaojiang Zhang, Kenneth Harris
  • Publication number: 20120282784
    Abstract: In one exemplary embodiment, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to an exposed surface of the first layer; heating the structure to a first temperature to enable the filling material to homogeneously fill the plurality of pores; after filling the plurality of pores, performing at least one process on the structure; and after performing the at least one process, removing the filling material from the plurality of pores by heating the structure to a second temperature to decompose the filling material.
    Type: Application
    Filed: July 19, 2012
    Publication date: November 8, 2012
    Applicant: International Business Machines Corporation
    Inventors: Sampath Purushothaman, Geraud Jean-Michel Dubois, Teddie P. Magbitang, Willi Volksen, Theo J. Frot