Insulative Material Having Impurity (e.g., For Altering Physical Characteristics, Etc.) Patents (Class 438/783)
  • Patent number: 11935750
    Abstract: A method for producing a semiconductor device includes forming, on a substrate, a film to be processed. The method further includes forming, on the film to be processed, a first film containing a metallic element and a second film containing at least one of carbon or boron. The method further includes forming an insulating film on the first and second films. The method further includes processing the film to be processed using the first film, the second film, and the insulating film, as a mask.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: March 19, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Kei Watanabe, Toshiyuki Sasaki, Soichi Yamazaki, Shunsuke Ochiai, Yuya Matsubara
  • Patent number: 11929296
    Abstract: A method of forming a semiconductor device, the method including the steps of providing a metal component having a top surface, and providing a passivation layer over the metal component such that an outer layer of the passivation layer is substantially planar and does not extend below the top surface of the metal component.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: March 12, 2024
    Assignee: X-FAB SARAWAK SDN. BHD.
    Inventors: Raj Sekar Sethu, Peng Yang, Kumar Sambhawam
  • Patent number: 11823893
    Abstract: Methods of forming SiCON films comprising sequential exposure to a silicon precursor and a mixture of alkanolamine and amine reactants and an optional plasma are described. Methods of forming a silicon-containing film comprising sequential exposure to a silicon precursor and an epoxide with an optional plasma exposure are also described.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: November 21, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Mark Saly, David Thompson, Thomas Knisley, Bhaskar Jyoti Bhuyan
  • Patent number: 11649560
    Abstract: Embodiments generally relate to methods for depositing silicon-phosphorous materials, and more specifically, relate to using silicon-phosphorous compounds in vapor deposition processes (e.g., epitaxy, CVD, or ALD) to deposit silicon-phosphorous materials. In one or more embodiments, a method for forming a silicon-phosphorous material on a substrate is provided and includes exposing the substrate to a deposition gas containing one or more silicon-phosphorous compounds during a deposition process and depositing a film containing the silicon-phosphorous material on the substrate. The silicon-phosphorous compound has the chemical formula [(R3-vHvSi)—(R2-wHwSi)n]xPHyR?z, where each instance of R and each instance of R? are independently an alkyl or a halogen, n is 0, 1, or 2; v is 0, 1, 2, or 3; w is 0, 1, or 2; x is 1, 2, or 3; y is 0, 1, or 2; z is 0, 1, or 2, and where x+y+z=3.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: May 16, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Errol Antonio C Sanchez, Mark J. Saly, Schubert Chu, Abhishek Dube, Srividya Natarajan
  • Patent number: 11646216
    Abstract: Semiconductor processing systems and method are described that may include flowing deposition precursors into a substrate processing region of a semiconductor processing chamber, where the substrate processing region includes an electrostatic chuck. The methods may further include depositing a seasoning layer on the electrostatic chuck from the deposition precursors to form a seasoned electrostatic chuck. The seasoning layer may be characterized by a dielectric constant greater than or about 3.5. The methods may still further include applying a voltage to the seasoned electrostatic chuck of greater than or about 500 V. The seasoned electrostatic chuck may be characterized by a leakage current of less than or about 25 mA when the voltage is applied.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: May 9, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Akhil Singhal, Allison Yau, Zeqiong Zhao, Sang-Jin Kim, Zhijun Jiang, Deenesh Padhi, Ganesh Balasubramanian
  • Patent number: 11631571
    Abstract: An apparatus for atomic scale processing is provided. The apparatus may include a reactor (100) and an inductively coupled plasma source (10). The reactor may have inner (154) and outer surfaces (152) such that a portion of the inner surfaces define an internal volume (156) of the reactor. The internal volume of the reactor may contain a fixture assembly (158) to support a substrate (118) wherein the partial pressure of each background impurity within the internal volume may be below 10?6 Torr to reduce the role of said impurities in surface reactions during atomic scale processing.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: April 18, 2023
    Assignee: Kurt J. Lesker Company
    Inventors: Gilbert Bruce Rayner, Jr., Noel Christopher O'Toole, Daniel Edward Carlsen
  • Patent number: 11499222
    Abstract: A method of depositing a metal-containing material is disclosed. The method can include use of cyclic deposition techniques, such as cyclic chemical vapor deposition and atomic layer deposition. The metal-containing material can include intermetallic compounds. A structure including the metal-containing material and a system for forming the material are also disclosed.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: November 15, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: Katja Väyrynen, Timo Hatanpää, Mikko Ritala, Markku Leskelä
  • Patent number: 11492703
    Abstract: A method of depositing a metal-containing material is disclosed. The method can include use of cyclic deposition techniques, such as cyclic chemical vapor deposition and atomic layer deposition. The metal-containing material can include intermetallic compounds. A structure including the metal-containing material and a system tor forming the material are also disclosed.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: November 8, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: Katja Väyrynen, Timo Hatanpää, Anton Vihervaara, Mikko Ritala, Markku Leskelä
  • Patent number: 11342216
    Abstract: There is provided a method of filling one or more recesses by providing the substrate in a reaction chamber; introducing a first reactant, to form first active species, for a first pulse time to the substrate; introducing a second reactant for a second pulse time to the substrate; and introducing a third reactant, to form second active species, for a third pulse time to the substrate. An apparatus for filling a recess is also disclosed and a structure formed using the method and/or apparatus is disclosed.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: May 24, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: Zecheng Liu, Viljami Pore
  • Patent number: 11282708
    Abstract: Performed is a hydrogen anneal of heating a semiconductor wafer on which a thin film containing a dopant and carbon is formed to an anneal temperature in an atmosphere containing hydrogen. Subsequently, a hydrogen atmosphere in a chamber is replaced with an oxygen atmosphere, and the semiconductor wafer is preheated to a preheating temperature in the oxygen atmosphere. Performed then is a flash heating treatment of heating a surface of the semiconductor wafer to a peak temperature for less than one second. The semiconductor wafer is heated in the oxygen atmosphere, thus activation of dopant and binding of carbon in the thin film and oxygen in the atmosphere are promoted, and carbon is exhausted from the thin film to prevent hardening of the thin film. As a result, the thin film containing carbon can be easily peeled from the semiconductor wafer.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: March 22, 2022
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Akitsugu Ueda, Kazuhiko Fuse
  • Patent number: 11276570
    Abstract: Exemplary processing methods may include forming a first deposition plasma of a silicon-and-nitrogen-containing precursor. The methods may include depositing a first portion of a silicon nitride material on a semiconductor substrate with the first deposition plasma. A first treatment plasma of a helium-and-nitrogen-containing precursor may be formed to treat the first portion of the silicon nitride material with the first treatment plasma. A second deposition plasma may deposit a second portion of a silicon nitride material, and a second treatment plasma may treat the second portion of the silicon nitride material. A flow rate ratio of helium-to-nitrogen in the first treatment plasma may be lower than a He/N2 flow rate ratio in the second treatment plasma. A first power level from a plasma power source that forms the first treatment plasma may be lower than a second power level that forms the second treatment plasma.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: March 15, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Vinayak Veer Vats, Byung Kook Ahn, SeoYoung Lee, Hang Yu
  • Patent number: 11211527
    Abstract: Light emitting diode (LED) devices comprise: a patterned substrate comprising a substrate body, a plurality of integral features protruding from the substrate body, and a base surface defined by spaces between the plurality of integral features; a selective layer comprising a dielectric material located on the surfaces of the integral features, wherein there is an absence of the selective layer on the base surface; and a III-nitride layer comprising a III-nitride material on the selective layer and the base surface.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: December 28, 2021
    Assignee: Lumileds LLC
    Inventors: Isaac Wildeson, Toni Lopez, Robert Armitage, Parijat Deb
  • Patent number: 11158450
    Abstract: A magnetic core comprises an anisotropic, composite material, which itself includes a matrix material (e.g., a dielectric, non-magnetic material, preferably a paramagnetic material), and magnetically aligned, ferromagnetic particles. The latter may for instance include micrometer- and/or nanometer-length scale particles. Such particles form chains of particles within the matrix material, wherein the chains form percolation paths of magnetic conduction. The paths extend along a first direction, whereby the chains extend, each, substantially along this first direction, while being distinct and distant from each other along a second direction that is perpendicular to the first direction and, possibly, to a third direction that is perpendicular to both the first direction and the second direction. Necking bridges are preferably formed between the particles. Related devices (e.g., inductor, amplifiers, transformers, etc.) and fabrication methods are also disclosed.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: October 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Arvind Raj Mahankali Sridhar, Thomas Brunschwiler, Suiying Ye, Luca Del Carro, Jens Oliver Ammann
  • Patent number: 11114548
    Abstract: The present disclosure relates to the field of semiconductor technologies, and discloses semiconductor devices and manufacturing methods for the same. A semiconductor device may include: a substrate; a first active region on the substrate; a first gate structure positioned on the first active region; and a first source and a first drain that are positioned in the first active region and respectively on two sides of the first gate structure, where a size of the first drain is larger than a size of the first source. In forms of the present disclosure, because the size of the first drain is larger than the size of the first source, a current from the first drain to the first source is greater than a current from the first source to the first drain, so that the semiconductor device can make a read current relatively low and a write current relatively high in a static random access memory (SRAM), thereby improving a read margin and a write margin.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: September 7, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Zhenghao Gan, Junhong Feng
  • Patent number: 10914998
    Abstract: Disclosed are an array substrate of a thin-film transistor liquid crystal display device and a method for manufacturing the same. The array substrate includes a plurality of data lines, a plurality of dummy data lines, a plurality of first gate lines, a plurality of second gate lines, and a plurality of groups of pixel units. Each group of pixel units includes an odd-numbered column of first thin film transistors and an even-numbered column of second thin film transistors. First ends and second ends of the dummy data lines are connected respectively to two common voltage electrode lines, which are arranged on the substrate in a transverse direction. The method includes steps of: forming a plurality of gate lines and two common voltage electrode lines; forming a source, a drain, and a plurality of data lines; and forming a plurality of pixel electrodes and a plurality of dummy data lines. A light shielding electrode line provided has good voltage driving uniformity.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: February 9, 2021
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiangyang Xu
  • Patent number: 10818489
    Abstract: A process for depositing a silicon carbon nitride film on a substrate can include a plurality of complete deposition cycles, each complete deposition cycle having a SiN sub-cycle and a SiCN sub-cycle. The SiN sub-cycle can include alternately and sequentially contacting the substrate with a silicon precursor and a SiN sub-cycle nitrogen precursor. The SiCN sub-cycle can include alternately and sequentially contacting the substrate with carbon-containing precursor and a SiCN sub-cycle nitrogen precursor. The SiN sub-cycle and the SiCN sub-cycle can include atomic layer deposition (ALD). The process for depositing the silicon carbon nitride film can include a plasma treatment. The plasma treatment can follow a completed plurality of complete deposition cycles.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: October 27, 2020
    Assignee: ASM IP Holding B.V.
    Inventor: Viljami Pore
  • Patent number: 10804094
    Abstract: Methods of forming SiCON films comprising sequential exposure to a silicon precursor and a mixture of alkanolamine and amine reactants and an optional plasma are described. Methods of forming a silicon-containing film comprising sequential exposure to a silicon precursor and an epoxide with an optional plasma exposure are also described.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: October 13, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Mark Saly, David Thompson, Thomas Knisley, Bhaskar Jyoti Bhuyan
  • Patent number: 10613407
    Abstract: The present invention is directed to an electrophoretic display device comprising (a) microcells filled with an electrophoretic fluid, and (b) at least one dielectric layer which comprises at least two types of filler. Among the types of filler, at least one type is sensitive to a magnetic field.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: April 7, 2020
    Assignee: E INK CALIFORNIA, LLC
    Inventors: Craig Lin, Yu Li, Peter B. Laxton, Lei Liu, Hui Du, HongMei Zang
  • Patent number: 10600882
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, and an interlayer dielectric disposed on the substrate which has agate structure therein. The gate structure further includes a gate electrode with a protruding portion, and a gate dielectric layer disposed between the gate electrode and the substrate. A spacer is disposed between the interlayer dielectric and the gate electrode. An insulating cap layer is disposed atop the gate electrode and encompasses the top and the sidewall of the protruding portion.
    Type: Grant
    Filed: October 11, 2015
    Date of Patent: March 24, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Yi-Wei Chen, Chun-Hsien Lin
  • Patent number: 10199211
    Abstract: A process for depositing a silicon carbon nitride film on a substrate can include a plurality of complete deposition cycles, each complete deposition cycle having a SiN sub-cycle and a SiCN sub-cycle. The SiN sub-cycle can include alternately and sequentially contacting the substrate with a silicon precursor and a SiN sub-cycle nitrogen precursor. The SiCN sub-cycle can include alternately and sequentially contacting the substrate with carbon-containing precursor and a SiCN sub-cycle nitrogen precursor. The SiN sub-cycle and the SiCN sub-cycle can include atomic layer deposition (ALD). The process for depositing the silicon carbon nitride film can include a plasma treatment. The plasma treatment can follow a completed plurality of complete deposition cycles.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 5, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventor: Viljami Pore
  • Patent number: 10023958
    Abstract: Provided are methods for the deposition of films comprising SiCN. Certain methods involve exposing a substrate surface to a silicon precursor, wherein the silicon precursor is halogenated with Cl, Br or I, and the silicon precursor comprises a halogenated silane, a halogenated carbosilane, an halogenated aminosilane or a halogenated carbo-sillyl amine. Then, the substrate surface can be exposed to a nitrogen-containing plasma or a nitrogen precursor and densification plasma.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: July 17, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Victor Nguyen, Ning Li, Mihaela Balseanu, Li-Qun Xia, Mark Saly, David Thompson
  • Patent number: 10008428
    Abstract: Methods and apparatus to form films on sensitive substrates while preventing damage to the sensitive substrate are provided herein. In certain embodiments, methods involve forming a bilayer film on a sensitive substrate that both protects the underlying substrate from damage and possesses desired electrical properties. Also provided are methods and apparatus for evaluating and optimizing the films, including methods to evaluate the amount of substrate damage resulting from a particular deposition process and methods to determine the minimum thickness of a protective layer. The methods and apparatus described herein may be used to deposit films on a variety of sensitive materials such as silicon, cobalt, germanium-antimony-tellerium, silicon-germanium, silicon nitride, silicon carbide, tungsten, titanium, tantalum, chromium, nickel, palladium, ruthenium, or silicon oxide.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: June 26, 2018
    Assignee: Novellus Systems, Inc.
    Inventors: Hu Kang, Shankar Swaminathan, Adrien LaVoie, Jon Henri
  • Patent number: 9887082
    Abstract: There is provided a method of filling one or more gaps by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant on a first area; introducing a second reactant to the substrate with a second dose, thereby forming no more than about one monolayer by the second reactant on a second area of the surface, wherein the first and the second areas overlap in an overlap area where the first and second reactants react and leave an initially unreacted area where the first and the second areas do not overlap; and, introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant remaining on the initially unreacted area.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: February 6, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Viljami Pore, Werner Knaepen, Bert Jongbloed, Dieter Pierreux, Gido Van Der Star, Toshiya Suzuki
  • Patent number: 9837263
    Abstract: A process for depositing a silicon carbon nitride film on a substrate can include a plurality of complete deposition cycles, each complete deposition cycle having a SiN sub-cycle and a SiCN sub-cycle. The SiN sub-cycle can include alternately and sequentially contacting the substrate with a silicon precursor and a SiN sub-cycle nitrogen precursor. The SiCN sub-cycle can include alternately and sequentially contacting the substrate with carbon-containing precursor and a SiCN sub-cycle nitrogen precursor. The SiN sub-cycle and the SiCN sub-cycle can include atomic layer deposition (ALD). The process for depositing the silicon carbon nitride film can include a plasma treatment. The plasma treatment can follow a completed plurality of complete deposition cycles.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: December 5, 2017
    Assignee: ASM IP HOLDING B.V.
    Inventor: Viljami Pore
  • Patent number: 9613819
    Abstract: Process chambers and methods of preparing and operating a process chamber are disclosed. In some embodiments, a method of preparing a process chamber for processing a substrate includes: forming a first barrier layer over an element disposed within a cavity of the process chamber, the element comprising an outgassing material; and forming, within the process chamber, a second barrier layer over the first barrier layer.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Ming-Ching Chang, Yuan-Sheng Huang, Jui-Ming Chen, Chao-Cheng Chen
  • Patent number: 9362107
    Abstract: Methods are described for forming a flowable low-k dielectric film on a patterned substrate. The film may be a silicon-carbon-oxygen (Si—C—O) layer in which the silicon and carbon constituents come from a silicon and carbon containing precursor while the oxygen may come from an oxygen-containing precursor activated in a remote plasma region. Shortly after deposition, the silicon-carbon-oxygen layer is treated by exposure to a hydrogen-and-nitrogen-containing precursor such as ammonia prior to curing. The treatment may remove residual moisture from the silicon-carbon-oxygen layer and may make the lattice more resilient during curing and subsequent processing. The treatment may reduce shrinkage of the silicon-carbon-oxygen layer during subsequent processing.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: June 7, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Kiran V. Thadani, Abhijit Basu Mallick, Sanjay Kamath
  • Patent number: 9053927
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes: forming a thin film containing a predetermined element on a substrate by repeating a cycle, the cycle including: forming a first layer containing the predetermined element, nitrogen and carbon by alternately performing supplying a source gas containing the predetermined element and a halogen element to the substrate and supplying a first reactive gas containing three elements including the carbon, the nitrogen and hydrogen and having a composition wherein a number of carbon atoms is greater than that of nitrogen atoms to the substrate a predetermined number of times; forming a second layer by supplying a second reactive gas different from the source gas and the first reactive gas to the substrate to modify the first layer; and modifying a surface of the second layer by supplying a hydrogen-containing gas to the substrate.
    Type: Grant
    Filed: December 8, 2012
    Date of Patent: June 9, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yoshiro Hirose, Atsushi Sano
  • Patent number: 9054046
    Abstract: A thin film including characteristics of low permittivity, high etching resistance and high leak resistance is to be formed. A method of manufacturing a semiconductor device includes forming a thin film containing a predetermined element on a substrate by performing a cycle a predetermined number of times, the cycle including: forming a first layer containing the predetermined element, nitrogen and carbon by alternately performing supplying a source gas containing the predetermined element and a halogen element to the substrate and supplying a first reactive gas containing three elements including the carbon, the nitrogen and hydrogen and having a composition wherein a number of carbon atoms is greater than that of nitrogen atoms to the substrate a predetermined number of times; and forming a second layer by supplying a second reactive gas different from the source gas and the first reactive gas to the substrate to modify the first layer.
    Type: Grant
    Filed: December 8, 2012
    Date of Patent: June 9, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yoshiro Hirose, Atsushi Sano, Yugo Orihashi, Yoshitomo Hashimoto, Satoshi Shimamoto
  • Publication number: 20150140836
    Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. Methods are disclosed that discuss the use of blocking species that bind to the surface of the dielectric and retard the etching of the dielectric surface by a doping/passivating species. The surface of the dielectric may be exposed to the blocking species a plurality of times during the process to ensure that the surface is well protected.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Applicant: Intermolecular, Inc.
    Inventor: Sandip Niyogi
  • Patent number: 9029272
    Abstract: A method for forming a gap-fill SiOCH film on a patterned substrate includes: (i) providing a substrate having recessed features on its surface; (ii) filling the recessed features of the substrate with a SiOCH film which is flowable and non-porous; (iii) after completion of step (ii), exposing the SiOCH film to a plasma including a hydrogen plasma; and (iv) curing the plasma-exposed SiOCH film with UV light.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: May 12, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Akinori Nakano, Shintaro Ueda, Dai Ishikawa, Kiyohiro Matsushita
  • Publication number: 20150118864
    Abstract: A method for forming a gap-fill SiOCH film on a patterned substrate includes: (i) providing a substrate having recessed features on its surface; (ii) filling the recessed features of the substrate with a SiOCH film which is flowable and non-porous; (iii) after completion of step (ii), exposing the SiOCH film to a plasma including a hydrogen plasma; and (iv) curing the plasma-exposed SiOCH film with UV light.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: ASM IP Holding B.V.
    Inventors: Akinori Nakano, Shintaro Ueda, Dai Ishikawa, Kiyohiro Matsushita
  • Patent number: 9018093
    Abstract: A method for forming a layer constituted by repeated stacked layers includes: forming a first layer and a second layer on a substrate under different deposition conditions to form a stacked layer, wherein the film stresses of the first and second layers are tensile or compressive and opposite to each other, and the wet etch rates of the first and second layers are at least 50 times different from each other; and repeating the above step to form a layer constituted by repeated stacked layers, wherein the deposition conditions for forming at least one stacked layer are different from those for forming another stacked layer.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: April 28, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Naoto Tsuji, Fumitaka Shoji
  • Patent number: 9006114
    Abstract: By integrating a spacer removal process into the sequence for patterning a first stress-inducing material during a dual stress liner approach, the sidewall spacer structure for one type of transistor may be maintained, without requiring additional lithography steps.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: April 14, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Volker Grimm, Heike Salz, Heike Berthold
  • Patent number: 8975143
    Abstract: Fluorine is located in selective portions of a gate oxide to adjust characteristics of the gate oxide. In some embodiments, the fluorine promotes oxidation which increases the thickness of the selective portion of the gate oxide. In some embodiments, the fluorine lowers the dielectric constant of the oxide at the selective portion. In some examples, having fluorine at selective portions of a select gate oxide of a non volatile memory may reduce program disturb of the memory.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: March 10, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Byoung W. Min
  • Patent number: 8969110
    Abstract: A method of manufacturing an organic light-emitting display apparatus includes: providing an organic light emission part on a substrate; providing a first inorganic layer including a first low temperature viscosity transition (“LVT”) inorganic material on the substrate to cover the organic light emission part; and adding fluoride into the first inorganic layer using a fluorine group material such that the first inorganic layer is converted into a second inorganic layer comprising a second low temperature viscosity transition inorganic material.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jai-Hyuk Choi
  • Patent number: 8962433
    Abstract: A MOS transistor process includes the following steps. A gate structure is formed on a substrate. A source/drain is formed in the substrate beside the gate structure. After the source/drain is formed, (1) at least a recess is formed in the substrate beside the gate structure. An epitaxial structure is formed in the recess. (2) A cleaning process may be performed to clean the surface of the substrate beside the gate structure. An epitaxial structure is formed in the substrate beside the gate structure.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: February 24, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chin-Cheng Chien
  • Publication number: 20150044881
    Abstract: According to the present disclosure, a film containing carbon added at a high concentration is formed with high controllability. A method of manufacturing a semiconductor device includes forming a film containing silicon, carbon and a predetermined element on a substrate by performing a cycle a predetermined number of times. The predetermined element is one of nitrogen and oxygen. The cycle includes supplying a precursor gas containing at least two silicon atoms per one molecule, carbon and a halogen element and having an Si—C bonding to the substrate, and supplying a modifying gas containing the predetermined element to the substrate.
    Type: Application
    Filed: August 6, 2014
    Publication date: February 12, 2015
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi SHIMAMOTO, Yoshiro HIROSE, Atsushi SANO
  • Publication number: 20150035073
    Abstract: A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region.
    Type: Application
    Filed: August 5, 2013
    Publication date: February 5, 2015
    Applicants: GLOBALFOUNDRIES Inc., INTERNATIONAL BUSINESS MACHINES CORPORAITON
    Inventors: Takashi Ando, Eduard A. Cartier, Kisik Choi, Wing L. Lai, Vijay Narayanan, Ravikumar Ramachandran
  • Patent number: 8946095
    Abstract: A method of forming an interlayer dielectric film above a metal gate of a metal oxide semiconductor device comprises forming a metal gate above a semiconductor substrate; and forming the interlayer dielectric film above the metal gate by reacting a silicon-containing compound as precursor and a reactant for oxidizing the silicon-containing compound. The silicon-containing compound has the formula: Six(A)y(B)z(C)m(D)n??(I) wherein x is in the range of from 1 to 9; y+z+m+n is in the range of from 4 to 20; and A, B, C, and D independently represent a functional group connecting with a silicon atom. The functional group is selected from a group consisting of alkyl, alkenyl, alkynyl, aryl, alkylaryl, alkoxyl, alkylcarbonyl, carboxyl, alkylcarbonyloxy, amide, amino, alkylcarbonylamino, —NO2, and —CN.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li Chen, Jyh-Nan Lin, Chin-Feng Sun, Po-Hsiung Leu, Ding-I Liu
  • Patent number: 8932954
    Abstract: According to one embodiment, an impurity analysis method comprises performing vapor-phase decomposition on a silicon-containing film formed on a substrate, heating the substrate at a first temperature after vapor phase decomposition, heating the substrate at a second temperature higher than the first temperature after heating at the first temperature, to remove a silicon compound deposited on the surface of the silicon-containing film, dropping a recovery solution onto the substrate surface after heating at the second temperature and moving the substrate surface, to recover metal into the recovery solution, and drying the recovery solution, to perform X-ray fluorescence spectrometry on a dried mark.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: January 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuji Yamada, Makiko Katano, Chikashi Takeuchi, Tomoyo Naito
  • Publication number: 20140346648
    Abstract: A low-K nitride film and a method of making are disclosed. Embodiments include forming a nitride film on a substrate by plasma enhanced chemical vapor deposition (PECVD) and periodically fluctuating a production of radicals during the PECVD based, at least in part, on plural cycles of a radiofrequency (RF) induced plasma.
    Type: Application
    Filed: May 23, 2013
    Publication date: November 27, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Huy CAO, Huang LIU, Vijayalakshmi SESHACHALAM
  • Patent number: 8895377
    Abstract: An embodiment of the disclosed invention is a method for manufacturing a semiconductor device, which includes the steps of: forming a first insulating film; performing oxygen doping treatment on the first insulating film to supply oxygen to the first insulating film; forming a source electrode, a drain electrode, and an oxide semiconductor film electrically connected to the source electrode and the drain electrode, over the first insulating film; performing heat treatment on the oxide semiconductor film to remove a hydrogen atom in the oxide semiconductor film; forming a second insulating film over the oxide semiconductor film; and forming a gate electrode in a region overlapping with the oxide semiconductor film, over the second insulating film. The manufacturing method allows the formation of a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: November 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8895456
    Abstract: A method of depositing a film of forming a doped oxide film including a first oxide film containing a first element and doped with a second element on substrates mounted on a turntable including depositing the first oxide film onto the substrates by rotating the turntable predetermined turns while a first reaction gas containing the first element is supplied from a first gas supplying portion, an oxidation gas is supplied from a second gas supplying portion, and a separation gas is supplied from a separation gas supplying portion, and doping the first oxide film with the second element by rotating the turntable predetermined turns while a second reaction gas containing the second element is supplied from one of the first and second gas supplying portions, an inert gas is supplied from another one, and the separation gas is supplied from the separation gas supplying portion.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: November 25, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Mitsuhiro Tachibana, Hiroaki Ikegawa, Yu Wamura, Muneyuki Otani, Jun Ogawa, Kosuke Takahashi
  • Patent number: 8846549
    Abstract: A non-volatile memory device on a semiconductor substrate may include a bottom oxide layer over the substrate, a middle layer of silicon nitride over the bottom oxide layer, and a top oxide layer over the middle layer. The bottom oxide layer may have a hydrogen concentration of up to 5E19 cm?3 and an interface trap density of up to 5E11 cm?2 eV?1. The three-layer structure may be a charge-trapping structure for the memory device, and the memory device may further include a gate over the structure and source and drain regions in the substrate.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: September 30, 2014
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Yen-Hao Shih, Hang-Ting Lue, Erh-Kun Lai, Kuang Yeu Hsieh
  • Publication number: 20140273524
    Abstract: Provided are methods for the deposition and doping of films comprising Si. Certain methods involve depositing a SiN, SiO, SiON, SiC or SiCN film and doping the Si-containing film with one or more of C, B, O, N and Ge by a plasma implantation process. Such doped Si-containing films may have improved properties such as reduced etch rate in acid-based clean solutions, reduced dielectric constant and/or improved dielectric strength.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Inventors: Victor Nguyen, Mihaela Balseanu, Li-Qun Xia, Ning Li, Martin A. Hilkene, Matthew D. Scotney-Castle
  • Patent number: 8828887
    Abstract: In sophisticated semiconductor devices, an efficient stress decoupling may be accomplished between neighboring transistor elements of a densely packed device region by providing a gap or a stress decoupling region between the corresponding transistors. For example, a gap may be formed in the stress-inducing material so as to reduce the mutual interaction of the stress-inducing material on the closely spaced transistor elements. In some illustrative aspects, the stress-inducing material may be provided as an island for each individual transistor element.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: September 9, 2014
    Assignee: GLOBALFOUNDRIE Inc.
    Inventors: Kai Frohberg, Frank Feustel, Thomas Werner
  • Patent number: 8815753
    Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, fluoroalkyl groups, heteroaryl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: August 26, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Tony P. Chiang, Majid Keshavarz, David E. Lazovsky
  • Patent number: 8796146
    Abstract: Method and apparatus for direct writing of passive structures having a tolerance of 5% or less in one or more physical, electrical, chemical, or optical properties. The present apparatus is capable of extended deposition times. The apparatus may be configured for unassisted operation and uses sensors and feedback loops to detect physical characteristics of the system to identify and maintain optimum process parameters.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: August 5, 2014
    Assignee: Optomec, Inc.
    Inventors: Michael J. Renn, Bruce H. King, Jason A. Paulsen
  • Patent number: 8785334
    Abstract: A select transistor for use in a memory device including a plurality of memory transistors connected in series includes a tunnel insulating layer formed on a semiconductor substrate, a charge storage layer formed on the tunnel insulating layer, a blocking insulating layer formed on the charge storage layer and configured to be irradiated with a gas cluster ion beam containing argon as source gas, a gate electrode formed on the blocking insulating layer, and a source/drain region formed within the semiconductor substrate at both sides of the gate electrode.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: July 22, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Yoshitsugu Tanaka
  • Publication number: 20140179100
    Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The remote plasma source may be used to provide a plasma surface treatment or as a source to incorporate dopants into a pre-deposited layer.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 26, 2014
    Applicant: INTERMOLECULAR, INC.
    Inventors: Sandip Niyogi, Amol Joshi, Chi-I Lang, Salil Mujumdar