Abstract: Nanowire articles and methods of making the same are disclosed. A conductive article includes a plurality of inter-contacting nanowire segments that define a plurality of conductive pathways along the article. The nanowire segments may be semiconducting nanowires, metallic nanowires, nanotubes, single walled carbon nanotubes, multi-walled carbon nanotubes, or nanowires entangled with nanotubes. The various segments may have different lengths and may include segments having a length shorter than the length of the article. A strapping material may be positioned to contact a portion of the plurality of nanowire segments. The strapping material may be patterned to create the shape of a frame with an opening that exposes an area of the nanowire fabric. Such a strapping layer may also be used for making electrical contact to the nanowire fabric especially for electrical stitching to lower the overall resistance of the fabric.

Abstract: A method for forming a photodiode that is self-aligned to a transfer gate while being compatible with a metal silicide process is disclosed. The method comprises forming a gate stack of gate oxide, polysilicon, and a sacrificial/disposable cap insulator over the polysilicon. The insulator may be a combination of silicon oxynitride and silicon dioxide. After formation of the photodiode, the cap insulator layer is removed.

Abstract: A thin film transistor array substrate structure includes a plurality of data lines; a plurality of gate lines intersecting the data lines to define pixel areas, the gate line being adjacent to at least two pixel areas; a plurality of common lines disposed between the at least two pixel areas; a plurality of thin film transistors formed at each intersection between the gate lines and the data lines; a plurality of common electrodes provided substantially parallel to the common lines; and a plurality of pixel electrodes connected to the thin film transistors.

Abstract: A solid-state imaging device includes: a plurality of N-type photodiode regions formed inside a P-type well; a gate electrode having one edge being positioned adjacent to each of the photodiode regions; a N-type drain region positioned adjacent to the other edge of the gate electrode; an element-isolating portion having a STI structure, and a gate oxide film having a thickness of not more than 10 nm. One edge of the gate electrode overlaps the photodiode region.

Abstract: The present invention provides a power-thrifty IT-CCD having a charge transfer electrode area thinned for improving the light reception efficiency of a photoelectric conversion section and being capable of executing high-speed and high-sensitivity transfer without lowering withstand voltage between charge transfer electrodes. A first insulation film is formed on the surface of a silicon substrate, and inter-electrode insulation films made of silicon oxide films and charge transfer electrodes made of polycrystalline silicon films are formed on the surface of the first insulation film. The inter-electrode insulation films are formed from side walls of the polycrystalline silicon films.

Abstract: A method is for filtering data output from an array of pixels in an image sensor. The method may include filtering noise from variation in pixel response across the array. An electronic device may have a device for filtering data output from an array of pixels in an image sensor. The device may include a noise filter for removing variation in pixel response across the array.

Abstract: A plurality of optical sensors (4) are arranged in a surface region of a semiconductor substrate (6) in a matrix pattern, and electric charge generated by the optical sensors (4) is transferred by first and second transfer electrodes (12 and 14) embedded under the optical sensors (4). The semiconductor substrate (6) is constructed by laminating a support substrate (16) composed of silicon, a buffer layer (18), and a thin silicon layer (20) composed of single-crystal silicon. p? regions (26) (overflow barrier) and n-type regions (28) which function as transfer paths are formed under the optical sensors (4). The first and the second transfer electrodes (12 and 14) are disposed between the buffer layer (18) and the n-type regions (28), and an insulating film (30) is interposed between the n-type regions (28) and the first and the second transfer electrodes (12 and 14). In this structure, the light-receiving area is large since the transfer electrodes are not disposed in the front region.

Abstract: A CMOS image sensor and a method for fabricating the same is disclosed, to enhance the image-sensing efficiency by forming a concave lens area for improving the light-condensing efficiency in a planarization layer formed before a micro-lens array, in which the CMOS image sensor includes a plurality of photosensitive devices on a semiconductor substrate; an insulating interlayer on the plurality of photosensitive devices; a plurality of color filter layers in correspondence with the respective photosensitive devices, to filter the light by respective wavelengths; a planarization layer on the color filter layers, and having first micro-lens by intaglio in correspondence with the respective photosensitive patterns to condense the light secondly; and a plurality of second micro-lens layers on the planarization layer in correspondence with the respective photosensitive devices, to condense the light firstly.

Abstract: A charge transfer element comprising a reverse conductive type well formed on the surface of one conductive type semiconductor substrate, the one conductive type channel region extending in one direction relative to the well, a transfer electrode formed intersecting the channel region, a floating diffusion region formed continuous from the channel region, and an output transistor having a gate connected to the floating diffusion region. In a region where the output transistor is formed, the dopant density profile in the depth direction of the semiconductor substrate exhibits the maximum value relative to a middle region.

Abstract: A CMOS image sensor and a manufacturing method thereof, wherein the gates of several transistors of the CMOS image sensor are formed in an active region defined by an isolation region for a unit pixel of the CMOS image sensor, and a passivation layer composed of insulating layer is formed on the semiconductor substrate. Impurities are ion-implanted into the active region to form one or more diffusion regions of a photo diode of the CMOS image sensor, wherein the passivation layer prevents a boundary portion of the active region from being ion-implanted. Thus, damages by ion implantation at the boundary portion between the diffusion region for the photo diode and the isolation region are prevented, and the dark current of the CMOS image sensor is reduced.

Abstract: A pixel of a semiconductor-based image detector includes a photodetector, at least one switching device serially connected to the photodetector and a bypass device interposed between the photodetector and a power supply voltage. Accordingly, even though excess charges may be generated in the photodetector, the excess charges flow into the power supply through the bypass device. Blooming can thereby be reduced or suppressed.

Abstract: The present invention provides a micro-electro-mechanical system (MEMS) device, a method of manufacture therefore, and an optical communications system including the same. The device includes an electrode located over a substrate and a charge dissipation layer located proximate and electrically coupled to the substrate. The device may further include a moveable element located over the electrode.

Abstract: Disclosed is a method for fabricating a solid-state imaging device including a semiconductor substrate of a first conductivity type, a plurality of light-receiving sections provided at a distance in the surface region of the semiconductor substrate, and channel stop regions of a second conductivity type provided between the adjacent light-receiving sections in the surface region and in the internal region of the semiconductor substrate. The method includes the steps of forming a first photoresist layer having openings corresponding to positions at which the channel stop regions are formed; ion-implanting an impurity of a second conductivity type into the semiconductor substrate at a first energy through the first photoresist layer as a mask; forming a second photoresist layer having openings; and ion-implanting an impurity of a second conductivity type into the semiconductor substrate at a second energy through the second photoresist layer as a mask.

Abstract: An embodiment of the invention is a method to reduce light induced corrosion and re-deposition of a metal, 8, (such as copper) that is used to make the interconnect wiring during the semiconductor manufacturing process. The light induced corrosion and re-deposition is caused by the exposure of a P-N junction to light, causing a photovoltaic effect. A photon-blocking layer, 13, is used in the invention to reduce the amount of exposure of the P-N junction to light. The photon blocking layer, 13, of the invention may be a direct band-gap material with a band-gap energy that is less than the lower edge of the energy spectrum of a typical light source used in the semiconductor manufacturing facility (typically less than 1.7 eV).

Abstract: A sensor may be formed with a transistor comprising a gate that has both n-type and p-type regions to increase the gate work function. In combination with moving the p-type well such that the p-type well only partially dopes the channel of the transistor, the increased gate work function further increases the reset voltage level required to create the reset channel without having to use high doping levels in the critical regions of the sensor structure including the photo-detector and the reset transistor. The source of the reset transistor is partially beneath the n-type region of gate, while the transistor's drain is partially beneath the p-type region of the gate. The channel has a p-type well portion and a substrate portion. This construction of the sensor may eliminate the reset noise associated with the uncertainty of whether the charge left in the transistor's channel will flow back towards the photo-detector after the transistor has been turned off.

Abstract: The present invention provides a micro-electro-mechanical system (MEMS) device, a method of manufacture therefore, and an optical communications system including the same. The device includes an electrode located over a substrate and a charge dissipation layer located proximate and electrically coupled to the substrate. The device may further include a moveable element located over the electrode.

Abstract: A method for in-line testing of a chip to include multiple independent bit Flash memory devices, includes the steps of: grounding every other polysilicon line on the chip to emulate the multiple independent bit Flash memory devices, where an oxide line reside between every two polysilicon lines; scanning the polysilicon lines with an electron beam; examining voltage contrasts between the polysilicon lines; and determining if there are consecutively grounded polysilicon lines based on the voltage contrasts. If consecutive polysilicon lines appear to be grounded, then this indicates that a bridge defect exists between two of the consecutively grounded polysilicon lines. With this method, bridge defects in multiple independent bit Flash memory devices are better detected, leading to improved yield and reliability of the devices.

Abstract: A CMOS image sensor and a method for manufacturing the same, capable of preventing an interface between an active region and a field region in the CMOS image sensor from being damaged by ion implantation. The method comprises the steps of depositing a sacrificial oxide layer and a hard mask layer on a semiconductor substrate; etching the sacrificial oxide layer and the hard mask layer to form a mask pattern; etching the substrate to a predetermined depth to form a trench; depositing an isolating material in the trench and planarizing it until substantially coplanar with the hard mask layer; removing the hard mask layer to leave a protrusion in the isolating layer; depositing an insulating layer on the substrate and isolating layer; and etching the insulating layer and the sacrificial oxide layer sufficiently to form a spacer mask and expose the surface of the substrate.

Abstract: Disclosed is a PIN photodiode used for a light-receiving element for optical communication. The PIN photodiode comprises a gate electrode structure consisting of a gate insulation layer and a gate electrode pad which prevent a bonding layer from being excessively depleted in the lateral direction at the time of applying a negative electric voltage to an electrode that is in contact with the bonding layer. The PIN photodiode allows the control of the electrostatic capacitance of the element by controlling the depletion level of the bonding layer in the lateral direction using the gate electrode pad. Therefore, it is possible to suppress the increase of the electrostatic capacitance and to achieve a high-speed operating property.

Abstract: A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is considered to be a different bin of time. A specified pattern is sent, and the output bins are investigated to look for that pattern. The time when the pattern is received indicates the time of flight.

Abstract: A light-receiving element, comprises an absorption layer formed on a semiconductor substrate, a window layer formed on the absorption layer, a first electrode formed on the window layer, a second electrode formed on the window layer and electrically connected to the first electrode, and a diffusion region which is formed in the absorption layer and the window layer and is formed between the first electrode and the substrate and between the second electrode and the substrate.

Abstract: An image sensor with improved productivity and sensitivity is provided. The image sensor includes a plurality of unit pixels, each unit pixel including an oxide film formed upon a semiconductor substrate; a gate electrode formed on the oxide film; a photodiode N-type region formed within the semiconductor substrate and interfacing with the oxide film, which is space apart from the gate electrode by a predetermined distance and disposed on one side of the gate electrode; and a floating diffusion region formed within the semiconductor substrate and interfacing with the oxide film, which is spaced apart from the gate electrode by a predetermined distance and is disposed on the other side of the gate electrode.

Abstract: A low temperature process for forming a metal doped silicon layer in which a silicon layer is deposited onto a substrate at low temperatures, with a metal doping layer then deposited upon the silicon layer. This structure is then annealed at low temperatures to form a metal doped semiconductor having greater than about 1×1020 dopant atoms per cm3 of silicon.

Abstract: A retrograde and periphery well structure for a CMOS imager is disclosed which improves the quantum efficiency and signal-to-noise ratio of the photosensing portion imager. The retrograde well comprises a doped region with a vertically graded dopant concentration that is lowest at the substrate surface, and highest at the bottom of the well. A single retrograde well may have a single pixel sensor cell, multiple pixel sensor cells, or even an entire array of pixel sensor cells formed therein. The highly concentrated region at the bottom of the retrograde well repels signal carriers from the photosensor so that they are not lost to the substrate, and prevents noise carriers from the substrate from diffusing up into the photosensor. The periphery well contains peripheral logic circuitry for the imager. By providing retrograde and peripheral wells, circuitry in each can be optimized. Also disclosed are methods for forming the retrograde and peripheral well.

Abstract: A conductive trace is formed over and insulated from a region of semiconductor material, such as a region adjacent to the n+ region of an n+/p− photodiode, and a sawtooth current is made to flow through the conductive trace. The sawtooth current induces charge carriers to move through the semiconductor material to a collection region in the semiconductor material.

Abstract: A solid-state pickup element achieves both improvement in sensitivity and reduction of pixel size and a method thereof, includes a first conductive type semiconductor area, which is formed at least so as to include the inside of the semiconductor substrate upward of the overflow barrier area inside the semiconductor substrate, and a charge accumulating area at the position corresponding to the first conductive type semiconductor area of the light receptive sensor part in the epitaxial layer on the semiconductor substrate. An overflow barrier area is formed in the semiconductor substrate, and the first conductive type semiconductor area is formed on the surface, respectively, wherein an epitaxial layer is formed on the semiconductor substrate, and a charge accumulating area is formed at the position corresponding to the first conductive type semiconductor area on the surface side of the epitaxial layer, thereby producing a solid-state pickup element.

Abstract: A compact sensing apparatus having reduced cross section and methods are provided for sensing the magnitude and direction of an electrical or magnetic field. The compact sensing apparatus and method preferably provide one of two transducer orientations in relation to the direction of the field arranged in the sensor apparatus to provide the smallest possible cross section. The compact sensing apparatus preferably includes a plurality of mounting pins. Each of the plurality of mounting pins preferably includes a first pin portion and a second pin portion connected to the first pin portion at a predetermined angle. The predetermined angle is preferably less than 180 degrees and more preferably in the range of about 70-110 degrees.

Abstract: A circuit-incorporating light receiving device includes an integrated circuit and a photodiode. The integrated circuit and the photodiode are provided on a single semiconductor substrate. The integrated circuit includes a transistor having a polycrystalline silicon as an emitter diffusion source and an electrode. Elements included in the integrated circuit are isolated from each other using local oxidization.

Abstract: A barrier area is located adjacent a horizontal transfer area and spaced from a field insulating area. The barrier area includes an insulating layer and a conductor extending from the horizontal transfer layer over the surface of a semiconductor substrate, a barrier layer of a second conductivity type formed under the surface of the semiconductor substrate and adjacent a first impurity layer of a first conductivity type of the horizontal transfer area, and a second impurity layer extending from the horizontal transfer area and formed under the barrier layer. A discharge area is located between the barrier area and the field insulating area.

Abstract: An image sensor, includes a semiconductor substrate; a photosensor having, a first photosensing region including a first stack of one or more layers of transparent materials overlying the substrate, the first photosensing region having a spectral response having peaks and valleys, and a second photosensing region including a second stack of one or more layers of transparent materials overlying the substrate, the second photosensing region having a spectral response having peaks and valleys; and wherein at least one peak or valley of the spectral response of the first region is matched to at least one valley or peak respectively of the spectral response of the second region such that the average spectral response of the photosensor is smoother than the individual spectral response of either the first or second photosensing regions.

Abstract: The invention relates to a CCD of the buried-channel type comprising a charge-transport channel in the form of a zone (12) of the first conductivity type, for example the n-type, in a well (13) of the opposite conductivity type, in the example the p-type. In order to obtain a drift field in the channel below one or more gates (9, 10a) to improve the charge transfer, the well is provided with a doping profile, so that the average concentration decreases in the direction of charge transport. Such a profile can be formed by covering the area of the well during the well implantation with a mask, thereby causing fewer ions to be implanted below the gates (9, 10a) than below other parts of the channel. By virtue of the invention, it is possible to produce a gate (10a) combining a comparatively large length, for example in the output stage in front of the output gate (9) to obtain sufficient storage capacity, with a high transport rate.

Abstract: A photo-detecting device includes: a semiconductor substrate; a multilayer structure formed on the semiconductor substrate; an island-like photo-detecting region formed in at least a portion of the multilayer structure, the island-like photo-detecting region having a central portion; and a light-shielding mask formed on the semiconductor substrate so as to shield from light a portion of the island-like photo-detecting region at least excluding the central portion. The light-shielding mask comprises an upper metal film and a lower metal film, and the upper metal film and the lower metal film are at least partially isolated by an insulative film, the upper metal film and the lower metal film having different patterns.

Abstract: The invention relates to a production method for a solar cell and to the solar cell itself which comprises an integrated bypass diode on the side facing away from the incidence of light and which can be produced in a simple manner by diffusion. A one-piece electric conductor serves to connect two successive solar cells in series and simultaneously effects the contacting of the corresponding bypass diode.

Abstract: The charge coupled device (CCD) formed according the method of the present invention includes a substrate, at least two photodiodes formed in the substrate and a first insulating layer formed on the substrate. A first transfer gate is formed on a portion of the first insulating layer between the photodiodes. A second insulating layer covers the first transfer gate, and has a projecting portion projecting up from the first transfer gate. The CCD further includes second and third transfer gates disposed over respective sides of the projecting portion of the second insulating layer and the first transfer gate with the second and third transfer gates having a gap therebetween over the projecting portion. A third insulating layer covers the second and third transfer gates, and a fourth transfer gate is formed over a portion of the second and third transfer gates and over the projecting portion of the second insulating layer.

Abstract: Provided is a method of fabrication of a blooming control structure for an imager. The structure is produced in a semiconductor substrate in which is configured an electrical charge collection region. The electrical charge collection region is configured to accumulate electrical charge that is photogenerated in the substrate, up to a characteristic charge collection capacity. A blooming drain region is configured in the substrate laterally spaced from the charge collection region. The blooming drain region includes an extended path of a conductivity type and level that are selected for conducting charge in excess of the characteristic charge collection capacity away from the charge collection region. A blooming barrier region is configured in the substrate to be adjacent to and laterally spacing the charge collection and blooming drain regions by a blooming barrier width. This barrier width corresponds to an acute blooming barrier impurity implantation angle with the substrate.

Abstract: A method of manufacturing an electro-optical apparatus substrate (10), includes the processes of: forming a light shield layer on one surface of an optically transparent substrate; patterning the light shield layer to thereby form a patterned light shield layer (11a) at least in a formation region of each transistor element (30) to be formed; forming a first insulation layer (12A) above the one surface of the optically transparent substrate above which the patterned light shield layer has been formed; forming a second insulation layer (12B) having a polishing rate lower than that of the first insulation layer, on the first insulation layer; polishing a surface of the second insulation layer; laminating a single crystal silicon layer (206) on the polished surface of the second insulation layer; and forming the each transistor element by using the single crystal silicon layer.

Abstract: A solid-state imaging device comprises a plurality of pixels, each pixel comprising a semiconductor substrate of a first conductivity type; a photo-receiving portion of a second conductivity type formed in the semiconductor substrate; a detecting portion of the second conductivity type formed in the semiconductor substrate; an insulating film formed on the semiconductor substrate; a transfer gate electrode formed on the insulating film at lest between the photo-receiving portion and the detecting portion; and a read-out circuit, which is electrically connected to the detecting portion. A diffusion region of the same conductivity type as the detecting portion is formed in a region of the semiconductor substrate that is adjacent to an end of the detecting portion near the gate electrode and separate from the photo-receiving portion. An impurity concentration in the photo-receiving portion and an impurity concentration in the diffusion region are lower than an impurity concentration in the detecting portion.

Abstract: A fast frame-rate CCD imaging device is produced by modifying the optical mask of an otherwise ordinary and inexpensive CCD integrated circuit to darken a majority of the active imaging photocells. The modified CCD integrated circuit is operated at near its maximum horizontal and vertical clock rates, but multiple image frames are newly defined within the one previous active photocell array field. The added dark areas in the optical mask act to protect all recent frames still in transit within the active array area from being double exposed and thus corrupted.

Abstract: P-type ion implantation is done in N well 15, so as to form a charge drain control layer 17 and form a photodiode N well 16 and OFD drain 5, the result being that, even if there is variation in the potential of the photodiode N well 16 making up the photodiode, because the variation in the potential of the charge drain control layer 17 is in the same direction as the potential of the photodiode N well 16, so that variation does not occur in the maximum amount of electrical charge that can be accumulated, the result being that there is no variation in the signal in the saturation condition.

Abstract: A compact sensing apparatus having reduced cross section and methods are provided for sensing the magnitude and direction of an electrical or magnetic field. The compact sensing apparatus and method preferably provide one of two transducer orientations in relation to the direction of the field arranged in the sensor apparatus to provide the smallest possible cross section. The compact sensing apparatus preferably includes a plurality of mounting pins. Each of the plurality of mounting pins preferably includes a first pin portion and a second pin portion connected to the first pin portion at a predetermined angle. The predetermined angle is preferably less than 180 degrees and more preferably in the range of about 70-110 degrees.

Abstract: A first silicon oxide film, silicon nitride film, and polycrystalline silicon film are formed on the entire surface of a semiconductor substrate. Then, the polycrystalline silicon film is etched to form a first transfer electrode and then, the surface of the first transfer electrode isothermally oxidized to form a second silicon oxide film. Thereafter, a polycrystalline silicon film and a third silicon oxide film are formed on the entire surface and patterned to form a second transfer electrode. A fourth silicon oxide film is formed on the entire surface, and is etched back. Thereafter, the side wall surfaces of the third silicon oxide film and the second transfer electrode are covered with a fourth silicon oxide film. Thereafter, a light shielding film is selectively formed on them.

Abstract: The optimization of two technologies (CMOS and CCD) wherein a pinned photodiode is integrated into the image sensing element of an active pixel sensor. Pinned photodiodes are fabricated with CCD process steps into the active pixel architecture. Charge integrated within the active pixel pinned photodiode is transferred into the charge sensing node by a transfer gate. The floating diffusion is coupled CMOS circuitry that can provide the addressing capabilities of individual pixels. Alternatively, a buried channel photocapacitor can be used in place of the pinned photodiode.

Abstract: The lateral overflow drain for charge coupled devices includes: a semiconductor region 70 of a first conductivity type having a trench 92; a drain region 24 of a second conductivity type below the trench 92; a gate 20 in the trench 92 overlying and separated from a portion of the semiconductor region 70; and a virtual gate 30 of the first conductivity type in the semiconductor region 70 adjacent the trench 92.

Abstract: In an amplifying type solid-state imaging device having a pixel MOS transistor, the occurrence of blooming can be suppressed and an amount of signal charges can be increased. A second conductivity-type overflow-barrier region (23) and a first conductivity-type semiconductor region (24) are sequentially formed on a first conductivity-type semiconductor substrate (22). A pixel MOS transistor (29) comprising a source region (27), a drain region (28) and a gate portion (26) is formed on the first conductivity-type semiconductor region (24), and a second conductivity-type channel stopper region (41) for signal charges accumulated in the first conductivity-type semiconductor region (24) of the gate portion (26) is formed within the first conductivity-type semiconductor region (24) formed just below the drain region (28).

Abstract: A semiconductor photosensitive element comprises first and second photosensitive regions. The first photosensitive region is different from the second photosensitive region in its structure and thereby the first photosensitive region has photoelectric conversion characteristic and frequency characteristic which are different from those of the second photosensitive region.

Abstract: By introducing an n-type drain implant substantially below the surface of the p-type substrate of a full frame image sensor, then enclosing the drain on the bottom and the sides with a deep p-type implant, and accumulating the surface with a shallow p-type implant, with all implantations performed through the same mask aperture, the blooming control, channel stop, and dark current suppression features of the imager are compressed, increasing the fill factor, facilitating pixel miniaturization, and therefore enabling high resolution imaging applications.

Abstract: A CCD solid state imaging device can reduce a smear component. This CCD solid state imaging device comprises a plurality of photosensor sections (10) arranged in a matrix fashion, a vertical transfer register (5) having a transfer electrode (16) disposed at every column of the photosensor sections, a shunt line layer (33) connected to the transfer electrode (16) on the vertical transfer register (5), and a photo-shield layer (38) formed so as to surround the photosensor section 10 through an interlayer insulating layer (37) which covers the shunt layer (33), in which the interlayer insulating layer (37) is formed under an overhang portion (38a) of the photo-shield layer (38) to the photosensor section (10).