Abstract: In one embodiment, a method of selectively forming a deposit may include providing a substrate, the substrate having a plurality of surface features, extending at a non-zero angle of inclination with respect to a perpendicular to a plane of the substrate. The method may include directing a reactive beam to the plurality of surface features, the reactive beam defining a non-zero angle of incidence with respect to a perpendicular to the plane of the substrate, wherein a seed layer is deposited on a first portion of the surface features, and is not deposited on a second portion of the surface features. The method may further include exposing the substrate to a reactive deposition process after the directing the reactive ion beam, wherein a deposit layer selectively grows over the seed layer.

Abstract: A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. The memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier. Conducting material of a lowest of the conductive tiers is directly against the conductor material of the conductor tier. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The conducting material in the lowest conductive tier is directly against the channel material of individual of the channel-material strings. Conductive material is of different composition from that of the conducting material above and directly against the conducting material. Other embodiments, including method, are disclosed.

Abstract: Described herein is a technique capable of improving the controllability of firm thickness distribution. According to one aspect of the technique, there is provided a substrate processing apparatus including: a process chamber; a first and a second gas supply system; an exhaust system; and a controller for controlling the first and the second gas supply system and the exhaust system to form a film. The first gas supply system includes: a first and a second storage part; a first gas supply port for supplying a gas stored in the first storage part from an outer periphery toward a center of a substrate; and a second gas supply for supplying the gas stored in the second storage part from the outer periphery along a direction more inclined toward the outer periphery than a direction from the outer periphery toward the center of the substrate.

Abstract: A method for depositing material is disclosed. An exemplary method includes positioning a substrate provided with a stepped structure comprising a top surface, a bottom surface, and a sidewall in a reaction chamber; controlling a pressure of the reaction chamber to a process pressure; providing a precursor; providing a reactant; and, providing a plasma with a RF plasma power, wherein by simultaneously providing the precursor, the reactant, and the plasma while controlling the process pressure to less than or equal to 200 Pa and controlling the RF plasma power to more than or equal to 0.21 W per cm2 the material is deposited on the top surface, the bottom surface, and the sidewall of the stepped structure.

Abstract: Exemplary methods of semiconductor processing may include forming a silicon oxide material on exposed surfaces of a processing region of a semiconductor processing chamber. The methods may include forming a silicon nitride material overlying the silicon oxide material. The methods may include performing a deposition process on a semiconductor substrate disposed within the processing region of the semiconductor processing chamber. The methods may include performing a chamber cleaning process.

Abstract: Embodiments of the present disclosure provide nanopore devices, such as nanopore sensors and/or other nanofluidic devices. In one or more embodiments, a nanopore device contains a substrate, an optional lower protective oxide layer disposed on the substrate, a membrane disposed on the lower protective oxide layer, and an optional upper protective oxide layer disposed on the membrane. The membrane has a pore and contains silicon nitride. The silicon nitride has a nitrogen to silicon ratio of about 0.98 to about 1.02 and the membrane has an intrinsic stress value of about ?1,000 MPa to about 1,000 MPa. The nanopore device also contains a channel extending through at least the substrate, the lower protective oxide layer, the membrane, the upper protective oxide layer, and the upper protective silicon nitride layer.

Abstract: Embodiments of the present disclosure generally relate to methods of forming hardmasks. Embodiments described herein enable, e.g., formation of carbon-containing hardmasks having reduced film stress. In an embodiment, a method of processing a substrate is provided. The method includes positioning a substrate in a processing volume of a processing chamber and depositing a diamond-like carbon (DLC) layer on the substrate. After depositing the DLC layer, the film stress is reduced by performing a plasma treatment, wherein the plasma treatment comprises applying a radio frequency (RF) bias power of about 100 W to about 10,000 W.

Abstract: An NVM device includes a semiconductor substrate, a first floating gate, a first control gate, a first drain region, and a common source region. The semiconductor substrate has a recess extending downward from the substrate surface. The first floating gate is disposed in the recess, has a base and a side wall connecting to the base. The first control gate is disposed on and adjacent to the first floating gate. The first drain region is disposed in the semiconductor substrate in the recess. The common source region is formed in the semiconductor substrate in the recess, is adjacent to the first floating gate, and includes a main body and an extension part. The main body is disposed below a bottom surface of the recess and adjacent to the base. The extension part extends upward from the bottom surface beyond the base to be adjacent to the side wall.

Abstract: A film forming apparatus sequentially supplies a raw material gas of a compound containing chlorine and an element other than the chlorine, and a first reaction to form a fil. The film forming apparatus includes a rotary table, a raw material gas ejection port configured to eject the raw material gas to a first region, a reaction gas supply part configured to supply, to a second region, a first reaction gas and a second reaction gas that reacts with chlorine to generate a third reaction product, in order to prevent a second reaction product from being generated due to a reaction of the chlorine remaining in the vacuum container with air when performing the opening-to-air. The film forming apparatus further includes an atmosphere separation part, a first exhaust port and a second exhaust port, and a controller.

Abstract: A microfluidic device includes a silicon device and a metallic component. The silicon device and the metallic component are attached by preparing a surface of a silicon device to be solderable, preparing a corresponding surface of a metallic component to be solderable, and soldering the prepared surface of the silicon device to the corresponding prepared surface of the metallic component with a solder of a pre-defined composition and thickness to accommodate strain due to co-efficient of thermal expansion (CTE) mismatch between the silicon device and the metallic component.

Abstract: A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.

Abstract: A method for fabricating a semiconductor device includes forming a line structure including a first contact plug on a semiconductor substrate and a conductive line on the first contact plug, forming a low-k layer having a first low-k, which covers a top surface and side walls of the line structure, performing a converting process on the low-k layer to form a non-converting portion adjacent to side walls of the first contact plug and maintains the first low-k and a converting portion adjacent to side walls of the conductive line and having a second low-k that is lower than the first low-k, and forming a second contact plug which is adjacent to the first contact plug with the non-converting portion therebetween while being adjacent to the conductive line with the converting portion therebetween.

Abstract: Methods of depositing uniform films on substrates using multi-cyclic atomic layer deposition techniques are described. Methods involve varying one or more parameter values from cycle to cycle to tailor the deposition profile. For example, some methods involve repeating a first ALD cycle using a first carrier gas flow rate during precursor exposure and a second ALD cycle using a second carrier gas flow rate during precursor exposure. Some methods involve repeating a first ALD cycle using a first duration of precursor exposure and a second ALD cycle using a second duration of precursor exposure.

Abstract: Embodiments of a blocker plate for use in a substrate process chamber are disclosed herein. In some embodiments, a blocker plate for use in a substrate processing chamber configured to process substrates having a given diameter includes: an annular rim; a central plate disposed within the annular rim; and a plurality of spokes coupling the central plate to the annular rim.

Abstract: A semiconductor device includes: a protruding conductive structure that protrudes to a height from a first surface of the semiconductor device; and a first passivation layer, the first passivation layer overlaying the protruding conductive structure by a first thickness, the first passivation layer overlaying the first surface by a second thickness greater than the first thickness, wherein the first passivation layer is planar at a top surface over the first thickness and the second thickness.

Abstract: Embodiments described herein relate to manufacturing layer stacks of oxide/nitride (ON) layers with minimized in-plane distortion (IPD) and lithographic overlay errors. A method of forming a layer stack ON layers includes flowing a first silicon-containing gas, an oxygen-containing gas, and a first dilution gas. A RF power is symmetrically applied to form a first material layer of SiO2. A second silicon-containing gas, a nitrogen-containing gas, and a second dilution gas are flowed. A second RF power is symmetrically applied to form a second material layer of Si3N4. The flowing the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power is repeated until a desired number of first material layers and second material layers make up a layer stack.

Abstract: Chemical vapor deposition processes and coated articles are disclosed. The process includes a first introducing of a first amount of silane to the enclosed chamber, the first amount of the silane remaining within the enclosed chamber for a first period of time, a first decomposing of the first amount of the silane during at least a portion of the first period of time, a second introducing of a second amount of the silane to the enclosed chamber, the second amount of the silane remaining within the enclosed chamber for a second period of time, and a second decomposing of the second amount of the silane during at least a portion of the second period of time. The process is devoid of inert gas purging between the first decomposing and the second introducing and/or produces a chemical vapor deposition coating devoid of hydrogen bubbles.

Abstract: A film deposition method includes steps of: placing a substrate in a substrate receiving area of a susceptor provided in a vacuum chamber; evacuating the vacuum chamber; alternately supplying plural kinds of reaction gases to the substrate in the substrate receiving area from corresponding reaction gas supplying parts thereby to form a thin film on the substrate; supplying plasma including a chemical component that reacts with second reaction gas adsorbed on the substrate from a plasma generation part to the substrate when the thin film is being formed, thereby to alter the thin film on the substrate; and changing plasma intensity of the plasma supplied to the substrate, at a predetermined point of time to a different plasma intensity of the plasma that is generated and supplied to the substrate by the plasma generation part before the predetermined point of time.

Abstract: Embodiments of the present disclosure relate to methods for in-situ deposition and treatment of a thin film for improved step coverage. In one embodiment, the method for processing a substrate is provided. The method includes forming a dielectric layer on patterned features of the substrate by exposing the substrate to a gas mixture of a first precursor and a second precursor simultaneously with plasma present in a process chamber, wherein the plasma is formed by a first pulsed RF power, exposing the dielectric layer to a first plasma treatment using a gas mixture of nitrogen and helium in the process chamber, and performing a plasma etch process by exposing the dielectric layer to a plasma formed from a gas mixture of a fluorine-containing precursor and a carrier gas, wherein the plasma is formed in the process chamber by a second pulsed RF power.

Abstract: A method of manufacturing a variable resistance memory device includes: forming an array of memory cells on a substrate, each memory cell including a variable resistance structure and a switching element; and forming a sidewall insulating layer covering a sidewall of the switching element. The forming the sidewall insulating layer includes: a preliminary step of supplying a silicon source to an exposed sidewall of the switching element; and a main step of performing a process cycle a plurality of times, the process cycle comprising supplying the silicon source and supplying a reaction gas, A time duration of the supplying the silicon source in the preliminary step is longer than a time duration of the supplying the silicon gas in the process cycle in the main step.

Abstract: A treatment, structure and system are provided that modify the deposition process of a material that can occur over two differing materials. In an embodiment the deposition rates may be adjusted by the treatment to change the deposition rate of one of the materials to be more in line with the deposition rate of a second one of the materials. Also, the deposition rates may be modified to be different from each other, to allow for a more selective deposition over the first one of the materials than over the second one of the materials.

Abstract: Methods and precursors for forming silicon nitride films are provided. In some embodiments, silicon nitride can be deposited by atomic layer deposition (ALD), such as plasma enhanced ALD. In some embodiments, deposited silicon nitride can be treated with a plasma treatment. The plasma treatment can be a nitrogen plasma treatment. In some embodiments the silicon precursors for depositing the silicon nitride comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%). In some embodiments, a method for depositing silicon nitride films comprises a multi-step plasma treatment.

Abstract: According to one embodiment, a display device includes an underlying insulation layer formed on a surface of a resin layer, and a thin-film transistor formed above the surface of the resin layer via the underlying insulation layer. The underlying insulation layer includes a three-layer multilayer structure of a first silicon oxide film, a silicon nitride film formed above the first silicon oxide film, and a second silicon oxide film formed above the silicon nitride film.

Abstract: A method for depositing a silicon nitride film is provided to fill a recessed pattern formed in a surface of a substrate. In the method, a first adsorption blocking region is formed by adsorbing first chlorine radicals such that an amount of adsorption increases upward from a bottom portion of the recessed pattern. A source gas that contains silicon and chlorine adsorbs on an adsorption site where the first adsorption site is not formed. A molecular layer of a silicon nitride film is deposited so as to have a V-shaped cross section. A second adsorption blocking region is formed by adsorbing second chlorine radicals on the molecular layer of the silicon nitride film. The molecular layer of the silicon nitride film is modified by nitriding the molecular layer while removing the second adsorption blocking region.

Abstract: There is provided a method of forming a silicon nitride film including: arranging substrates in a process vessel; and forming a silicon nitride film on the substrates in a batch by repeating a cycle including: a first purge step of purging the process vessel while heating the process vessel and making an interior of the process vessel be in a predetermined depressurized state; a film-forming raw material gas adsorbing step of adsorbing a chlorine-containing silicon compound to the substrates by supplying a film-forming raw material gas composed of the chlorine-containing silicon compound into the process vessel; a second purge step of purging the process vessel; and a nitriding step of nitriding the substrates by supplying a nitriding gas into the process vessel, and wherein in each of the cycle, a hydrogen radical purge step is performed between the film-forming raw material gas adsorbing step and the nitriding step.

Abstract: A hydrogen sensor can include a substrate, an Ohmic metal disposed on the substrate, a nitride layer disposed on the substrate and having a first window exposing the substrate, a Schottky metal placed in the first window and disposed on the substrate, a final metal disposed on the nitride layer and the Schottky metal and having a second window exposing the Schottky metal, and a polymethyl-methacrylate (PMMA) layer encapsulating the second window. The PMMA layer can fill the second window and be in contact with the Schottky metal.

Abstract: Embodiments described herein relate to semiconductor and metal substrate surface preparation and controlled growth methods. An example application is formation of an atomic layer deposition (ALD) control layer as a diffusion barrier or gate dielectric layer and subsequent ALD processing. Embodiments described herein are believed to be advantageously utilized concerning gate oxide deposition, diffusion barrier deposition, surface functionalization, surface passivation, and oxide nucleation, among other processes. More specifically, embodiments described herein provide for silicon nitride ALD processes which functionalize, passivate, and nucleate a SiNx monolayer at temperatures below about 300° C.

Abstract: Multilayer dielectric structures are provided with graded composition. For example, a multilayer dielectric structure includes a stack of dielectric films, wherein the dielectric films include at least a first SiCNO (silicon carbon nitride oxide) film and a second SiCNO film. The first SiCNO film has a first composition profile of C, N, and O atoms. The second SiCNO film has a second composition profile of C, N, and O atoms, which is different from the first composition profile of C, N, and O atoms. The composition profiles of C, N and/or O atoms of the constituent dielectric films of the multilayer dielectric structure are customized to enhance or otherwise optimize one or more electrical and/or physical properties of the multilayer dielectric structure.

Abstract: Multilayer dielectric structures are provided with graded composition. For example, a multilayer dielectric structure includes a stack of dielectric films, wherein the dielectric films include at least a first SiCNO (silicon carbon nitride oxide) film and a second SiCNO film. The first SiCNO film has a first composition profile of C, N, and O atoms. The second SiCNO film has a second composition profile of C, N, and O atoms, which is different from the first composition profile of C, N, and O atoms. The composition profiles of C, N and/or O atoms of the constituent dielectric films of the multilayer dielectric structure are customized to enhance or otherwise optimize one or more electrical and/or physical properties of the multilayer dielectric structure.

Abstract: A method of forming a high k gate stack on a surface of a III-V compound semiconductor, such GaAs, is provided. The method includes subjecting a III-V compound semiconductor material to a precleaning process which removes native oxides from a surface of the III-V compound semiconductor material; forming a semiconductor, e.g., amorphous Si, layer in-situ on the cleaned surface of the III-V compound semiconductor material; and forming a dielectric material having a dielectric constant that is greater than silicon dioxide on the semiconducting layer. In some embodiments, the semiconducting layer is partially or completely converted into a layer including at least a surface layer that is comprised of AOxNy prior to forming the dielectric material. In accordance with the present invention, A is a semiconducting material, preferably Si, x is 0 to 1, y is 0 to 1 and x and y are both not zero.

Abstract: A method of forming a memory cell material comprises forming a first portion of a dielectric material over a substrate by atomic layer deposition. Discrete conductive particles are formed on the first portion of the dielectric material by atomic layer deposition. A second portion of the dielectric material is formed on and between the discrete conductive particles by atomic layer deposition. A memory cell material, a method of forming a semiconductor device structure, and a semiconductor device structure are also described.

Abstract: Multilayer dielectric structures are provided with graded composition. For example, a multilayer dielectric structure includes a stack of dielectric films, wherein the dielectric films include at least a first SiCNO (silicon carbon nitride oxide) film and a second SiCNO film. The first SiCNO film has a first composition profile of C, N, and O atoms. The second SiCNO film has a second composition profile of C, N, and O atoms, which is different from the first composition profile of C, N, and O atoms. The composition profiles of C, N and/or O atoms of the constituent dielectric films of the multilayer dielectric structure are customized to enhance or otherwise optimize one or more electrical and/or physical properties of the multilayer dielectric structure.

Abstract: A method of operating vertical heat treatment apparatus includes: cleaning interior of vertical reaction chamber by supplying cleaning gas; pre-coating the interior of the reaction chamber by performing, a plurality of times, a cycle including alternately supplying the first gas and supplying the second gas while generating plasma from the second gas; eliminating charges by loading substrate holding unit holding a dummy semiconductor substrate or a conductive substrate into the reaction chamber and supplying the second gas while generating plasma from the second gas without supplying the first gas; loading the substrate holding unit holding a plurality of product semiconductor substrates into the reaction chamber; and forming thin film in the reaction chamber by performing, a plurality of times, a cycle including alternately supplying the first gas and supplying the second gas while generating plasma from the second gas.

Abstract: A nonvolatile semiconductor memory according to an embodiment includes: a semiconductor region; a first insulating film formed on the semiconductor region; a charge storage film formed on the first insulating film; a hydrogen diffusion preventing film formed on the charge storage film; a second insulating film formed on the hydrogen diffusion preventing film; a control gate electrode formed on the second insulating film; a hydrogen discharge film formed on the control gate electrode; and a sidewall formed on a side surface of a multilayer structure including the first insulating film, the charge storage film, the hydrogen diffusion preventing film, the second insulating film, and the control gate electrode, the sidewall containing a material for preventing hydrogen from diffusing.

Abstract: A method of creating a virtual relaxed substrate includes providing a bulk semiconductor substrate, and creating a layer of strained semiconductor material on the substrate, a non-zero lattice mismatch of less than about 2% being present between the substrate and the layer of strained semiconductor material, and the layer of strained semiconductor material having a thickness of from about 50 nm to about 150 nm. The method further includes etching through the layer of strained semiconductor material and into the substrate to create shaped pillars separated by slits and sized to achieve edge effect relaxation throughout each shaped pillar, merging a top portion of the pillars with single crystal growth of epitaxial material to create a continuous surface while substantially maintaining the slits, and creating a virtual relaxed substrate by creating a layer of epitaxial composite semiconductor material over the continuous surface.

Abstract: Some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a substrate, a high k dielectric layer disposed over the substrate, and a gate layer over the high k dielectric layer. The high k dielectric layer is partially crystallized and comprising an average thickness of from about 10 ? to about 30 ?. Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. The method includes (i) forming a high k dielectric layer with a thickness of from about 10 ? to about 30 ? over a substrate, (ii) forming a gate layer over the dielectric layer, and (iii) transforming at least a portion of the dielectric layer from a first phase to a second phase by microwave irradiation.

Abstract: Provided are a deposition apparatus and a method of manufacturing a semiconductor device. In the method, a reaction chamber provided with a gaseous source supply unit and a liquid source supply unit is prepared, and an etch stop layer is formed on a substrate by using a gaseous source. Then, an interlayer insulation layer is formed on the etch stop layer by using a vaporized liquid source and a vaporized dopant source. In this way, the etch stop layer and the interlayer insulation layer are formed in-situ in the same reaction chamber.

Abstract: Provided are silacyclopropane-based compounds and methods of making the same. Also provided are methods of using said compounds in film deposition processes to deposit films comprising silicon. Certain methods comprise exposing a substrate surface to a silacyclopropane-based precursor and a co-reagent in various combinations.

Abstract: A crystal growth apparatus comprises a reaction vessel holding a melt mixture containing an alkali metal and a group III metal, a gas supplying apparatus supplying a nitrogen source gas to a vessel space exposed to the melt mixture inside the reaction vessel, a heating unit heating the melt mixture to a crystal growth temperature, and a support unit supporting a seed crystal of a group III nitride crystal inside the melt mixture.

Abstract: Embodiments of the disclosure generally provide methods of forming a hydrogen free silicon containing layer in TFT devices. The hydrogen free silicon containing layer may be used as a passivation layer, a gate dielectric layer, an etch stop layer, or other suitable layers in TFT devices, photodiodes, semiconductor diode, light-emitting diode (LED), or organic light-emitting diode (OLED), or other suitable display applications. In one embodiment, a method for forming a hydrogen free silicon containing layer in a thin film transistor includes supplying a gas mixture comprising a hydrogen free silicon containing gas and a reacting gas into a plasma enhanced chemical vapor deposition chamber, wherein the hydrogen free silicon containing gas is selected from a group consisting of SiF4, SiCl4, Si2Cl6, and forming a hydrogen free silicon containing layer on the substrate in the presence of the gas mixture.

Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.

Abstract: A method for forming a conformal, homogeneous dielectric film includes: forming a conformal dielectric film in trenches and/or holes of a substrate by cyclic deposition using a gas containing a silicon and a carbon, nitrogen, halogen, hydrogen, and/or oxygen, in the absence of a porogen gas; and heat-treating the conformal dielectric film and continuing the heat-treatment beyond a point where substantially all unwanted carbons are removed from the film and further continuing the heat-treatment to render substantially homogeneous film properties of a portion of the film deposited on side walls of the trenches and/or holes and a portion of the film deposited on top and bottom surfaces of the trenches and/or holes.

Abstract: A method of forming a material layer on a substrate is provided. The method is based on a combination of an overheating before deposition and a cooling of the reaction chamber during a second deposition stage. The second deposition stage follows a first deposition stage preferably carried out at a predetermined temperature. This combination makes it possible to compensate for the reactant gas depletion across wafer throughout the whole deposition process. The method can be conveniently used when growing a nitride layer to be used as a hard mask during shallow trench isolation (STI) region formation.

Abstract: A thin film transistor in which deterioration at initial operation is not likely to be caused and a manufacturing method thereof. A transistor which includes a gate insulating layer at least whose uppermost surface is a silicon nitride layer, a semiconductor layer over the gate insulating layer, and a buffer layer over the semiconductor layer and in which the concentration of nitrogen in the vicinity of an interface between the semiconductor layer and the gate insulating layer, which is in the semiconductor layer is lower than that of the buffer layer and other parts of the semiconductor layer. Such a thin film transistor can be manufactured by exposing the gate insulating layer to an air atmosphere and performing plasma treatment on the gate insulating layer before the semiconductor layer is formed.

Abstract: A method for forming a layer constituted by repeated stacked layers includes: forming a first layer and a second layer on a substrate under different deposition conditions to form a stacked layer, wherein the film stresses of the first and second layers are tensile or compressive and opposite to each other, and the wet etch rates of the first and second layers are at least 50 times different from each other; and repeating the above step to form a layer constituted by repeated stacked layers, wherein the deposition conditions for forming at least one stacked layer are different from those for forming another stacked layer.

Abstract: There is provided a method for manufacturing a semiconductor device, including forming an insulating film having a prescribed composition and a prescribed film thickness on a substrate by alternately performing the following steps prescribed number of times: supplying one of the sources of a chlorosilane-based source and an aminosilane-based source to a substrate in a processing chamber, and thereafter supplying the other source, to form a first layer containing silicon, nitrogen, and carbon on the substrate; and supplying a reactive gas different from each of the sources, to the substrate in the processing chamber, to modify the first layer and form a second layer.

Abstract: A silicon carbide semiconductor device having excellent electrical characteristics including channel mobility and a method for manufacturing the same are provided. The method for manufacturing a silicon carbide semiconductor device includes: an epitaxial layer forming step of preparing a semiconductor film of silicon carbide; a gate insulating film forming step of forming an oxide film on a surface of the semiconductor film; a nitrogen annealing step of performing heat treatment on the semiconductor film on which the oxide film is formed, in a nitrogen-containing atmosphere; and a post heat treatment step of performing, after the nitrogen annealing step, post heat treatment on the semiconductor film on which the oxide film is formed, in an atmosphere containing an inert gas. The heat treatment temperature in the post heat treatment step is higher than that in the nitrogen annealing step and lower than a melting point of the oxide film.

Abstract: Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B,C films with desirable properties, such as conformality and etch rate, are provided. One or more boron and/or carbon containing precursors can be decomposed on a substrate at a temperature of less than about 400° C. In some embodiments methods of depositing silicon nitride films comprising B and C are provided. A silicon nitride film can be deposited by a deposition process including an ALD cycle that forms SiN and a CVD cycle that contributes B and C to the growing film.

Abstract: Provided is a method of forming a silicon nitride film on a surface to be processed of a target object, which includes: repeating a first process a first predetermined number of times, the process including supplying a silicon source gas containing silicon toward the surface to be processed and supplying a decomposition accelerating gas containing a material for accelerating decomposition of the silicon source gas toward the surface to be processed; performing a second process of supplying a nitriding gas containing nitrogen toward the surface to be processed a second predetermine number of times; and performing one cycle a third predetermined number of times, the one cycle being a sequence including the repetition of the first process and the performance of the second process to form the silicon nitride film on the surface to be processed.

Abstract: A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies.