Silicon Nitride Formation Patents (Class 438/791)
  • Patent number: 8999863
    Abstract: A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: April 7, 2015
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Jae Gon Lee, Jingze Tian, Shyue Seng Tan, Luona Goh, Wei Lu, Elgin Quek
  • Patent number: 8999847
    Abstract: Embodiments of the present invention provide methods for depositing a nitrogen-containing material on large-sized substrates disposed in a processing chamber. In one embodiment, a method includes processing a batch of substrates within a processing chamber to deposit a nitrogen-containing material on a substrate from the batch of substrates, and performing a seasoning process at predetermined intervals during processing the batch of substrates to deposit a conductive seasoning layer over a surface of a chamber component disposed in the processing chamber. The chamber component may include a gas distribution plate fabricated from a bare aluminum without anodizing. In one example, the conductive seasoning layer may include amorphous silicon, doped amorphous silicon, doped silicon, doped polysilicon, doped silicon carbide, or the like.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: April 7, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Gaku Furuta, Soo Young Choi, Beom Soo Park, Young-jin Choi, Omori Kenji
  • Patent number: 8981466
    Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
  • Publication number: 20150050817
    Abstract: A superjunction semiconductor device is provided having at least one column of a first conductivity type and at least one column of a second conductivity type extending from a first main surface of a semiconductor substrate toward a second main surface of the semiconductor substrate opposed to the first main surface. The at least one column of the second conductivity type has a first sidewall surface proximate the at least one column of the first conductivity type and a second sidewall surface opposed to the first sidewall surface. A termination structure is proximate the second sidewall surface of the at least one column of the second conductivity type. The termination structure includes a layer of dielectric of an effective thickness and consumes about 0% of the surface area of the first main surface. Methods for manufacturing superjunction semiconductor devices and for preventing surface breakdown are also provided.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 19, 2015
    Inventor: Xu CHENG
  • Publication number: 20150050818
    Abstract: Disclosed is a substrate processing apparatus, including: a processing chamber for processing a substrate; a substrate rotating mechanism for rotating the substrate; a gas supply unit for supplying gas to the substrate, at least two kinds of gases A and B being alternately supplied a plurality of times to form a desired film on the substrate; and a controller for controlling a rotation period of the substrate or a gas supply period defined as a time period between an instant when the gas A is made to flow and an instant when the gas A is made to flow next time such that the rotation period and the gas supply period are not brought into synchronization with each other at least while the alternate gas supply is carried out predetermined times.
    Type: Application
    Filed: October 31, 2014
    Publication date: February 19, 2015
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Masanori SAKAI, Tomohiro YOSHIMURA
  • Patent number: 8956984
    Abstract: Provided is a method of manufacturing a semiconductor device capable of forming a nitride layer having high resistance to hydrogen fluoride at low temperatures. The method includes forming a nitride film on a substrate by performing a cycle a predetermined number of times, the cycle including supplying a source gas to the substrate, supplying a plasma-excited hydrogen-containing gas to the substrate, supplying a plasma-excited or thermally excited nitriding gas to the substrate, and supplying at least one of a plasma-excited nitrogen gas and a plasma-excited rare gas to the substrate.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: February 17, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Kazuyuki Okuda
  • Patent number: 8940615
    Abstract: The present invention provides a method of forming an isolation structure. A substrate is provided, and a trench is formed in the substrate. Next, a semiconductor layer is formed on a surface of the trench. A nitridation is carried out to form a nitridation layer in the semiconductor layer. Lastly, an insulation layer is filled into the trench.
    Type: Grant
    Filed: September 9, 2012
    Date of Patent: January 27, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Te-Lin Sun, Chien-Liang Lin, Yu-Ren Wang
  • Patent number: 8940586
    Abstract: The present disclosure relates to a bump processing method and/or resulting MEMS-CMOS structure, in which one or more anti-stiction bumps are formed within a substrate prior to the formation of a cavity in which the one or more anti-stiction bumps reside. By forming the one or more anti-stiction bumps prior to a cavity, the sidewall angle and the top critical dimension (i.e., surface area) of the one or more anti-stiction bumps are reduced. The reduction in sidewall angle and critical dimension reduces stiction between a substrate and a moveable part of a MEMS device. By reducing the size of the anti-stiction bumps through a processing sequence change, lithographic problems such as reduction of the lithographic processing window and bump photoresist collapse are avoided.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chris Kuo, Lee-Chuan Tseng
  • Patent number: 8937369
    Abstract: A transistor includes a semiconductor substrate, at least a gate structure, at least a first tensile stress layer, a second tensile stress layer, a source region, and a drain region. The gate structure is disposed within a first transistor region of the semiconductor substrate. The first tensile stress layer includes a curved portion encompassing the gate structure, at least an extension portion with a curved top surface located on the semiconductor substrate at sides of the gate structure, and a transition portion between the curved portion and the extension portion. The first tensile stress layer has a thickness gradually thinning from the curved portion and the extension portion toward the transition portion. The second tensile stress layer is disposed on the first tensile stress layer. And the source/drain regions are separately located in the semiconductor substrate on two sides of the gate structure.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: January 20, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Yu-Shu Lin, Jei-Ming Chen, Wen-Yi Teng
  • Patent number: 8906455
    Abstract: This invention discloses the method of forming silicon nitride, silicon oxynitride, silicon oxide, carbon-doped silicon nitride, carbon-doped silicon oxide and carbon-doped oxynitride films at low deposition temperatures. The silicon containing precursors used for the deposition are monochlorosilane (MCS) and monochloroalkylsilanes. The method is preferably carried out by using plasma enhanced atomic layer deposition, plasma enhanced chemical vapor deposition, and plasma enhanced cyclic chemical vapor deposition.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: December 9, 2014
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Liu Yang, Xinjian Lei, Bing Han, Manchao Xiao, Eugene Joseph Karwacki, Jr., Hansong Cheng
  • Patent number: 8895455
    Abstract: To form an insulating film with extremely low concentration of impurities such as carbon, hydrogen, nitrogen, chlorine, etc in a film. There are provided the steps of forming a specific element-containing layer on a substrate by supplying source gas containing a specific element into a processing container in which the substrate is accommodated; changing the specific element-containing layer into a nitride layer, by activating and supplying gas containing nitrogen into the processing container; and changing the nitride layer into an oxide layer or an oxynitride layer, by activating and supplying gas containing oxygen into the processing container; with this cycle set as one cycle and performed for at least one or more times.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: November 25, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Naonori Akae, Yoshiro Hirose
  • Patent number: 8895457
    Abstract: To provide a method of manufacturing a semiconductor device, including: forming a thin film different from a silicon oxide film on a substrate by supplying a processing gas into a processing vessel in which the substrate is housed; removing a deposit including the thin film adhered to an inside of the processing vessel by supplying a fluorine-containing gas into the processing vessel after executing forming the thin film prescribed number of times; and forming a silicon oxide film having a prescribed film thickness on the inside of the processing vessel by alternately supplying a silicon-containing gas, and an oxygen-containing gas and a hydrogen-containing gas into the heated processing vessel in which a pressure is set to be less than an atmospheric pressure after removing the deposit.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: November 25, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Naonori Akae, Kotaro Murakami, Yoshiro Hirose, Kenji Kameda
  • Publication number: 20140339497
    Abstract: Fluorescent semiconductor nanocrystals and quantum dots having an inorganic coating on the outermost surface of the nanocrystal are described herein as well as methods for preparing and using such nanocrystals and quantum dots. Devices in which such nanocrystals and quantum dots are used are also described.
    Type: Application
    Filed: June 20, 2012
    Publication date: November 20, 2014
    Applicant: CRYSTALPLEX CORPORATION
    Inventors: Lianhua Qu, Matthew W. Bootman
  • Patent number: 8889568
    Abstract: Disclosed are: a method for producing a silicon nitride film, wherein generation of blisters at the periphery of a substrate is suppressed when a silicon nitride film is formed through application of a bias power; and an apparatus for producing a silicon nitride film. Specifically disclosed are a method and apparatus for producing a silicon nitride film, wherein a silicon nitride film used for a semiconductor element is formed on a substrate by plasma processing. In the method and apparatus for producing a silicon nitride film, a bias is applied to the substrate at time (b1), and a starting material gas SiH4 for the silicon nitride film is started to be supplied at time (b3) after the application of the bias.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: November 18, 2014
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Seiji Nishikawa, Hidetaka Kafuku, Tadashi Shimazu
  • Patent number: 8883624
    Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: November 11, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventor: Krishnaswamy Ramkumar
  • Patent number: 8871656
    Abstract: Methods of depositing initially flowable dielectric films on substrates are described. The methods include introducing silicon-containing precursor to a deposition chamber that contains the substrate. The methods further include generating at least one excited precursor, such as radical nitrogen or oxygen precursor, with a remote plasma system located outside the deposition chamber. The excited precursor is also introduced to the deposition chamber, where it reacts with the silicon-containing precursor in a reaction zone deposits the initially flowable film on the substrate. The flowable film may be treated in, for example, a steam environment to form a silicon oxide film.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: October 28, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Abhijit Basu Mallick, Nitin K. Ingle
  • Publication number: 20140315393
    Abstract: A method of manufacturing a semiconductor device includes: pre-treating a surface of a substrate by supplying an oxygen-containing gas and a hydrogen-containing gas to the substrate heated in a process chamber under a pressure less than atmospheric pressure; and forming a film on the pre-treated substrate by performing a cycle a predetermined number of times. The cycle includes: supplying a precursor gas to the substrate in the process chamber; and supplying a reaction gas to the substrate in the process chamber.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 23, 2014
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Takashi OZAKI, Hideki HORITA
  • Patent number: 8846536
    Abstract: Provided herein are integration-compatible dielectric films and methods of depositing and modifying them. According to various embodiments, the methods can include deposition of flowable dielectric films targeting specific film properties and/or modification of those properties with an integration-compatible treatment process. In certain embodiments, methods of depositing and modifying flowable dielectric films having tunable wet etch rates and other properties are provided. Wet etch rates can be tuned during integration through am integration-compatible treatment process. Examples of treatment processes include plasma exposure and ultraviolet radiation exposure.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: September 30, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Nerissa Draeger, Karena Shannon, Bart van Schravendijk, Kaihan Ashtiani
  • Patent number: 8835240
    Abstract: A method for fabricating a semiconductor device is provided, wherein the method comprises steps as follows: A first conductive-type metal-oxide-semiconductor transistor and a second conductive-type metal-oxide-semiconductor transistor are firstly formed on a substrate. Subsequently, a first stress-inducing dielectric layer and a first capping layer are formed in sequence on the first conductive-type metal-oxide-semiconductor transistor; and then a second stress-inducing dielectric layer and a second capping layer are formed in sequence on the second conductive-type metal-oxide-semiconductor transistor. Next, the fist capping layer is removed.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: September 16, 2014
    Assignee: United Microelectronics Corporation
    Inventors: An-Chi Liu, Chih-Wen Teng, Tzu-Yu Tseng, Chi-Heng Lin
  • Publication number: 20140252427
    Abstract: Embodiments of the invention include methods of forming gate caps. Embodiments may include providing a semiconductor device including a gate on a semiconductor substrate and a source/drain region on the semiconductor substrate adjacent to the gate, forming a blocking region, a top surface of which extends above a top surface of the gate, depositing an insulating layer above the semiconductor device, and planarizing the insulating layer using the blocking region as a planarization stop. Embodiments further include semiconductor devices having a semiconductor substrate, a gate above the semiconductor substrate, a source/drain region adjacent to the gate, a gate cap above the gate that cover the full width of the gate, and a contact adjacent to the source/drain region having a portion of its sidewall defined by the gate cap.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan, Thomas N. Adam
  • Patent number: 8809207
    Abstract: A pattern-forming method for forming a predetermined pattern serving as a mask when etching film on a substrate includes the steps of: an organic film pattern-forming step for forming an organic film pattern on a film to be processed; forming a silicon nitride film on the organic film pattern; etching the silicon nitride film so that the silicon nitride film remains only on the lateral wall sections of the organic film pattern; and removing the organic film, thereby forming the predetermined silicon nitride film pattern on the film to be processed on a substrate. With the temperature of the substrate maintained at no more than 100° C., the film-forming step excites a processings gas and generates a plasma, performs plasma processing with the plasma, and forms a silicon nitride film having stress of no more than 100 MPa.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: August 19, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Hiraku Ishikawa, Teruyuki Hayashi, Takaaki Matsuoka, Yuji Ono
  • Patent number: 8809202
    Abstract: Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a protective material over a bottom surface and edges of the workpiece. A top surface of the workpiece is processed. The protective material protects the edges and the bottom surface of the workpiece during the processing of the top surface of the workpiece.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hui Weng, Wei-Sheng Yun, Shao-Ming Yu, Hsin-Chih Chen, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8791034
    Abstract: A chemical vapor deposition method for forming an aluminum-silicon nitride layer upon a substrate uses an aluminum precursor, a silicon precursor and a nitrogen precursor under chemical vapor deposition conditions to deposit the aluminum-silicon nitride layer upon the substrate. The aluminum-silicon nitride layer has an index of refraction interposed between silicon nitride and aluminum nitride. The aluminum-silicon nitride layer also has a bandgap from about 4.5 to about 6 eV and a permittivity from about 6×10^-11 to about 8×10^-11 F/m. The aluminum-silicon nitride layer may be further thermally annealed to reduce a hydrogen content of the aluminum-silicon nitride layer.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: July 29, 2014
    Assignee: Cornell University
    Inventors: James R. Shealy, Richard Brown
  • Patent number: 8785312
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8765617
    Abstract: A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon nitride on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including a nitrogen atom.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Electric Industries, Inc.
    Inventor: Takeyoshi Masuda
  • Patent number: 8759232
    Abstract: The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an adhesion layer in a plasma-free process atmosphere, thereby enabling a reduced thickness of the adhesion layer and a higher internal stress level of the subsequent top layer.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: June 24, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Joerg Hohage, Hartmut Ruelke, Ralf Richter
  • Patent number: 8753989
    Abstract: High tensile stress in a deposited layer, such as a silicon nitride layer, may be achieved utilizing one or more techniques employed either alone or in combination. In one embodiment, a silicon nitride film having high tensile stress may be formed by depositing the silicon nitride film in the presence of a porogen. The deposited silicon nitride film may be exposed to at least one treatment selected from a plasma or ultraviolet radiation to liberate the porogen. The silicon nitride film may be densified such that a pore resulting from liberation of the porogen is reduced in size, and Si—N bonds in the silicon nitride film are strained to impart a tensile stress in the silicon nitride film. In another embodiment, tensile stress in a silicon nitride film may be enhanced by depositing a silicon nitride film in the presence of a nitrogen-containing plasma at a temperature of less than about 400° C., and exposing the deposited silicon nitride film to ultraviolet radiation.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: June 17, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Mihaela Balseanu, Michael S. Cox, Li-Qun Xia, Mei-Yee Shek, Jia Lee, Vladimir Zubkov, Tzu-Fang Huang, Rongping Wang, Isabelita Roflox, Hichem M'Saad
  • Publication number: 20140141625
    Abstract: A method of forming an insulation film on a semiconductor substrate by plasma enhanced atomic layer deposition (PEALD), includes: (i) adsorbing a non-excited non-halide precursor having four or more silicon atoms in its molecule onto a substrate placed in a reaction space; (ii) supplying an oxygen-free reactant to the reaction space without applying RF power so as to expose the precursor-adsorbed substrate to the reactant; and (iii) after step (ii), applying RF power to the reaction space while the oxygen-free reactant is supplied in the reaction space; and (iv) repeating steps (i) to (iii) as a cycle, thereby depositing an insulation film on the substrate.
    Type: Application
    Filed: November 16, 2012
    Publication date: May 22, 2014
    Applicant: ASM IP HOLDING B.V.
    Inventors: Atsuki Fukazawa, Hideaki Fukuda
  • Patent number: 8728955
    Abstract: A method of depositing a film on a substrate surface includes providing a substrate in a reaction chamber; selecting a silicon-containing reactant from a precursor group consisting of di-tert-butyl diazidosilane, bis(ethylmethylamido)silane, bis(diisopropylamino)silane, bis(tert-butylhydrazido)diethylsilane, tris(dimethylamido)silylazide, tris(dimethylamido)silylamide, ethylsilicon triazide, diisopropylaminosilane, and hexakis(dimethylamido)disilazane; introducing the silicon-containing reactant in vapor phase into the reaction chamber under conditions allowing the silicon-containing reactant to adsorb onto the substrate surface; introducing a second reactant in vapor phase into the reaction chamber while the silicon-containing reactant is adsorbed on the substrate surface, and wherein the second reactant is introduced without first sweeping the silicon-containing reactant out of the reaction chamber; and exposing the substrate surface to plasma to drive a reaction between the silicon-containing reactant and
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: May 20, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Adrien LaVoie, Mark J. Saly, Daniel Moser, Rajesh Odedra, Ravi Konjolia
  • Patent number: 8728956
    Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: May 20, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Adrien LaVoie, Shankar Swaminathan, Hu Kang, Ramesh Chandrasekharan, Tom Dorsh, Dennis M. Hausmann, Jon Henri, Thomas Jewell, Ming Li, Bryan Schlief, Antonio Xavier, Thomas W. Mountsier, Bart J. van Schravendijk, Easwar Srinivasan, Mandyam Sriram
  • Patent number: 8722549
    Abstract: A method of fabricating a semiconductor device having reduced plasma-induced damage includes providing a p-type semiconductor substrate. The p-type semiconductor substrate has a front surface including the semiconductor device and a back surface. The method further includes doping the back surface with an n-type dopant to form an n-type semiconductor region before forming metal interconnections on the front surface. The n-type semiconductor region and the p-type semiconductor substrate form a pn junction. The method also includes forming an insulation layer on an exposed surface of the n-type semiconductor region.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: May 13, 2014
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Ming Zhou
  • Patent number: 8716155
    Abstract: Methods of improving charge trapping are disclosed. One such method includes forming an oxide-nitride-oxide tunnel stack and a silicon nitride layer on the oxide-nitride-oxide tunnel stack. This silicon nitride layer is implanted with ions. These ions may function as electron traps or as fields. The silicon nitride layer may be part of a flash memory device.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 6, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Deepak A. Ramappa, Kyu-Ha Shim
  • Publication number: 20140106577
    Abstract: Provided is a method of forming a silicon nitride film on an object to be processed, which includes: supplying a silicon raw material gas into a processing chamber; and supplying a nitridant gas into the processing chamber, wherein supplying the silicon raw material gas includes an initial supply stage in which the silicon raw material gas is initially supplied and a late supply stage following the initial supply stage, wherein a first internal pressure of the processing chamber defined in the initial supply stage is lower than a second internal pressure of the processing chamber defined in the late supply stage.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 17, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Yamato TONEGAWA, Keiji TABUKI
  • Patent number: 8679989
    Abstract: A method of manufacturing a semiconductor device has: carrying a substrate into a process chamber; depositing a thin film on the substrate by supplying inside the process chamber a first film deposition gas including at least one element among plural elements forming a thin film to be deposited and capable of accumulating a film solely and a second film deposition gas including at least another element among the plural elements and incapable of accumulating a film solely; carrying the substrate on which is deposited the thin film out from inside the process chamber; and removing a first sediment adhering to an interior of the process chamber and a second sediment adhering to an interior of the supply portion and having a chemical composition different from a chemical composition of the first sediment by supplying cleaning gases inside the process chamber and inside a supply portion that supplies the first film deposition gas while changing at least one of a supply flow rate, a concentration, and a type betwee
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: March 25, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Sadao Nakashima, Takahiro Maeda, Kiyohiko Maeda, Kenji Kameda, Yushin Takasawa
  • Patent number: 8669185
    Abstract: A method of tailoring conformality of a film deposited on a patterned surface includes: (I) depositing a film by PEALD or pulsed PECVD on the patterned surface; (II) etching the film, wherein the etching is conducted in a pulse or pulses, wherein a ratio of an etching rate of the film on a top surface and that of the film on side walls of the patterns is controlled as a function of the etching pulse duration and the number of etching pulses to increase a conformality of the film; and (III) repeating (I) and (II) to satisfy a target film thickness.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: March 11, 2014
    Assignee: ASM Japan K.K.
    Inventors: Shigeyuki Onizawa, Woo-Jin Lee, Hideaki Fukuda, Kunitoshi Namba
  • Patent number: 8659020
    Abstract: It is an object to provide an epitaxial silicon wafer that is provided with an excellent gettering ability in which a polysilicon layer is formed on the rear face side of a silicon crystal substrate into which phosphorus (P) and germanium (Ge) have been doped. A silicon epitaxial layer is grown by a CVD method on the surface of a silicon crystal substrate into which phosphorus and germanium have been doped at a high concentration. After that, a PBS forming step for growing a polysilicon layer is executed on the rear face side of a silicon crystal substrate. By the above steps, the number of LPDs (caused by an SF) that occur on the surface of the epitaxial silicon wafer due to the SF can be greatly reduced.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: February 25, 2014
    Assignee: Sumco Corporation
    Inventors: Tadashi Kawashima, Masahiro Yoshikawa, Akira Inoue, Yoshiya Yoshida
  • Publication number: 20140051264
    Abstract: Methods of depositing initially flowable dielectric films on substrates are described. The methods include introducing silicon-containing precursor to a deposition chamber that contains the substrate. The methods further include generating at least one excited precursor, such as radical nitrogen or oxygen precursor, with a remote plasma system located outside the deposition chamber. The excited precursor is also introduced to the deposition chamber, where it reacts with the silicon-containing precursor in a reaction zone deposits the initially flowable film on the substrate. The flowable film may be treated in, for example, a steam environment to form a silicon oxide film.
    Type: Application
    Filed: February 12, 2013
    Publication date: February 20, 2014
    Applicant: Applied Materials, Inc.
    Inventors: Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 8647993
    Abstract: Described are methods of making silicon nitride (SiN) materials and other silicon-containing films, including carbon-containing and/or oxygen-containing films such as SiCN (also referred to as SiNC), SiON and SiONC films, on substrates. According to various embodiments, the methods involve electromagnetic radiation-assisted activation of one or more reactants. In certain embodiments, for example, the methods involve ultraviolet (UV) activation of vapor phase amine coreactants. The methods can be used to deposit silicon-containing films, including SiN and SiCN films, at temperatures below about 400° C.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: February 11, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Adrien LaVoie, Bhadri Varadarajan, Jon Henri, Dennis Hausmann
  • Patent number: 8637362
    Abstract: A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: January 28, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Publication number: 20140015060
    Abstract: A method for fabricating a stress enhanced CMOS circuit includes forming a first plurality of MOS transistors at a first pitch and forming a second plurality of MOS transistors at a second pitch. The second pitch is larger than the first pitch. The method further includes depositing a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner deposited in the fabrication of the stress enhanced CMOS circuit. A stress enhanced CMOS circuit includes a first plurality of MOS transistors formed at a first pitch and a second plurality of MOS transistors formed at a second pitch. The second pitch is larger than the first pitch. The circuit further includes a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner formed on the stress enhanced CMOS circuit.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 16, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stefan Flachowsky, Jan Hoentschel
  • Publication number: 20140017908
    Abstract: A method for forming a conformal, homogeneous dielectric film includes: forming a conformal dielectric film in trenches and/or holes of a substrate by cyclic deposition using a gas containing a silicon and a carbon, nitrogen, halogen, hydrogen, and/or oxygen, in the absence of a porogen gas; and heat-treating the conformal dielectric film and continuing the heat-treatment beyond a point where substantially all unwanted carbons are removed from the film and further continuing the heat-treatment to render substantially homogeneous film properties of a portion of the film deposited on side walls of the trenches and/or holes and a portion of the film deposited on top and bottom surfaces of the trenches and/or holes.
    Type: Application
    Filed: June 20, 2013
    Publication date: January 16, 2014
    Inventors: Julien Beynet, Ivo Raaijmakers, Atsuki Fukazawa
  • Patent number: 8629067
    Abstract: Methods of forming dielectric layers are described. The method may include the steps of mixing a silicon-containing precursor with a radical-nitrogen precursor, and depositing a dielectric layer on a substrate. The radical-nitrogen precursor is formed in a remote plasma by flowing hydrogen (H2) and nitrogen (N2) into the plasma in order to allow adjustment of the nitrogen/hydrogen ratio. The dielectric layer is initially a silicon-and-nitrogen-containing layer which may be converted to a silicon-and-oxygen-containing layer by curing and/or annealing the film in an oxygen-containing environment.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: January 14, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jingmei Liang, Xiaolin Chen, Matthew L. Miller, Nitin K. Ingle, Shankar Venkataraman
  • Patent number: 8609551
    Abstract: To form an insulating film with extremely low concentration of impurities such as carbon, hydrogen, nitrogen, chlorine, etc in a film. There are provided the steps of forming a specific element-containing layer on a substrate by supplying source gas containing a specific element into a processing container in which the substrate is accommodated; changing the specific element-containing layer into a nitride layer, by activating and supplying gas containing nitrogen into the processing container; and changing the nitride layer into an oxide layer or an oxynitride layer, by activating and supplying gas containing oxygen into the processing container; with this cycle set as one cycle and performed for at least one or more times.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: December 17, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Naonori Akae, Yoshiro Hirose
  • Patent number: 8609556
    Abstract: Assembly and method for depositing a thin film including: providing an expanding thermal plasma plume, including at least one chemical component to be deposited; designating a first and a second deposition zone within the plasma plume, such that the first and second deposition zones have a mutually different relative content of the chemical component; providing a substrate, and transporting said substrate through the plasma plume along a substrate transport path having a substrate transport path direction; and providing a mask that is at least partly disposed in the plasma plume and that shields a portion of the substrate transport path from being deposited on, wherein said shielded portion of the substrate transport path extends in the direction of the substrate transport path and bridges at least the first deposition zone, while it starts or terminates in the second deposition zone.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: December 17, 2013
    Assignee: OTB Solar B.V.
    Inventors: Björn Van Gerwen, Roland Cornelis Maria Bosch, Franciscus Cornelius Dings
  • Patent number: 8610182
    Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: December 17, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiko Hayakawa, Mitsunori Sakama, Satoshi Toriumi
  • Patent number: 8586487
    Abstract: Methods and apparatus for forming conformal silicon nitride films at low temperatures on a substrate are provided. The methods of forming a silicon nitride layer include performing a deposition cycle including flowing a processing gas mixture into a processing chamber having a substrate therein, wherein the processing gas mixture comprises precursor gas molecules having labile silicon to nitrogen, silicon to carbon, or nitrogen to carbon bonds, activating the precursor gas at a temperature between about 20° C. to about 480° C. by preferentially breaking labile bonds to provide one or more reaction sites along a precursor gas molecule, forming a precursor material layer on the substrate, wherein the activated precursor gas molecules bond with a surface on the substrate at the one or more reaction sites, and performing a plasma treatment process on the precursor material layer to form a conformal silicon nitride layer.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: November 19, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Victor Nguyen, Mihaela Balseanu, Li-Qun Xia, Derek R. Witty
  • Patent number: 8569186
    Abstract: A plasma processing apparatus generates plasma by introducing microwaves into a processing chamber by using a planar antenna having a plurality of slots. By using the plasma processing apparatus, a nitrogen containing gas and a silicon containing gas introduced into the processing chamber are brought into the plasma state, and at the time of depositing by using the plasma a silicon nitride film on the surface of the a substrate to be processed, stress to the silicon nitride film to be formed is controlled by the combination of the type and the processing pressure of the nitrogen containing gas.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: October 29, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Masayuki Kohno, Tatsuo Nishita, Toshio Nakanishi
  • Patent number: 8557716
    Abstract: A thin film can be formed on a substrate at a low temperature with a practicable film-forming rate. There is provided a semiconductor device manufacturing method for forming an oxide or nitride film on a substrate. The method comprises: exposing the substrate to a source gas; exposing the substrate to a modification gas comprising an oxidizing gas or a nitriding gas, wherein an atom has electronegativity different from that of another atom in molecules of the oxidizing gas or the nitriding gas; and exposing the substrate to a catalyst. The catalyst has acid dissociation constant pKa in a range from 5 to 7, but a pyridine is not used as the catalyst.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: October 15, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Norikazu Mizuno
  • Patent number: 8557719
    Abstract: A method for fabricating a semiconductor device, according to the present invention includes the steps of: preparing an SOI substrate, which comprises a semiconductor supporting layer, an oxide layer formed on the semiconductor supporting layer and an SOI layer formed on the oxide layer; forming a semiconductor device on the SOI layer; forming a passivation layer over the SOI substrate, the passivation layer allowing a UV light to pass through it; and applying a UV light to the SOI substrate after the step of forming the semiconductor device is completed.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: October 15, 2013
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventors: Wataru Shimizu, Ikuo Kurachi
  • Publication number: 20130260576
    Abstract: According to an embodiment of the present disclosure a method of forming a boron-containing silicon oxycarbonitride film on a base is provided. The method includes forming a boron-containing film on the base, and forming the boron-containing silicon oxycarbonitride film by laminating a silicon carbonitride film and a silicon oxynitride film on the boron-containing film.
    Type: Application
    Filed: March 18, 2013
    Publication date: October 3, 2013
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kentaro KADONAGA, Keisuke SUZUKI