Organic Reactant Patents (Class 438/793)
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Patent number: 7387971Abstract: A fabricating method for a flat panel display device having a thin film pattern over a substrate is disclosed. The fabricating method includes depositing a hydrophilic resin over a substrate and patterning the hydrophilic resin to form hydrophilic resin patterns over areas outside where thin film patterns are to be formed over the substrate. The fabricating method also includes depositing a hydrophobic nano powder thin film material over the substrate and between the hydrophilic resin patterns and removing the hydrophilic resin patterns to form hydrophobic nano powder thin film patterns over the substrate. Moreover, the fabricating method includes treating the hydrophobic nano powder thin film patterns to form the thin film pattern.Type: GrantFiled: October 28, 2005Date of Patent: June 17, 2008Assignee: LG.Philips LCD Co., Ltd.Inventors: Gee Sung Chae, Mi Kyung Park
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Patent number: 7365029Abstract: Embodiments of the invention generally provide a method for depositing a film containing silicon (Si) and nitrogen (N). In one embodiment, the method includes heating a substrate disposed in a processing chamber to a temperature less than about 650 degrees Celsius, flowing a nitrogen-containing gas into the processing chamber, flowing a silicon-containing gas into the processing chamber, and depositing a SiN-containing layer on a substrate. The silicon-containing gas is at least one of a gas identified as NR2—Si(R?2)—Si(R?2)—NR2 (amino(di)silanes), R3—Si—N?N?N (silyl azides), R?3—Si—NR—NR2 (silyl hydrazines) or 1,3,4,5,7,8-hexamethytetrasiliazane, wherein R and R? comprise at least one functional group selected from the group of a halogen, an organic group having one or more double bonds, an organic group having one or more triple bonds, an aliphatic alkyl group, a cyclical alkyl group, an aromatic group, an organosilicon group, an alkyamino group, or a cyclic group containing N or Si.Type: GrantFiled: June 14, 2005Date of Patent: April 29, 2008Assignee: Applied Materials, Inc.Inventors: R. Suryanarayanan Iyer, Sean M. Seutter, Sanjeev Tandon, Errol Antonio C. Sanchez, Shulin Wang
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Patent number: 7138068Abstract: A method is disclosed for fabricating a patterned embedded capacitance layer. The method includes fabricating (1305, 1310) a ceramic oxide layer (510) overlying a conductive metal layer (515) overlying a printed circuit substrate (505), perforating (1320) the ceramic oxide layer within a region (705), and removing (1325) the ceramic oxide layer and the conductive metal layer in the region by chemical etching of the conductive metal layer. The ceramic oxide layer may be less than 1 micron thick.Type: GrantFiled: March 21, 2005Date of Patent: November 21, 2006Assignee: Motorola, Inc.Inventors: Gregory J. Dunn, Robert T. Croswell, Jaroslaw A. Magera, Jovica Savic, Aroon V. Tungare
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Patent number: 7129187Abstract: A method for low-temperature plasma-enhanced chemical vapor deposition of a silicon-nitrogen-containing film on a substrate. The method includes providing a substrate in a process chamber, exciting a reactant gas in a remote plasma source, thereafter mixing the excited reactant gas with a silazane precursor gas, and depositing a silicon-nitrogen-containing film on the substrate from the excited gas mixture in a chemical vapor deposition process. In one embodiment of the invention, the reactant gas can contain a nitrogen-containing gas to deposit a SiCNH film. In another embodiment of the invention, the reactant gas can contain an oxygen-containing gas to deposit a SiCNOH film.Type: GrantFiled: July 14, 2004Date of Patent: October 31, 2006Assignee: Tokyo Electron LimitedInventor: Raymond Joe
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Patent number: 7098061Abstract: A method for forming an electronic device, comprising: forming a first conductive or semiconductive layer; forming a sequence of at least on insulating layer and at least one semiconducting layer over the first conductive or semiconductive layer; locally depositing solvents at a localised region of the insulating layer so as to dissolve the sequence of insulating and semiconducting layers in the region to leave a void extending through the sequence of layer; and depositing conductive or semiconductive material in the void.Type: GrantFiled: June 21, 2002Date of Patent: August 29, 2006Assignee: Plastic Logic LimitedInventors: Henning Sirringhaus, Richard Henry Friend, Takeo Kawase
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Patent number: 7067414Abstract: A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide-comprising inter-level dielectric layer including carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the dielectric layer, it is exposed to a plasma including oxygen effective to reduce the dielectric constant to below what it was prior to the exposing. A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least patially formed thereon. In a chamber, an inter-level dielectric layer including carbon and having a dielectric constant no greater than 3.5 is plasma-enhanced chemical vapor deposited over the substrate at subatmospheric pressure.Type: GrantFiled: March 27, 2000Date of Patent: June 27, 2006Assignee: Micron Technology, Inc.Inventors: Weimin Li, Zhiping Yin, William Budge
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Patent number: 7067415Abstract: A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide comprising interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is formed over the substrate. After forming the carbon comprising dielectric layer, it is exposed to a plasma comprising oxygen effective to reduce the dielectric constant to below what it was prior to said exposing. A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. In a chamber, an interlevel dielectric layer comprising carbon and having a dielectric constant no greater than 3.5 is plasma enhanced chemical vapor deposited over the substrate at subatmospheric pressure.Type: GrantFiled: July 25, 2002Date of Patent: June 27, 2006Assignee: Micron Technology, Inc.Inventors: Weimin Li, Zhiping Yin, William Budge
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Patent number: 7001844Abstract: Stress level of a nitride film is adjusted as a function of two or more of the following: identity of a starting material precursor used to make the nitride film; identity of a nitrogen-containing precursor with which is treated the starting material precursor; ratio of the starting material precursor to the nitrogen-containing precursor; a set of CVD conditions under which the film is grown; and/or a thickness to which the film is grown. A rapid thermal chemical vapor deposition (RTCVD) film produced by reacting a compound containing silicon, nitrogen and carbon (such as bis-tertiary butyl amino silane (BTBAS)) with NH3 can provide advantageous properties, such as high stress and excellent performance in an etch-stop application. An ammonia-treated BTBAS film is particularly excellent in providing a high-stress property, and further having maintainability of that high-stress property over repeated annealing.Type: GrantFiled: April 30, 2004Date of Patent: February 21, 2006Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Shreesh Narasimha, Victor Chan, Judson Holt, Satya N. Chakravarti
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Patent number: 6875709Abstract: A method and apparatus for curing and modifying a low k dielectric layer in an interconnect structure is disclosed. A spin-on low k dielectric layer which includes an organic silsesquioxane, polyarylether, bisbenzocyclobuene, or SiLK is spin coated on a substrate. The substrate is placed in a process chamber in a supercritical CO2 system and is treated at a temperature between 30° C. and 150° C. and at a pressure from 70 to 700 atmospheres. A co-solvent such as CF3—X or F—X is added that selectively replaces C—CH3 bonds with C—CF3 or C—F bonds. Alternatively, H2O2 is employed as co-solvent to replace a halogen in a C—Z bond where Z=F, Cl, or Br with an hydroxyl group. Two co-solvents may be combined with CO2 for more flexibility. The cured dielectric layer has improved properties that include better adhesion, lower k value, increased hardness, and a higher elastic modulus.Type: GrantFiled: March 7, 2003Date of Patent: April 5, 2005Assignee: Taiwan Semiconductor Manufacturing Comapny, Ltd.Inventors: Chun-Hsien Lin, Henry Lo, Anthony Liu, Yu-Liang Lin
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Patent number: 6849562Abstract: A method for depositing a low k dielectric film comprising silicon, carbon, and nitrogen is provided. The low k dielectric film is formed by a gas mixture comprising a silicon source, a carbon source, and NR1R2R3, wherein R1, R2, and R3 are selected from the group consisting of alkyl and phenyl groups. The low k dielectric film may be used as a barrier layer, an etch stop, an anti-reflective coating, or a hard mask.Type: GrantFiled: March 4, 2002Date of Patent: February 1, 2005Assignee: Applied Materials, Inc.Inventors: Chi-I Lang, Li-Qun Xia, Ping Xu, Louis Yang
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Patent number: 6828256Abstract: A method of forming a film on a substrate using one or more complexes containing one or more chelating O- and/or N-donor ligands. The complexes and methods are particularly suitable for the preparation of semiconductor structures using chemical vapor deposition techniques and systems.Type: GrantFiled: January 13, 2004Date of Patent: December 7, 2004Assignee: Micron Technology, Inc.Inventor: Brian A. Vaartstra
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Patent number: 6812164Abstract: A method for ionization film formation to form a deposited film by ionizing vaporized particles with an ionization mechanism of the hot-cathode system and injecting the ionized particles into a substrate is provided. The method includes the step of introducing He gas inside the ionization mechanism.Type: GrantFiled: January 24, 2003Date of Patent: November 2, 2004Assignee: Canon Kabushiki KaishaInventors: Hirohito Yamaguchi, Masahiro Kanai, Atsushi Koike, Katsunori Oya
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Patent number: 6777349Abstract: Hermetic amorphous doped silicon carbide is deposited on an integrated circuit substrate in a PECVD reactor. Nitrogen-doping of an SiC film is conducted by flowing nitrogen-containing molecules, preferably nitrogen or ammonia gas, into the reactor chamber together with an organosilane, preferably tetramethylsilane, and forming a plasma. Oxygen-doping is conducted by flowing oxygen-containing molecules into the reaction chamber.Type: GrantFiled: June 28, 2002Date of Patent: August 17, 2004Assignee: Novellus Systems, Inc.Inventors: Haiying Fu, Ka Shun Wong, Xingyuan Tang, Judy Hsiu-Chih Huang, Bart Jan van Schravendijk
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Patent number: 6759346Abstract: A method of forming a dielectric layer includes placing a semiconductor wafer in a reaction chamber. Oxygen, hafnium and silicon sources are separately provided to the reaction chamber to react with the wafer. After each source has reacted, a monolayer or near-monolayer film is produced. Each source may also be provided to the reaction chamber a number of times to achieve a film having the desired thickness.Type: GrantFiled: October 15, 2002Date of Patent: July 6, 2004Assignee: Advanced Micro Devices, Inc.Inventor: Joong Jeon
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Patent number: 6746970Abstract: A passivation layer is deposited onto the surface of a substrate followed by deposition of a polymer layer, through the application of a plasma enhanced chemical vapor deposition process, in which the substrate is placed on a chuck within a reaction chamber and fluorocarbon gas is introduced into the reaction chamber under the influence of at least one plasma source. The fluorocarbon gas can be a CFX gas. The at least one plasma source can include a first plasma source that ionizes the fluorocarbon gas by applying RF plasma energy, and a second plasma source that applies a near-zero self-bias to the substrate at an RF frequency during deposition of the passivation layer and a greater bias during deposition of the polymer layer. The passivation layer is deposited prior to the polymer layer to protect the surface of the substrate from damage during the deposition of the polymer layer.Type: GrantFiled: June 24, 2002Date of Patent: June 8, 2004Assignee: Macronix International Co., Ltd.Inventors: Ming-Chung Liang, Chung Tai Chen, Hsin-Yi Tsai
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Patent number: 6737365Abstract: A dielectric layer is made porous by treating the dielectric material after metal interconnects are formed in or through that layer. The porosity lowers the dielectric constant of the dielectric material. The dielectric material may be subjected to an electron beam or a sonication bath to create the pores. The structure has smooth sidewalls for metal interconnects extending through the dielectric layer.Type: GrantFiled: March 24, 2003Date of Patent: May 18, 2004Assignee: Intel CorporationInventors: Grant M. Kloster, Kevin P. O'Brien, Justin K. Brask, Michael D. Goodner, Donald Bruner
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Publication number: 20040072081Abstract: Method and apparatus for etching an optically transparent layer disposed on a substrate, such as a photolithographic reticle, are provided. In one aspect, a method is provided for etching a substrate comprising placing the reticle on a support member in a processing chamber, positioning the reticle on a support member in a processing chamber, wherein the reticle comprises a patterned metal photomask layer formed on an optically transparent material, and a patterned resist material deposited on the patterned metal photomask layer, introducing a processing gas comprising one or more fluorine containing hydrocarbons and one or more chlorine-containing gases into the processing chamber, delivering power to the processing chamber to generate a plasma by applying a source RF power to a coil and applying a bias power to the support member, and etching exposed portions of the optically transparent material.Type: ApplicationFiled: May 13, 2003Publication date: April 15, 2004Inventors: Thomas P. Coleman, Yi-Chiau Huang, Melisa J. Buie, Lawrence C. Sheu, Brigitte C. Stoehr, Phillip L. Jones
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Patent number: 6713390Abstract: A method is provided for depositing a barrier layer on a substrate using a gaseous mixture that includes a hydrocarbon-containing gas and a silicon-containing gas. The gaseous mixture is provided to a process chamber and is used to form a plasma for depositing the barrier layer. The barrier layer is deposited with a thickness less than 500 Å. Suitable hydrocarbon-containing gases include alkanes and suitable silicon-containing gases include silanes.Type: GrantFiled: July 12, 2002Date of Patent: March 30, 2004Assignee: Applied Materials Inc.Inventors: Hichem M'Saad, Seon Mee Cho, Dana Tribula
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Patent number: 6673709Abstract: The reactive element is introduced to the surface of the metal substrate in the form of an oxide powder and the aluminide-type coating is then formed.Type: GrantFiled: August 27, 2001Date of Patent: January 6, 2004Assignee: SNECMA MoteursInventors: Yann Jaslier, Alain Martinez, Marie-Christine Ntsama Etoundi, Guillaume Oberlaender
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Patent number: 6673725Abstract: The present invention relates to a semiconductor device manufacturing method for forming an interlayer insulating film having a low dielectric constant by coating a copper wiring. The low dielectric constant insulating film is formed by reaction of a plasma of a film-forming gas containing an oxygen-containing gas of N2O, H2O, or CO2, ammonia (NH3), and at least one of an alkyl compound having a siloxane bond and methylsilane (SiHn(CH3)4−n: n=0, 1, 2, 3).Type: GrantFiled: April 30, 2001Date of Patent: January 6, 2004Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.Inventors: Yoshimi Shioya, Kouichi Ohira, Kazuo Maeda
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Publication number: 20030190821Abstract: The present invention discloses a method for forming a layer of nitrogen and silicon containing material on a substrate by first providing a heated substrate and then flowing a gas which has silicon and nitrogen atoms but no carbon atoms in the same molecule over said heated substrate at a pressure of not higher than 500 Torr, such that a layer of nitrogen and silicon containing material is formed on the surface. The present invention is further directed to a composite structure that includes a substrate and a layer of material containing nitrogen and silicon but not carbon overlying the substrate for stopping chemical species from reaching the substrate. The present invention is further directed to a structure that includes a semiconducting substrate, a gate insulator on the substrate, a nitrogen-rich layer on top of the gate insulator, and a gate electrode on the nitrogen-rich layer, wherein the nitrogen-rich layer blocks diffusion of contaminating species from the gate electrode to the gate insulator.Type: ApplicationFiled: May 2, 2003Publication date: October 9, 2003Applicant: International Business Machines CorporationInventors: Douglas Andrew Buchanan, Matthew Warren Copel, Fenton Read McFeely, Patrick Ronald Varekamp, Mark Monroe Banaszak Holl, Kyle Erik Litz
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Patent number: 6624094Abstract: A method of manufacturing an interlayer dielectric film by vacuum ultraviolet CVD including the steps of placing a wafer in a vacuum chamber having a window; causing a first gas that contains silicon atoms to flow through the vacuum chamber; exposing the wafer to light emitted from a Xe2 excimer lamp through the window; and maintaining an atmosphere in the chamber at a first temperature which is less than 350° C. to form an insulating film on the wafer which substantially fills stepped portions of the wafer to provide step coverage and which has a substantially flat top surface.Type: GrantFiled: April 13, 2001Date of Patent: September 23, 2003Assignee: Oki Electric Industry, Co., Ltd.Inventors: Kiyohiko Toshikawa, Yoshikazu Motoyama, Yousuke Motokawa, Yusuke Yagi, Junichi Miyano, Tetsurou Yokoyama, Yutaka Ichiki
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Patent number: 6620741Abstract: A method for controlling etch bias of carbon doped oxide films comprising performing the etch in a cyclic two step process i.e., a carbon doped oxide (CDO) removal process, said CDO removal process comprises a first gas to etch a trench in the CDO layer. The CDO removal process is followed by a polymer deposition process. The polymer deposition process comprises introducing a second gas in the reactor to deposit a polymer in the trench of the CDO layer. The first gas comprises a first molecule having a first ratio of carbon atoms to fluorine atoms, and the second gas comprises a second molecule having a second ratio of carbon atoms to fluorine atoms, such that the second ratio of carbon atoms to fluorine atoms is greater than the first ratio of carbon atoms to fluorine atoms. The above process may be repeated to etch the final structure.Type: GrantFiled: June 10, 2002Date of Patent: September 16, 2003Assignee: Intel CorporationInventors: David H. Gracias, Hyun-Mog Park, Vijayakumar S. Ramachandrarao
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Publication number: 20030162412Abstract: A method of forming a silicon nitride film includes a CVD process that uses an organic Si compound having an organic silazane bond as a gaseous source. The CVD process is conducted under a condition that the organic silazane bond in the organic Si source is preserved in the silicon nitride film.Type: ApplicationFiled: January 23, 2003Publication date: August 28, 2003Inventor: Gishi Chung
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Publication number: 20030141560Abstract: A method of forming a diffusion barrier layer in a semiconductor device is disclosed. A high-k gate dielectric layer is formed over a substrate. A silicon nitride barrier layer is subsequently formed over the high-k gate dielectric layer by reacting tetrachlorosilane with ammonia through a chemical vapor deposition process. The silicon nitride barrier layer substantially blocks diffusion of impurities from an ensuing overlying gate layer. A semiconductor device comprising the silicon nitride barrier layer, and a method of fabricating such a semiconductor device are also disclosed.Type: ApplicationFiled: January 25, 2002Publication date: July 31, 2003Inventor: Shi-Chung Sun
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Patent number: 6596652Abstract: A method of forming a low dielectric constant film. The low dielectric constant film is formed by passing gaseous silane into a reaction chamber and performing a plasma chemical vapor deposition to form a carbon-rich layer. Micro-particles deposited on the dielectric film are purged by ammonia. By adjusting the flow rate of ammonia, and the pressure and plasma density inside the reaction chamber, several ammonium plasma conditions are produced in sequence to clear the particles on the dielectric film.Type: GrantFiled: March 6, 2001Date of Patent: July 22, 2003Assignee: United Microelectronics Corp.Inventors: Neng-Hui Yang, Ming-Sheng Yang
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Patent number: 6573196Abstract: A method of forming an organosilicate layer is disclosed. The organosilicate layer is formed by applying an electric field to a gas mixture comprising a phenyl-based silane compound. The gas mixture may optionally include an oxidizing gas. The organosilicate layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the organosilicate layer is used as an anti-reflective coating (ARC). In another integrated circuit fabrication process, the organosilicate layer is incorporated into a damascene structure.Type: GrantFiled: August 12, 2000Date of Patent: June 3, 2003Assignee: Applied Materials Inc.Inventors: Frederick Gaillard, Li-Qun Xia, Tian-Hoe Lim, Ellie Yieh
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Patent number: 6521544Abstract: A method of forming an ultra thin dielectric film or dielectric layer on a semiconductor device is disclosed. In one embodiment of the present invention, an oxide layer is formed over a substrate. A silicon-containing material is deposited over the oxide layer. The deposited material and oxide layer are processed in a plasma to form the dielectric layer or ultra thin dielectric film. The silicon-containing dielectric layer can allow for improved or smaller semiconductor devices. The silicon containing dielectric layer can be fabricated at low temperatures. Improved or smaller semiconductor devices may be accomplished by reducing leakage, increasing the dielectric constant or fabricating at lower temperatures.Type: GrantFiled: August 31, 2000Date of Patent: February 18, 2003Assignee: Micron Technology, Inc.Inventors: Vishnu Agarwal, Garry Anthony Mercaldi
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Patent number: 6500772Abstract: A method of depositing a film on a substrate, comprising placing the substrate in the presence of plasma energy, and contacting the substrate with a reactive gas component comprising a compound of the formula (R—NH)4−nSiXn, wherein R is an alkyl group, n is 1, 2, or 3, and X is selected from hydrogen or the halogens. The reactive gas composition may further comprise an oxidizer and/or a reducing agent.Type: GrantFiled: January 8, 2001Date of Patent: December 31, 2002Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Richard A. Conti, Chester Dziobkowski, Thomas Ivers, Paul Jamison, Frank Liucci
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Patent number: 6495447Abstract: A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer; decreasing the hydrophilic properties of a first portion of the dielectric layer, forming an opening through the dielectric layer, and filling the opening with metal to form a first metal feature. The hydrophilic properties of the first portion are lesser than a second portion of the dielectric layer. The hydrophilic properties of the first portion can be decreased by doping the first portion with hydrogen using ion implantation or plasma etching. An upper surface of the dielectric layer can also be roughened during the process of hydrogen doping. A semiconductor device produced by the method of manufacturing is also disclosed.Type: GrantFiled: June 26, 2001Date of Patent: December 17, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Lynne A. Okada, Calvin T. Gabriel
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Patent number: 6492240Abstract: Performance of the high resistance resistor, which is polysilicon, is improved by treating the surface of the polysilicon layer in mixed signal integrated circuits for ADSL (Asymmetric Digital Subscriber Line) broadband service application. This treated surface of the polysilicon layer will prevent ions in the resistor from out-diffusion when performing an annealing step after forming the resistor.Type: GrantFiled: September 14, 2000Date of Patent: December 10, 2002Assignee: United Microelectronics Corp.Inventors: Shyan-Yhu Wang, Kun-Lin Wu
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Patent number: 6465373Abstract: A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-comprising gas to deposit a thin silicon nitride seeding layer on the surface, and then exposed to a mixture of silicon tetrachloride (TCS) and a nitrogen comprising gas to deposit a TCS silicon nitride layer on the DCS seeding layer. In another embodiment, the method involves first nitridizing the surface of the silicon-comprising substrate prior to forming the DCS nitride seeding layer and the TCS nitride layer. The method achieves a TCS nitride layer having a sufficient thickness to eliminate bubbling and punch-through problems and provide high electrical performance regardless of the substrate type. Also provided are methods of forming a capacitor, and the resulting capacitor structures.Type: GrantFiled: August 31, 2000Date of Patent: October 15, 2002Assignee: Micron Technology, Inc.Inventors: Lingyi A. Zheng, Er-Xuan Ping
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Patent number: 6455421Abstract: A method of forming tantalum nitride (TaN) compound layers for use in integrated circuit fabrication processes is disclosed. The tantalum nitride (TaN) compound layer is formed by thermally decomposing a tantalum containing metal organic precursor. After the tantalum nitride (TaN) compound layer is formed, it is plasma treated.Type: GrantFiled: July 31, 2000Date of Patent: September 24, 2002Assignee: Applied Materials, Inc.Inventors: Toshio Itoh, Michael X. Yang, Christophe Marcadal
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Patent number: 6399489Abstract: A method of depositing a film, such as a barrier layer, on a substrate using a gaseous mixture including a hydrocarbon-containing gas and a silicon-containing gas. Suitable hydrocarbon-containing gases include alkanes such as methane (CH4), ethane (C2H6), butane (C3H8), propane (C4H10), etc. Suitable silicon-containing gases include silanes such as monosilane (SiH4). The method generally comprises providing a suitable gaseous mixture to the chamber, generating a plasma from the gaseous mixture, and depositing a film onto the substrate using the plasma. In a preferred embodiment, the film is deposited in a high-density plasma chemical vapor deposition (HDP-CVD) system. The gaseous mixture typically includes a silicon containing gas, such as an alkane, and a hydrocarbon containing gas, such as a silane. Embodiments of the method of the present invention can integrated stack structures having overall dielectric constant of about 4.0 or less.Type: GrantFiled: November 1, 1999Date of Patent: June 4, 2002Assignee: Applied Materials, Inc.Inventors: Hichem M'Saad, Seon Mee Cho, Dana Tribula
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Publication number: 20020013068Abstract: The present invention discloses a film forming method for forming an insulating film having a low dielectric constant. This method comprises the steps of adding at least one diluting gas of an inert gas and a nitrogen gas (N2) to a major deposition gas component consisting of siloxane and N2O, converting the resultant deposition gas into plasma, causing reaction in the plasma, and forming an insulating film 25,27,or28 on a substrate targeted for film formation.Type: ApplicationFiled: May 24, 2001Publication date: January 31, 2002Applicant: CANON SALES CO., INC.Inventors: Youichi Yamamoto, Hiroshi Ikakura, Tomomi Suzuki, Yuichiro Kotake, Yoshimi Shioya, Kouichi Ohira, Shoji Ohgawara, Kazuo Maeda
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Patent number: 6333278Abstract: An interlayer insulating film of a semiconductor device is made of a material in which silicon atoms are main elements, and each of the silicon atoms has an oxygen bond and a carbon bond, and further at least some of the silicon atoms have a hydrogen bond. The interlayer insulating film is formed by chemical vapor deposition employing a mixed gas of hydrogen peroxide and a reactive gas having a gas molecular structure in which silicon atoms have a hydrogen bond and a carbon bond.Type: GrantFiled: March 15, 2000Date of Patent: December 25, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Masazumi Matsuura
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Patent number: 6225241Abstract: To provide a fabrication method of compound semiconductor devices which can improve the problems of conventional MESFETs, such as the breakdown voltage degradation owing to increase of the gate leak current or the electron traps in the passivation film, the drain current decrease because of the gate-lag, or the threshold voltage dispersion caused by the interfacial tension, and easily restrain the emitter-size effect of conventional mesa type HBT without revising or complicating its epitaxial layer structure, a fabrication method according to the invention of a semiconductor device having a high-resistance film (9) covering a part of a surface other than electrodes (5, 6, and 7) of the semiconductor device comprises a step of depositing the high-resistance film (9) by way of catalytic CVD.Type: GrantFiled: January 15, 1998Date of Patent: May 1, 2001Assignee: NEC CorporationInventor: Yosuke Miyoshi
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Patent number: 6221734Abstract: A method of reducing a chemical mechanical polishing (CMP) dishing effect. A plurality of trenches are formed in the substrate, while a first insulating layer, such as silicon oxide layer is formed on the substrate to fill those trenches. A chemical reaction, such as nitridation reaction, is performed on the surface of the insulating layer to form a second insulating layer, which is harder than the first insulating layer. CMP is then performed.Type: GrantFiled: July 15, 1999Date of Patent: April 24, 2001Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Chingfu Lin
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Patent number: 6156673Abstract: A ceramic layer, in particular having ferroelectric, dielectric or superconducting properties, uses compounds with a simple structure as precursors and only methanoic acid, acetic acid or propionic acid and, where appropriate, water as solvent.Type: GrantFiled: September 30, 1998Date of Patent: December 5, 2000Assignee: Infineon Technologies AGInventors: Frank Hintermaier, Carlos Mazure-Espejo
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Patent number: 5972804Abstract: A method for forming an oxynitride gate dielectric layer (202, 204) begins by providing a semiconductor substrate (200). This semiconductor substrate is cleaned via process steps (10-28). Optional nitridation and oxidation are performed via steps (50 and 60) to form a thin interface layer (202). Bulk oxynitride gate deposition occurs via a step (70) to form a bulk gate dielectric material (204) having custom tailored oxygen and nitrogen profile and concentration. A step (10) is then utilized to in situ cap this bulk dielectric layer (204) with a polysilicon or amorphous silicon layer (208). The layer (208) ensures that the custom tailors oxygen and nitrogen profile and concentration of the underlying gate dielectric (204) is preserved even in the presence of subsequent wafer exposure to oxygen ambients.Type: GrantFiled: November 3, 1997Date of Patent: October 26, 1999Assignee: Motorola, Inc.Inventors: Philip J. Tobin, Rama I. Hegde, Hsing-Huang Tseng, David O'Meara, Victor Wang
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Patent number: 5968611Abstract: A method for chemical vapor deposition of a silicon-nitrogen based film onto a substrate includes introducing into a deposition chamber: (i) a substrate; (ii) a haloethylsilane precursor in the vapor state; and (iii) at least one nitrogen-containing reactant gas; and maintaining the deposition temperature within the chamber as from about 200.degree. C. to about 1000.degree. C. for a period of time sufficient to deposit a silicon-nitrogen based film on the substrate. Silicon-nitrogen based films are also included which are formed by chemical vapor deposition using a haloethylsilane precursor in a vapor state and at least one reactant gas comprising nitrogen.Type: GrantFiled: November 26, 1997Date of Patent: October 19, 1999Assignees: The Research Foundation of State University of New York, Gelest, Inc.Inventors: Alain E. Kaloyeros, Barry C. Arkles
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Patent number: 5904567Abstract: A chemical vapor reaction method including (a) introducing a first reactive gas into a reaction chamber; (b) exciting the first reactive gas to form a first film over a substrate; (c) introducing a second reactive gas into the reaction chamber after the formation of the first film; (d) exciting the second reactive gas to form a second film on the first film wherein the first film constitutes one of a semiconductor material and an insulating material while the second film constitutes the other one of the semiconductor material and the insulating material; (e) introducing a cleaning gas including nitrogen fluoride into the reaction chamber; and (f) exciting the cleaning gas in order to perform a cleaning in the inside of the reaction chamber.Type: GrantFiled: September 9, 1997Date of Patent: May 18, 1999Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 5817549Abstract: A TFT having a crystalline semiconductor layer and a gate insulating film of silicon oxide is manufactured. The gate insulating film is formed by vapor phase deposition such as sputtering or CVD and the deposited silicon oxide is thermally annealed in a reactive nitrogen atmosphere. The silicon oxide film, especially, the boundary portion of the silicon oxide film close the active region is nitrided. Thus, dangling bonds included in the silicon oxide film can be neutralized.Type: GrantFiled: August 30, 1995Date of Patent: October 6, 1998Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasuhiko Takemura
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Patent number: 5795820Abstract: A method and apparatus is provided for simplifying the manufacture of an interlayer dielectric where local interconnects are utilized. The invention utilizes a separate LI stack and first contact stack deposition and etch. In the first step, a layer of oxide etch stop and a layer of TEOS oxide are deposited to form a first LI stack. This stack is then contact etched, filled, and polished. A first contact stack is then formed by deposition of a doped silane oxide layer that is contact etched, filled, and polished. The method produces an ILD with a first layer of oxide etch stop, a second layer of undoped TEOS oxide, and a final layer of doped silane oxide.Type: GrantFiled: July 1, 1996Date of Patent: August 18, 1998Assignee: Advanced Micro DevicesInventor: Nick Kepler