Abstract: The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined.

Abstract: A semiconductor device having a specific contact angle for immersion lithography is disclosed. The semiconductor device includes a substrate and a top layer disposed on the substrate. The top layer used in an immersion lithography process includes a composition such that a fluid droplet that occurs during the immersion lithographic process and is not part of an exposure fluid puddle, will have a contact angle between about 40° and about 80° with a surface of the top layer.

Abstract: A phase change memory (PCM) device, a manufacturing technique of making the PCM device, and a way of operating the PCM device is presented. The PCM device is structured to have a silicon on insulator type substrate that provides an advantage of thermally insulating the active area of the PCM device without the need for an additional insulation layer. The PCM device has a phase change resistor PCR that has one terminal connected to a word line and the other terminal connected in common to the N-terminals of two PN diodes in which the P-terminals are connected in common to the bit line. As a result, a current flowing through the phase change resistor PCR is doubled which results in doubling the cell driving capacity.

Abstract: This invention provides methods and systems, e.g., to control the flow of photo-polymerizable resins. In the method, e.g., flow of a photo-polymerizable resin is restricted from illuminated resin exclusion regions on a substrate surface by precisely situated flow barriers. A system to control photo-polymerizable resin flow includes, e.g., a light source, a mask and a substrate.

Abstract: A phase change memory may be formed which is amenable to multilevel programming. The phase change material may be formed with a lateral extent which does not exceed the lateral extent of an underlying heater. As a result, the possibility of current bypassing the amorphous phase change material in the reset state is reduced, reducing the programming current that is necessary to prevent this situation. In addition, a more controllable multilevel phase change memory may be formed in some embodiments.

Abstract: In accordance with some embodiments described herein, a method for transferring a substrate to two or more process modules is provided, comprising loading at least one substrate into one or more mobile transverse chambers, the mobile transverse chambers being carried on a rail positioned adjacent to the two or more process modules, and wherein each mobile transverse chamber is configured to maintain a specified gas condition during conveyance of the substrate. One or more drive systems are actuated to propel at least one of the one or more mobile transverse chambers along the rail. The at least one mobile transfer chamber docks to at least one of the process modules, and the substrate is conveyed from the mobile transverse chamber to the at least one process modules.

Abstract: A method of batching substrates in an automated processing tool, the automated process tool and a system for batching substrates in the automated process tool. The method includes selecting a first container containing a first group of substrates; simultaneously transferring each substrate of the first group of substrates into a batching station of the automated processing tool; selecting a second container containing a second group of substrates; selecting less than all substrates of the second group of substrates; and transferring each substrate of the less than all substrates of the second group of substrates to the batching station to form a third group of substrates.

Abstract: A novel top-down procedure for synthesis of stable passivated nanoparticles uses a one-step mechanochemical process to form and passivate the nanoparticles. High-energy ball milling (HEBM) can advantageously be used to mechanically reduce the size of material to nanoparticles. When the reduction of size occurs in a reactive medium, the passivation of the nanoparticles occurs as the nanoparticles are formed. This results in stable passivated silicon nanoparticles. This procedure can be used, for example in the synthesis of stable alkyl- or alkenyl-passivated silicon and germanium nanoparticles. The covalent bonds between the silicon or germanium and the carbon in the reactive medium create very stable nanoparticles.

Abstract: A sensing system includes a nanowire, a passivation layer established on at least a portion of the nanowire, and a barrier layer established on the passivation layer.

Abstract: A method of operating and process for fabricating an electron source. A conductive rod is covered by an insulating layer, by dipping the rod in an insulation solution, for example. The rod is then covered by a field emitter material to form a layered conductive rod. The rod may also be covered by a second insulating material. Next, the materials are removed from the end of the rod and the insulating layers are recessed with respect to the field emitter layer so that a gap is present between the field emitter layer and the rod. The layered rod may be operated as an electron source within a vacuum tube by applying a positive bias to the rod with respect to the field emitter material and applying a higher positive bias to an anode opposite the rod in the tube. Electrons will accelerate to the charged anode and generate soft X-rays.

Abstract: A resistance memory element having a pair of electrodes and an insulating film sandwiched between a pair of electrodes includes a plurality of cylindrical electrodes of a cylindrical structure of carbon formed in a region of at least one of the pair of electrodes, which is in contact with the insulating film. Thus, the position of the filament-shaped current path which contributes to the resistance states of the resistance memory element can be controlled by the positions and the density of the cylindrical electrodes.

Abstract: A processing chamber is seasoned by providing a flow of season precursors to the processing chamber. A high-density plasma is formed from the season precursors by applying at least 7500 W of source power distributed with greater than 70% of the source power at a top of the processing chamber. A season layer having a thickness of at least 5000 ? is deposited at one point using the high-density plasma. Each of multiple substrates is transferred sequentially into the processing chamber to perform a process that includes etching. The processing chamber is cleaned between sequential transfers of the substrates.

Abstract: An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×108 Ohm-cm.

Abstract: In manufacturing a semiconductor device, a first chamber is provided. An opening couples the first chamber to a first environment through which at least one substrate can pass. A first seal environmentally isolates the first chamber from the first environment. A process chamber is coupled to the first chamber. Another seal environmental isolates the first and the process chambers. The substrate is placed within the first chamber, and the first chamber and the outside environment are isolated. The second opening is opened, and the substrate moves into the semiconductor process chamber. The first chamber is again environmentally isolated from the second volume. A semiconductor processing step is performed on the substrate within the processing chamber. While the substrate is processed, the substrate is rotated and translated through the processing chamber.

Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.

Abstract: A silicon/lithium battery can be fabricated from a silicon substrate. This allows the battery to be produced as an integrated unit on a chip. The battery includes a silicon anode formed from submicron diameter pillars of silicon fabricated on an n-type silicon wafer. The battery also includes a cathode including lithium.

Abstract: A composition for removing an insulation material and related methods of use are disclosed. The composition comprises about 1 to 50 percent by weight of an oxidizing agent, about 0.1 to 35 percent by weight of a fluorine-containing compound, and water. The insulation material comprises at least one of a low-k material and a protection material.

Abstract: A method that includes forming a gate of a semiconductor device on a substrate and forming a recess for an embedded silicon-straining material in source and drain regions for the gate. In this method, a proximity value, which is defined as a distance between the gate and a closest edge of the recess, is controlled by controlling formation of an oxide layer provided beneath the gate. The method can also include feedforward control of process steps in the formation of the recess based upon values measured during the formation of the recess. The method can also apply feedback control to adjust a subsequent recess formation process performed on a subsequent semiconductor device based on the comparison between a measured proximity value and a target proximity value to decrease a difference between a proximity value of the subsequent semiconductor device and the target proximity value.

Abstract: In accordance with the invention, there is a method of forming a nanochannel including depositing a photosensitive film stack over a substrate and forming a pattern on the film stack using interferometric lithography. The method can further include depositing a plurality of silica nanoparticles to form a structure over the pattern and removing the pattern while retaining the structure formed by the plurality of silica nanoparticles, wherein the structure comprises an enclosed nanochannel.

Abstract: The present invention is a substrate processing apparatus including: a holder that holds substrates in a tier-like manner; a processing container that contains the holder and that conducts a predetermined thermal process to the substrates in a process-gas atmosphere under a predetermined temperature and pressure; a gas-introducing part that introduces a process gas into the processing container; a gas-discharging part that discharges a gas from the processing container to create a predetermined vacuum pressure therein; and a heating part that heats the processing container; wherein the holder is provided with baffle plates each of which forms a processing space for each substrate when the holder is contained in the processing container; the gas-introducing part is provided with gas introduction holes disposed at one lateral side of the respective processing spaces; and the gas-discharging part is provided with gas discharge holes disposed at the other lateral side of the respective processing spaces, opposite

Abstract: An apparatus for heating a chip includes: a laser generator for emitting a laser beam to a semiconductor chip to heat the semiconductor chip; and a beam intensity adjuster disposed on a laser emission path between the semiconductor chip and the laser generator to equalize the intensity of the laser beam to be emitted to the semiconductor chip. A flip chip bonder having the chip heating apparatus, and a method for bonding a flip chip using the same are also provided.

Abstract: A method of fabricating a semiconductor metamaterial is provided, comprising providing a sample of engineered microstructured material that is transparent to electromagnetic radiation and comprises one or more elongate, high aspect ratio voids, passing through the voids a high pressure fluid comprising a semiconductor material carried in a carrier fluid, and causing the semiconductor material to deposit onto the surface of the one or more voids of the engineered microstructured material to form the metamaterial. Many microstructured materials and semiconductor materials can be used, together with various techniques for controlling the location, spatial extent, and thickness of the deposition of the semiconductor within the microstructured material, so that a wide range of different metamaterials can be produced.

Abstract: MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One embodiment provides a method of making a MEMS device that includes depositing a polymer layer over a substrate, forming an electrically conductive layer over the polymer layer, and vaporizing at least a portion of the polymer layer to form a cavity between the substrate and the electrically conductive layer.

Abstract: A micropump includes a body (10) of semiconductor material, accommodating fluid-tight chambers (32), having an internal preset pressure, lower than atmospheric pressure. The fluid-tight chambers (32), sealed by a diaphragm (35) that can be electrically opened, are selectively openable using a first electrode (37) and second electrodes (38), accommodating between them portions of the diaphragm (35).

Abstract: A device is used to measure contamination directly in transport enclosures of FOUP or SMIF type, for example. The transport enclosure is placed on an adapter that sets up direct communication between it and an external gas analyzer. The gas analyzer ionizes the sampled gases and performs the analysis by measuring a parameter of the ions resulting from this ionization. This measures very low levels of gaseous contamination in real time.

Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.

Abstract: The present application relates to a reinforcing structure (1, 2) for reinforcing a stack of layers (100) in a semiconductor component, wherein at least one reinforcing element (110, 118) having at least one integrated anchor-like part (110a, 110b), is provided. The basic idea is to reinforce bond pad structures by providing a better mechanical connection between the layers below an advanced underbump metallization (BUMA, UBM) by providing reinforcing elements under the UBM and/or BUMA layer.

Abstract: Programmable power management using a nanotube structure is disclosed. In one embodiment, a method includes coupling a nanotube structure of an integrated circuit to a conductive surface when a command is processed, and enabling a group of transistors of the integrated circuit based on the coupling the nanotube structure to the conductive surface. A current may be applied to the nanotube structure to couple the nanotube structure to the conductive surface. The nanotube structure may be formed from a material chosen from one or more of a polymer, carbon, and a composite material. The group of transistors may be enabled during an activation sequence of the integrated circuit. In addition, one or more transistors of the group of transistors may be disengaged from the one or more power sources (e.g., to minimize leakage) when the nanotube structure is decoupled from the conductive surface.

Abstract: An exemplary film hole forming apparatus (400) includes a chemical etching system (410) and a driving system (420). The driving system includes a transmission belt, which passes through the chemical etching system. A material of the transmission belt is polytetrafluoroethylene, polytetrafluoroethylene-containing material, polyvinylidene fluoride, metal, or metal-sandwiched composite. An exemplary method for forming film holes includes the following steps: providing a flexible printed circuit board (300) to be etched, with copper holes (321) pre-formed thereat and the copper holes exposing a base film (310) at corresponding positions; and transporting the flexible printed circuit board into a chemical etching system by a transmission belt to form film holes in the base film.

Abstract: Carbon nanotube apparatus, and methods of carbon nanotube modification, include carbon nanotubes having locally modified properties with the positioning of the modifications being controlled. More specifically, the positioning of nanotubes on a substrate with a deposited substance, and partially vaporizing part of the deposited substance etches the nanotubes. The modifications of the carbon nanotubes determine the electrical properties of the apparatus and applications such as a transistor or Shockley diode. Other applications of the above mentioned apparatus include a nanolaboratory that assists in study of merged quantum states between nanosystems and a macroscopic host system.

Abstract: The electronic properties (such as electron mobility, resistivity, etc.) of an electronic material in operation in an electronic device or electronic circuit can be modified/enhanced when subjected to dynamic or stationary magnetic fields with current flowing through the electronic material. Heating or cooling of the electronic material further enhances the electronic properties.

Abstract: A semiconductor substrate undergoing processing to fabricate integrated circuit devices thereon is spun about a rotational axis while introducing liquid onto a surface of the substrate. An annular-shaped sheet of liquid is formed on the surface, the sheet of liquid having an inner diameter defining a liquid-free void. The size of a diameter of the void is reduced by manipulation of the annular-shaped sheet of liquid. The void may then be enlarged until the surface is substantially dry. The annular-shaped sheet of liquid may be formed and altered by selectively moving a contact area on the surface of the substrate on which the liquid is introduced. Systems for processing a substrate and configured to deposit and manipulate a sheet of liquid thereon are also disclosed.

Abstract: Hydrogen ions are implanted to a surface (main surface) of the single crystal Si substrate 10 to form the hydrogen ion implanted layer (ion-implanted damage layer) 11. As a result of the hydrogen ion implantation, the hydrogen ion implanted boundary 12 is formed. The single crystal Si substrate 10 is bonded to the quartz substrate 20 having a carbon concentration of 100 ppm or higher, and an external shock is applied near the ion-implanted damage layer 11 to delaminate the Si crystal film along the hydrogen ion implanted boundary 12 of the single crystal Si substrate 10 out of the bonded substrate. Then, the surface of the resultant silicon thin film 13 is polished to remove a damaged portion, so that an SOQ substrate can be fabricated. There can be provided an SOQ substrate highly adaptable to a semiconductor device manufacturing process.

Abstract: The electronic properties (such as electron mobility, resistivity, etc.) of an electronic material can be modified/enhanced when subjected to dynamic or stationary magnetic fields in conjunction with select cycles of heating, cooling and passage of electric current through the material. This “processing” includes one or more cycles using combinations of the aforementioned variables.

Abstract: A device linewidth characteristic is predicted based on a sharp-edged feature of a projected image of a predetermined pattern (steps 104 to 110), and an exposure condition of the pattern is adjusted based on the device linewidth characteristic that has been predicted (step 112). Then, exposure is performed under the adjusted exposure condition. That is, patterning of a resist on a substrate is performed with the projected image of the pattern (step 114). And, by developing the substrate after patterning, a resist pattern that satisfies a desired device linewidth characteristic is formed on the substrate. Accordingly, by performing etching of the substrate with the resist pattern serving as a mask, a pattern after etching can be formed with a desired linewidth.

Abstract: A method and system for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks, or with other two-mask lithographic processes employing a trim mask. The method and system comprises locating regions in a finished semiconductor design that do not contain as-designed shapes. The method and system generates dummy fill shapes in the regions at a predetermined final density and sizes the generated dummy shapes so that their local density is increased to a predetermined value. The method and system further creates corresponding trim shapes that act to expose an oversized portion of the dummy shape, effectively trimming each dummy shape back to the predetermined final density. The method and system can be implemented on a computer program product comprising a computer useable medium including a computer readable program.

Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.

Abstract: According to an aspect of the present invention, there is provided a method for evaluating a process model, the method including: acquiring, for each of given patterns, a dimensional difference amount between: a first pattern that is formed by actually applying a process onto a corresponding one of the given patterns; and a second pattern that is calculated by applying a process model modeling the process to the corresponding one of the given patterns; and evaluating the process model based on an evaluation index, the evaluation index being based on the number of the patterns at which the dimensional difference amount is equal to or less than a threshold value.

Abstract: Carbon nanotube apparatus, and methods of carbon nanotube modification, include carbon nanotubes having locally modified properties with the positioning of the modifications being controlled. More specifically, the positioning of nanotubes on a substrate with a deposited substance, and partially vaporizing part of the deposited substance etches the nanotubes. The modifications of the carbon nanotubes determine the electrical properties of the apparatus and applications such as a transistor or Shockley diode. Other applications of the above mentioned apparatus include a nanolaboratory that assists in study of merged quantum states between nanosystems and a macroscopic host system.

Abstract: A device and method associated with carbon nanowires, such as single walled carbon nanowires having a high degree of alignment are set forth herein. A catalyst layer is deposited having a predetermined crystallographic configuration so as to control a growth parameter, such as an alignment direction, a diameter, a crystallinity and the like of the carbon nanowire. The catalyst layer is etched to expose a sidewall portion. The carbon nanowire is nucleated from the exposed sidewall portion. An electrical circuit device can include a single crystal substrate, such as Silicon, and a crystallographically oriented catalyst layer on the substrate having an exposed sidewall portion. In the device, carbon nanowires are disposed on the single crystal substrate aligned in a direction associated with the crystallographic properties of the catalyst layer.

Abstract: Embodiments of a method and apparatus for imprinting a trench pattern on a substrate using ultrasonic vibrations. The trench pattern corresponds to a circuit pattern that is to be formed on the substrate, the circuit pattern including a number of conductive traces and other conductive elements. In one embodiment, the substrate includes a base layer and a layer of dielectric material overlying a surface of the base layer, and the circuit pattern is formed in the dielectric layer.

Abstract: A method of cooling a complex electronic system includes preventing system air from passing through a front side and a rear side of a server system main board, organizing a plurality of electronic segments of the server system main board, providing cool air horizontally to the server system main board through a cool air intake provided at a position located underneath the front side and at a bottom side of the server system main board, using the cool air intake to provide the cool air to a plurality of cooling segments that redirect the cool air vertically at a 90° angle, and using a hot air exhaust after the hot air reaches the top side of the server system main board to redirect the hot air horizontally at a 90° angle and exhaust the hot air.

Abstract: A method of preparing a patterned carbon nanotube array a patterned carbon nanotube array prepared thereby are provided. The method includes forming carbon nanotubes in channels of porous templates, arranging the templates in a predetermined pattern on a substrate and selectively removing the templates to expose the carbon nanotubes.

Abstract: Programmable power management using a nanotube structure is disclosed. In one embodiment, a method includes coupling a nanotube structure of an integrated circuit to a conductive surface when a command is processed, and enabling a group of transistors of the integrated circuit based on the coupling the nanotube structure to the conductive surface. A current may be applied to the nanotube structure to couple the nanotube structure to the conductive surface. The nanotube structure may be formed from a material chosen from one or more of a polymer, carbon, and a composite material. The group of transistors may be enabled during an activation sequence of the integrated circuit. In addition, one or more transistors of the group of transistors may be disengaged from the one or more power sources (e.g., to minimize leakage) when the nanotube structure is decoupled from the conductive surface.

Abstract: A substrate processing system processes a plurality of substrates in a single-substrate processing mode by a plurality of processes and provided with a plurality of modules respectively for carrying out processes. When a defect is found in a substrate, a defective processing unit that caused the defect can be easily found out. The substrate processing system and a substrate processing method to be carried out by the substrate processing system can suppress the reduction of throughput when a large number of substrates are to be processed. The substrate processing system is provided with a plurality of modules for processing a plurality of substrates (W) in a single-substrate processing mode by a plurality of processes and includes a substrate carrying means (A4) for carrying a substrate (W) from a sending module to a receiving module, and a control means (6) for controlling the substrate carrying means (A4) on the basis of one of at least two carrying modes each assigning receiving modules to sending modules.

Abstract: Carbon nanotube-based devices made by electrolytic deposition and applications thereof are provided. In a preferred embodiment, the present invention provides a device comprising at least one array of active carbon nanotube junctions deposited on at least one microelectronic substrate. In another preferred embodiment, the present invention provides a device comprising a substrate, at least one pair of electrodes disposed on the substrate, wherein one or more pairs of electrodes are connected to a power source, and a bundle of carbon nanotubes disposed between the at least one pair of electrodes wherein the bundle of carbon nanotubes consist essentially of semiconductive carbon nanotubes. In another preferred embodiment, a semiconducting device formed by electrodeposition of carbon nanotubes between two electrodes is provided. The invention also provides preferred methods of forming a semiconductive device by applying a bias voltage to a carbon nanotube rope.

Abstract: An MTJ in an MRAM array or TMR read head is disclosed in which a low magnetization capping layer is a composite having a NiFeHf inner layer formed on a NiFe or CoFeB/NiFe free layer, a Ta middle layer, and a Ru outer layer on the Ta layer. For example, a low magnetization NiFeHf layer is achieved by co-sputtering NiFe and Hf targets with a forward power of 400 W and 200 W, respectively. A higher Hf content increases the oxygen gettering power of the NiFeHf layer and the thickness is modified to change dR/R, RA, and magnetostriction values. A so-called dead layer between the free layer and capping layer is restored by incorporating a NiFeHf layer on the free layer to improve lattice matching. The Fe content in the NiFe target used to make the NiFeHf layer is preferably the same as in the NiFe free layer.

Abstract: Described herein is an apparatus useful for depositing a material on a substrate. At least one component of the apparatus comprises a protective coating, which facilitates the cleaning and/or removal of the deposited material from the component. Also described are methods for depositing a material on a substrate using the disclosed apparatus, for fabricating the apparatus, and for cleaning the apparatus.

Abstract: A method and an apparatus are provided for manufacturing an active matrix device including a top gate type TFT. A manufacturing process of the top gate type TFT includes the steps of forming an oxide film on the inner wall of a CVD processing chamber and arranging a substrate having source and drain electrodes formed thereon in the processing chamber. Additional steps include doping the source and drain electrodes with P, and forming an a-Si layer and a gate insulating film in the processing chamber. Furthermore, an apparatus is provided for manufacturing an active matrix device including a top gate type TFT having the inner surface of the processing chamber coated with the oxide film.

Abstract: Electronic devices are formed on a substrate that is advanced stepwise through a plurality of deposition vessels. Each deposition vessel includes a source of deposition material and has at least two shadow masks associated therewith. Each of the two masks is alternately positioned within the corresponding deposition vessel for patterning the deposition material onto the substrate through apertures in the mask positioned therein, and positioned in an adjacent cleaning vessel for mask cleaning. The patterning onto the substrate and the cleaning of at least one of the masks are performed concurrently.