Abstract: A wafer-level test module is disclosed to include a base layer having multiple first apertures spaced from one another at a pitch corresponding to the pitch of the image sensor chips of an integrated circuit wafer, a cover layer having second apertures respectively axially aimed at the first apertures, and an optical layer sandwiched between the base layer and the cover layer having multiple optical lenses of which the optical axes pass through the first apertures and the second apertures, so that when one image capturing device of the image sensor chips of an integrated circuit wafer is adjusted to the image plane of one of the optical lenses and the wafer-level test module is set in alignment with the integrated circuit wafer horizontally and vertically, then the effective test light can be simultaneously projected onto the image capturing devices of the respective image sensor chips through the wafer-level test module to achieve an effective wafer-level test on multiple image sensor chips of the integrated

Abstract: This invention relates to a dense ceramics having ESD dissipative characteristics, tunable volume and surface resistivities in semi-insulative range (103-1011 Ohm-cm), substantially pore free, high flexural strength, light colors, for desired ESD dissipation characteristics, structural reliability, high vision recognition, low wear and particulate contamination to be used as ESD dissipating tools, fixtures, load bearing elements, work surfaces, containers in manufacturing and assembling electrostatically sensitive microelectronic, electromagnetic, electro-optic components, devices and systems.

Abstract: The present invention relates to new methods for manufacturing photovoltaic devices and an apparatus for practicing those methods of manufacture. The present invention employs a transfer-through system for advancing work piece substrates through an integrated apparatus of multiple treatment chambers that control each of the manufacturing processes.

Abstract: A method is provided to cause deformation of a substrate during processing of the substrate.

Abstract: Semiconductor processing equipment includes a transfer chamber (3) having a plurality of transfer ports (33) arranged at different positions in a lateral direction. A process chamber (4A) for performing a semiconductor process to a substrate (W) to be processed is connected with the transfer chamber (3) through one of the transfer ports. A transfer arm device (5) is arranged in the transfer chamber (3) so as to transfer the substrate (W) through a plurality of the transfer ports (33). A drive mechanism (55) is arranged so as to extend and retract the transfer arm device (5) and to turn it in a vertical axis direction. Inclination adjusting mechanisms (6A-6C) are arranged so as to adjust the inclination of the transfer arm device (5).

Abstract: A method of forming patterned thin films includes the steps of providing a porous membrane and a solution including a plurality of solid constituents and at least one surface stabilizing agent for preventing the solid constituents from flocculating out of suspension. The solution is dispensed onto a surface of the membrane. The solution is then removed by filtration through the membrane, wherein a patterned film coated membrane comprising a plurality of primarily spaced apart patterned regions are formed on the membrane. In one embodiment the method further includes the step of blocking liquid passage through selected portions of the membrane to form a plurality of open membrane portions and a plurality of blocked membrane portions before the dispensing step. The dispensing step includes ink jet printing the solution. An article having a patterned nanotube-including film thereon includes a substrate, and a patterned nanotube including film disposed on the substrate.

Abstract: A memory cell includes a memory cell layer over a memory cell access layer. The memory cell access layer comprises a bottom electrode. The memory cell layer comprises a dielectric layer and a side electrode at least partially defining a void with a memory element therein. The memory element comprises a memory material switchable between electrical property states by the application of energy. The memory element is in electrical contact with the side electrode and with the bottom electrode. In some examples the memory element has a pillar shape with a generally constant lateral dimension with the side electrode and the dielectric layer surrounding and in contact with first and second portions of the memory element.

Abstract: Methods for compression molding through holes in polymer layers are provided, as are the resulting patterned polymer layers. Two key aspects of the invention are provision of a mold and substrate having different mechanical hardness, and provision of room for local flow of material. These aspects of the invention facilitate formation of through holes by compression molding that are not blocked or partially blocked by undesirable material. These polymer layers can be formed into three dimensional patterned structures by bonding patterned layers together. Since the layers include through holes, a three-dimensional polymer pattern can be formed. These patterned polymer layers and three dimensionally patterned polymer constructs have a wide variety of applications. For example, these constructs can be used for fabrication of micro-fluidic devices, and/or can be used for various medical and biological applications including drug delivery devices and tissue engineering devices.

Abstract: One embodiment of the present invention provides a process for fabricating an electrode for a capacitor using carbon nanotubes (CNTs), wherein the electrode comprises a metal substrate and a layer of active material (CNTs) coated onto the metal substrate. Specifically, the process starts by dispersing CNTs in a solvent to form a suspension. Next, the CNTs are charged in the suspension. The metal substrate is then immersed in the suspension. Next, the CNTs are deposited onto the metal substrate using electrophoretic deposition (EPD) to form the layer of active material on the metal substrate. In particular, the layer of active material is formed on the metal substrate without using a binder, which effectively reduces contact resistance between the active material and the metal substrate.

Abstract: A method of manufacturing a crystal oscillator, in which method semiconductor components and the crystal or another resonator (1) are joined to a bottom base (4), most suitably to the printed circuit board material. The components (2, 3, 5) are joined by soldering or gluing to said bottom base and the crystal and another resonator (1) are installed, in regard to other components (2, 3, 5), using the bottom base area on the same spot.

Abstract: The present invention relates to a method for preparing self-assembled silicon nanotubes (SiNTs) by a hydrothermal method. A method for preparing self-assembled SiNTs comprises forming a mixture of silicon oxide and water in a sealed container, wherein the mixture has a silicon oxide to water ratio of no more than 10% by weight. The mixture is maintained at a constant temperature and a constant pressure, and the mixture is stirred for a period of time. Self-assembled SiNTs may be formed with an average inner diameter of less than 5 nm and an average outer diameter of around 15 nm. The present invention completely utilizes non-toxic raw materials, and the materials and process do not pollute the environment, so the method satisfies the development trends of the modern industry.

Abstract: A memory device of the current invention includes a memory layer having nanochannels sandwiched between an upper electrode and a lower electrode, in which the memory layer is made of an organic-inorganic complex for use in formation of nanopores, and has metal nanoparticles or metal ions fed into the nanopores. Therefore, the memory device has excellent processability, high reproducibility, and uniform performance.

Abstract: An apparatus for and method of storing and transporting a photomask. A photomask storage container has fluid-tight walls, an opening for moving the photomask into and out of the container, and a sealable inlet for a storage fluid. The method includes placing the photomask in the storage container through the opening, introducing a storage fluid into the container through the inlet, closing the container opening and sealing the storage fluid inlet, whereby the storage fluid is essentially inert with respect to the photomask. The method then includes opening the container opening and contacting a surface of the photomask with an alcohol-containing gas while removing the photomask from the storage container to remove the storage fluid from the photomask surface.

Abstract: Methods for fabricating solar cells without the need to perform gasification of metallurgical-grade silicon are disclosed. Consequently, the costs and health and environmental hazards involved in fabricating the solar or silicon grade silicon are being avoided. A solar cell structure comprises a metallurgical grade doped silicon substrate and a thin-film structure formed over the substrate to form a p-i-n junction with the substrate. The substrate may be doped p-type, and the thin film structure may be an intrinsic amorphous layer formed over the substrate and an n-type amorphous layer formed over the intrinsic layer.

Abstract: A composition for the production of semiconductors, comprising H2SiF6 and/or HBF4 in a total amount of 10-500 mg/kg, 1-17 % by weight of H2S04, 1-15% by weight of H202, optionally in combination with additives, in aqueous solution and a process of removing residual polymers using the composition.

Abstract: Electronic devices are formed on a substrate that is advanced stepwise through a plurality of deposition vessels. Each deposition vessel includes a source of deposition material and has at least two shadow masks associated therewith. Each of the two masks is alternately positioned within the corresponding deposition vessel for patterning the deposition material onto the substrate through apertures in the mask positioned therein, and positioned in an adjacent cleaning vessel for mask cleaning. The patterning onto the substrate and the cleaning of at least one of the masks are performed concurrently.

Abstract: An image projection module within a housing is operative for causing selected pixels in a raster pattern to be illuminated to produce an image at different image planes of VGA quality. A movable component on the housing causes the image to be formed at a selected image plane.

Abstract: A method of batching substrates in an automated processing tool, the automated process tool and a system for batching substrates in the automated process tool. The method includes selecting a first container containing a first group of substrates; simultaneously transferring each substrate of the first group of substrates into a batching station of the automated processing tool; selecting a second container containing a second group of substrates; selecting less than all substrates of the second group of substrates; and transferring each substrate of the less than all substrates of the second group of substrates to the batching station to form a third group of substrates.

Abstract: Methods of extracting a TEM sample from a substrate include milling a hole on the sample and inserting a probe into the hole. The sample adheres to the probe, and can be processed on transferred while on the probe. In another embodiment, the sample is freed from a substrate and adheres to a probe by electrostatic attraction. The sample is placed onto a TEM sample holder in a vacuum chamber.

Abstract: A method of curing a low dielectric constant (low-k) dielectric film on a substrate is described, wherein the dielectric constant of the low-k dielectric film is less than a value of approximately 4. The method comprises exposing the low-k dielectric film to ultraviolet (UV) radiation. Following the UV exposure, the dielectric film is exposed to IR radiation.

Abstract: A method of assembling large numbers of nanoscale structures in pre-determined ways using fluids or capillary lithography to control the patterning and arrangement of the individual nanoscale objects and nanostructures formed in accordance with the inventive method are provided. In summary, the current method uses the controlled dispersion and evaporation of fluids to form controlled patterns of nanoscale objects or features anchored on a substrate, such as nanoscale fibers like carbon nanotubes.

Abstract: Substrate processing with return processing is carried out efficiently by a substrate processing apparatus that continuously processes a plurality of substrates. The apparatus is equipped with a conveyor chamber constituting a substrate convey space, a plurality of process chambers in which substrate processing is carried out, a substrate conveying device provided in the conveyor chamber having a function of conveying substrates, and a substrate convey control device that controls the process of substrate conveyance by the substrate conveying device so that in a case in which after a substrate is continuously processed by two or more process chambers, the substrate is re-conveyed from the last process chamber to any of the two or more process chambers other than the last and return processing is implemented. In the re-conveyance, the substrate is conveyed to any of the process chambers after being temporarily retracted to a place other than a process chamber.

Abstract: Inserts are used to line openings in parts that form a semiconductor processing reactor. In some embodiments, the reactor parts delimit a reaction chamber. The reactor parts may be formed of graphite. A layer of silicon carbide is deposited on surfaces of the openings in the reactor parts and the inserts are placed in the openings. The inserts are provided with a hole, which can accept another reactor part such as a thermocouple. The insert protects the walls of the opening from abrasion caused by insertion of the other reactor part into the opening.

Abstract: A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-charge-eliminating the semiconductor substrates before and after process treatment in a transport area between the load port and a treatment section. The static-charge-eliminated semiconductor substrate is accommodated in the container positioned to the load port. Thus, it is possible to decrease foreign materials adhering to the semiconductor substrate and errors in handling the semiconductor substrate.

Abstract: A substrate processing method of the present invention includes the steps of placing a substrate inside a vacuum container containing particles and processing the substrate inside the container while moving the substrate at a predetermined relative velocity of the substrate to the container. In this case, an allowable upper limit of the number or density of defects produced at the substrate due to the particles in the process for the substrate is determined, and the predetermined relative velocity is set at a value equal to or smaller than the relative velocity obtained when the number or density of defects reaches the upper limit.

Abstract: A semiconductor substrate undergoing processing to fabricate integrated circuit devices thereon is spun about a rotational axis while introducing liquid onto a surface of the substrate. An annular-shaped sheet of liquid is formed on the surface, the sheet of liquid having an inner diameter defining a liquid-free void. The size of a diameter of the void is reduced by manipulation of the annular-shaped sheet of liquid. The void may then be enlarged until the surface is substantially dry. The annular-shaped sheet of liquid may be formed and altered by selectively moving a contact area on the surface of the substrate on which the liquid is introduced. Systems for processing a substrate and configured to deposit and manipulate a sheet of liquid thereon are also disclosed.

Abstract: Elongated features may be incorporated at least partially in an alignment region. The alignment region may be defined by a plurality of alignment features aligned along a first axis. A long axis of the elongated features may be neither parallel nor perpendicular to the first axis. The alignment region may further include another plurality of alignment features aligned a second axis that is not parallel to the first axis. The second axis may be neither parallel to or perpendicular to the long axis.

Abstract: A resistance-changing function body includes an object made of a first substance and interposed between a first electrode and a second electrode, and a plurality of particles made of a second substance and arranged within the object so that an electrical resistance between the first electrode and the second electrode is changed before and after application of a specified voltage to between the first electrode and the second electrode. The first substance makes an electrical barrier against the second substance. With this constitution, by applying a specified voltage to between the first electrode and the second electrode, the electrical resistance can be changed depending on a state of the particles made of the second substance. Also, by virtue of a simple structure, a resistance-changing function body of small size is provided with low cost.

Abstract: Embodiments consistent with the present invention provide a semiconductor device having a photo aligning key and a method for manufacturing the same. The semiconductor device includes a pattern photo aligning key formed on a scribe line of a semiconductor substrate, and a plurality of dummy pattern keys formed around the pattern photo aligning key, the dummy pattern keys having a width smaller than that of the pattern photo aligning key.

Abstract: A memory device including a phase change element and a vacuum jacket. The device includes a first electrode element; a phase change element in contact with the first electrode element; an upper electrode element in contact with the phase change element; a bit line electrode in contact with the upper electrode element; and a dielectric fill layer surrounding the phase change element and the upper electrode element, spaced from the same and sealed by the bit line electrode to define a vacuum jacket around the phase change element and upper electrode element.

Abstract: A method of sample extraction entails making multiple, overlapping cuts using a beam, such as a focused ion beam, to create a trench around a sample, and then undercutting the sample to free it. Because the sidewalls of the cut are not vertical, the overlapping cuts impinge on the sloping sidewalls formed by previous cuts. The high angle of incidence provides a greatly enhanced mill rate, so that making multiple overlapping cuts to produce a wide trench can requires less time than making a single, deep cut around the perimeter of a sample.

Abstract: Experiments suggest that the mathematically weakest non-abelian TQFT may be physically the most robust. Such TQFT's—the v=5/2 FQHE state in particular—have discrete braid group representations, so one cannot build a universal quantum computer from these alone. Time tilted interferometry provides an extension of the computational power (to universal) within the context of topological protection. A known set of universal gates has been realized by topologically protected methods using “time-tilted interferometry” as an adjunct to the more familiar method of braiding quasi-particles. The method is “time-tilted interferometry by quasi-particles.” The system is its use to construct the gates {g1, g2, g3}.

Abstract: A substrate processing pallet can cool a substrate. A substrate processing pallet can include a base member; an interface pad attachable to the base member, the interface pad having substantially the same coefficient of thermal expansion as the base member and adapted to facilitate cooling of the substrate; and a surface of the base member having features for aligning a substrate on the interface pad. A substrate processing pallet can also include a base member; an interface pad attachable to the base member; an electrostatic chuck for gripping the substrate during processing; an energy storage system for storing energy to sustain the electrostatic chuck at sufficient charge to sustain grip the substrate during processing; and a conduit for transporting gas to a backside of the substrate to facilitate cooling of the substrate.

Abstract: A thermal processing system includes a source of laser radiation having an array of lasers emitting light at a laser wavelength, a substrate support, optics disposed between said source and said substrate support for forming a line beam in a substrate plane of the substrate support from the light emitted by the source of laser radiation, and scanning apparatus for effecting movement of said line beam relative to said substrate support in a direction transverse to the longitudinal axis of said line beam. The system further includes a housing encompassing said optics, a light detector disposed inside said housing for sensing an ambient light level, a power supply coupled to the source of laser radiation, and a controller governing said power supply and responsive to said light detector for interrupting said power supply upon an increase in the output of said light detector above a threshold ambient level.

Abstract: The present invention relates to a composition for the removal of so-called “sidewall residues” from metal surfaces, in particular from aluminium or aluminium-containing surfaces, in particular from aluminium or aluminium-containing surfaces, during the production of semiconductor elements.

Abstract: In a semiconductor-fabrication equipment of a minienvironment system, ambient air is prevented from entering a gap between an opening of the semiconductor-fabrication equipment and a wafer gateway of a hermetic container to prevent dust entrained in the ambient air from adhering to wafers in the hermetic container.

Abstract: The invention includes a template comprising one or both of CdS and CdSe adhered to a base in a desired pattern. The base can be any transparent or translucent material, and the desired pattern can include two or more separated segments. The template can be utilized for patterning a plurality of substrates. For instance, the substrates can be provided to have masking layers thereover, and the CdS and/or CdSe can be utilized as catalytic material to sequentially impart patterns in the masking layers. The imparting of the patterns can modify some regions of the masking layers relative to others, and either the modified or unmodified regions can be selectively removed to form patterned masks from the masking layers. Patterns from the patterned masks can then be transferred into the substrates.

Abstract: A system for of aligning a mask to a substrate comprising: a fixture for holding the mask and the substrate in fixed positions relative to each other; means for holding the substrate, the means for holding the substrate protruding through openings in a table and the fixture, the means for holding fixedly mounted on a stage, the stage moveable in first and second directions and rotatable about an axis relative to the table; means for affixing the fixture containing the mask and the substrate to the table; means for controlling the means for temporarily affixing so as to generate a uniform force around a perimeter of the fixture to effectuate the temporarily affixing; means for aligning the mask to the substrate, the means for aligning controlling movement of the stage in the first and second directions and rotation about the axis; and means for fastening the fixture together.

Abstract: A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a first electrode and a second electrode that are physically and electrically separated one from another, and which both at least partially overlie the switching layer, and a cavity disposed between the switching layer and the second electrode, where the switching is layer is flexible to make electrical contact with the second electrode by flexing through the cavity upon selective application of an electrical bias.

Abstract: A memory cell device includes a bottom electrode, pipe shaped member comprising phase change material and a top electrode in contact with the pipe-shaped member. An electrically and thermally insulating material is inside the pipe-shaped member. An integrated circuit including an array of pipe-shaped phase change memory cells is described.

Abstract: A phase-changeable memory device includes a substrate having a contact region on an upper surface thereof. An insulating interlayer on the substrate has an opening therein, and a lower electrode is formed in the opening. The lower electrode has a nitrided surface portion and is in electrical contact with the contact region of the substrate. A phase-changeable material layer pattern is on the lower electrode, and an upper electrode is on the phase-changeable material layer pattern. The insulating interlayer may have a nitrided surface portion and the phase-changeable material layer may be at least partially on the nitrided surface portion of the insulating interlayer. Methods of forming phase-changeable memory devices are also disclosed.

Abstract: A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-eliminating the semiconductor substrates before and after process treatment in a transport area between the load port and a treatment section. The static-eliminated semiconductor substrate is accommodated in the container positioned to the load port. Thus, it is possible to decrease foreign materials adhering to the semiconductor substrate and errors in handling the semiconductor substrate.

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract: A transfer chamber for a cluster system includes a first body, a second body attached at one side of the first body, and a cover combined with an upper portion of the first body. The transfer chamber further includes a third body at another side of the first body, wherein the third body has the same shape as the second body.

Abstract: A method for carrying an object to be processed used for a processing apparatus which comprises a plurality of process chambers including a specific process chamber for a process in which the object in process is easily contaminated and a carrying mechanism having two picks. The method includes a plurality of carrying steps wherein the object in process is sequentially carried from one chamber to another among the plurality of process chambers. One of the two picks is used in carrying steps up right before carrying the object into the specific process chamber, and the other pick is used in the step of carrying the object into the specific process chamber and the later carrying steps.

Abstract: A method of fabricating a nanotube structure which includes providing a substrate, providing a mask region positioned on the substrate, patterning and etching through the mask region to form at least one trench, depositing a conductive material layer within the at least one trench, depositing a solvent based nanoparticle catalyst onto the conductive material layer within the at least one trench, removing the mask region and subsequent layers grown thereon using a lift-off process, and forming at least one nanotube electrically connected to the conductive material layer using chemical vapor deposition with a methane precursor.

Abstract: A method of forming channels on a die or other substrate. Also disclosed are liquid cooling systems including such channels.

Abstract: The present invention is directed to a semiconductor apparatus that enables in situ wet processing of semiconductor wafers, and prevents creation of a static pressure within the in situ wet processing system. The apparatus comprises multiple exhaust receptacles. Each exhaust receptacle is operable in an open and closed position and receives an associated toxic wet processing byproduct only in the open position. An exhaust is connected to each exhaust receptacle and suctions the contents of said exhaust receptacle in both the open and closed positions. An intake is connected to said exhaust receptacle only when the exhaust receptacle is in a closed position. The intake introduces a gas chemically compatible to the toxic wet processing byproduct associated with the exhaust receptacle. The exhaust releases the toxic wet processing byproduct and the chemically compatible gas to the same waste stream at the semiconductor factory.

Abstract: A method and an apparatus are provided for manufacturing an active matrix device including a top gate type TFT. A manufacturing process of the top gate type TFT includes the steps of forming an oxide film on the inner wall of a CVD processing chamber and arranging a substrate having source and drain electrodes formed thereon in the processing chamber. Additional steps include doping the source and drain electrodes with P, and forming an a-Si layer and a gate insulating film in the processing chamber. Furthermore, an apparatus is provided for manufacturing an active matrix device including a top gate type TFT having the inner surface of the processing chamber coated with the oxide film.

Abstract: This invention demonstrates a method for making a device of storing energy, enhancing the efficiency of manufacture and the reliability of products. The electrode plates of storing energy are accumulated according to the working voltage needed to form a pre-structuring unit of storing energy. The electrolyte leak of a capacitor and the unequal voltage of an accumulative unit, which are the main factors of the fail in a conventional capacitor, are solved by using three layers of sealing gel. And then, the electrolyte is to back fill in by vacuum and to seal the units to accomplish the device of storing energy. Each porous electrode in the device has two faces at the same time, which are used for the positive and negative poles respectively. The electrode plates are assembled with bipolar structure, the same as the series connection of the storing-energy devices, which can reduce the volume and mass of the device and the cost of the manufacture.