Cleaning Of Reaction Chamber Patents (Class 438/905)
  • Patent number: 7569484
    Abstract: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a plasma source to provide an increased reactive species density. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: August 4, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Neal R. Rueger, Mark J. Williamson, Gurtej S. Sandhu
  • Patent number: 7569256
    Abstract: In a parallel flat plate type plasma CVD apparatus, plasma damage of constituent parts in a reaction chamber due to irregularity of dry cleaning in the reaction chamber is reduced and the cost is lowered. In the parallel flat plate type plasma CVD apparatus in which high frequency voltages of pulse waves having mutually inverted waveforms are applied to an upper electrode and a lower electrode, and the inversion interval of the pulse wave can be arbitrarily changed, the interior of the reaction chamber is dry cleaned.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: August 4, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Mitsuhiro Ichijo
  • Patent number: 7560369
    Abstract: The present invention provides a method of forming metal lines in a semiconductor device having advantages of preventing an “explosion” phenomenon during a dual damascene process so as to improve the yield of the device. An exemplary embodiment of the present invention includes removing etching residues by wet cleaning the semiconductor substrate after forming the via hole, dry cleaning the semiconductor substrate after the wet cleaning, and forming a second metal line that is electrically connected with the first metal line through the via hole.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: July 14, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Jea-Hee Kim
  • Patent number: 7550090
    Abstract: A method for in-situ cleaning of a dielectric dome surface having been used in pre-clean processes is provided. Carbon containing deposits are removed by providing a plasma of one or more oxidizing gases which react with the carbon containing films to form volatile carbon containing compounds.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: June 23, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Quancheng Gu, Cheng-Hsiung Tsai, John C. Forster, Xiaoxi Guo, Larry Frazier
  • Patent number: 7546840
    Abstract: After semiconductor wafers are loaded into a reaction vessel, and ruthenium (Ru) film or ruthenium oxide film is formed, the interior of the reaction vessel is efficiently cleaned without contaminating the wafers. The interior of the reaction vessel is heated to a temperature of above 850° C. while the pressure inside the reaction vessel is reduced to, e.g., 133 pa (1 Torr)-13.3 Kpa (100 Torr), and oxygen gas is fed into the reaction vessel at a flow rate of, e.g., above 1.5 Lm, whereby the ruthenium film or the ruthenium oxide film formed inside the reaction vessel is cleaned off. In place of oxygen gas, active oxygen, such as O3, O* and OH*, etc. may be used.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: June 16, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Daisuke Nozu, Dong-Kyun Choi
  • Patent number: 7541094
    Abstract: Described are methods and chemistries for preparing firepolished quartz parts for use in semiconductor processing. The quartz parts in need of preparation include newly manufactured parts as well as parts requiring refurbishment after previous use in semiconductor processing. The embodiments described avoid methods and chemistries that may damage the surfaces of the quartz parts and render the parts unfit for use in semiconductor processing. A method in accordance with one embodiment minimizes damage by limiting exposure of the quartz parts to hydrofluoric acid. A quartz part for use in semiconductor processing comprises a surface including a surface portion having a surface portion area to expose to a gas, wherein at least 95 percent of the surface portion area is free of defects and wherein the surface portion has less than E12 atoms per centimeter squared of aluminum.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: June 2, 2009
    Assignee: Quantum Global Technologies, LLC
    Inventors: David S. Zuck, Gregory H. Leggett
  • Patent number: 7530359
    Abstract: A plasma treatment apparatus has a reaction vessel (11) provided with a top electrode (13) and a bottom electrode (14), and the first electrode is supplied with a VHF band high frequency power from a VHF band high frequency power source (32), while the bottom electrode on which a substrate (12) is loaded and is moved by a vertical movement mechanism. The plasma treatment system has a controller (36) which, at the time of a cleaning process after forming a film on the substrate (12), controls a vertical movement mechanism to move the bottom electrode to narrow the gap between the top electrode and bottom electrode and form a narrow space and starts cleaning by a predetermined high density plasma in that narrow space. In the cleaning process, step cleaning is performed. Due to this, the efficiency of utilization of the cleaning gas is increased, the amount of exhaust gas is cut, and the cleaning speed is raised. Further, the amount of the process gas used is cut and the process cost is reduced.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: May 12, 2009
    Assignees: Canon Anelva Corporation, Sanyo Electric Co., Ltd., Renesas Technology Corporation, Matsushita Electric Industrial Co., Ltd., Ulvac, Inc., Hitachi Kokusai Electric Inc., Tokyo Electron Limited, Kanto Denka Kogyo Co., Ltd.
    Inventors: Yoichiro Numasawa, Yoshimi Watabe
  • Patent number: 7520937
    Abstract: The present invention relates to a technique for cleaning a thin film forming apparatus. In a typical embodiment, deposits originating from process gases for forming a thin film and deposited on the inner surface of a reaction tube are removed by etching by supplying a cleaning gas into the reaction tube while heating the interior of the reaction tube at a predetermined temperature. The inner surface of the reaction tube roughened by etching is subjected to a planarizing step. The planarizing step is performed by supplying a gas containing hydrogen fluoride into the reaction tube while keeping the interior of the reaction tube 2 at a low temperature, such as a room temperature. The planarizing step is effective in preventing the reduction of deposition rate in a thin film forming process.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: April 21, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Mitsuhiro Okada, Hiromichi Kotsugai
  • Patent number: 7509962
    Abstract: A method and control system for treating a hafnium-based dielectric processing system in which a system component of the processing system is exposed to a chlorine-containing gas. A residual hafnium by-product remaining in the processing system after a hafnium removal process is reacted with a chlorine-containing etchant derived from the chlorine-containing gas. A chlorinated hafnium product is volatilized for exhaustion from the processing system. The control system can utilize a computer readable medium to introduce a chlorine-containing gas to the processing system, to adjust at least one of a temperature and a pressure in the processing system to produce from the chlorine-containing gas a chlorine-containing etchant for dissolution of a residual hafnium by-product remaining in the processing system after a hafnium silicate, hafnium oxide, or hafnium oxynitride removal process, and to exhaust a chlorinated hafnium product from the processing system.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: March 31, 2009
    Assignee: Tokyo Electron Limited
    Inventors: David L. O'Meara, Shingo Maku
  • Patent number: 7506654
    Abstract: A method and apparatus that reduces the time required to clean a processing chamber employing a reactive plasma cleaning process. A plasma is formed in an Astron fluorine source generator from a flow of substantially pure inert-source gas. After formation of the plasma, a flow of a fluorine source gas is introduced therein such that the fluorine source flow accelerates at a rate no greater than 1.67 standard cubic centimeters per second2 (scc/s2). In this fashion, the plasma contains a plurality of radicals and dissociated inert-source gas atoms, defining a cleaning mixture. The ratio of inert-source gas to fluorine source is greater than 1:1.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: March 24, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Shankar N. Chandran, Scott Hendrickson, Gwendolyn D. Jones, Shankar Venkataraman, Ellie Yieh
  • Patent number: 7498267
    Abstract: A capacitor is formed by forming a mold insulating layer with a plurality of storage node holes over a semiconductor substrate. A metal storage node is formed on the surface of each of the storage node holes in the mold insulating layer. The mold insulating layer is removed by performing the following steps: loading the semiconductor substrate with the storage node in the chamber for in-situ cleaning, rinsing, and drying processes; removing the mold insulating layer by an etchant in the chamber; then rinsing the semiconductor substrate by introducing deionized water into the chamber while discharging the etchant out of the chamber; finally rinsing the rinsed semiconductor substrate with a mixed solution of the deionized water and organic solvent; drying the finally rinsed semiconductor substrate by IPA vapor in the chamber while discharging the mixed solution of the deionized water and organic solvent out of the chamber.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: March 3, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Gyu Hyun Kim, Yong Soo Choi
  • Patent number: 7494943
    Abstract: In a method for using a film formation apparatus for a semiconductor process, process conditions of a film formation process are determined. The process conditions include a preset film thickness of a thin film to be formed on a target substrate. Further, a timing of performing a cleaning process is determined in accordance with the process conditions. The timing is defined by a threshold concerning a cumulative film thickness of the thin film. The cumulative film thickness does not exceed the threshold where the film formation process is repeated N times (N is a positive integer), but exceeds the threshold where the film formation process is repeated N+1 times. The method includes continuously performing first to Nth processes, each consisting of the film formation process, and performing the cleaning process after the Nth process and before an (N+1)th process consisting of the film formation process.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: February 24, 2009
    Assignee: Tokyo Electron Limited
    Inventors: Naotaka Noro, Yamato Tonegawa, Takehiko Fujita, Norifumi Kimura
  • Patent number: 7491652
    Abstract: A process for manufacturing semiconductor devices in an in-line processing includes the steps of: forming a silicon nitride film on a semiconductor wafer by nitrization in a reactor chamber having an inner pressure at a specific pressure; reducing the inner pressure from the specific pressure; raising the inner pressure up to the specific pressure; replacing the semiconductor wafer with another semiconductor wafer; and forming a nitride film on the another semiconductor wafer at the specific pressure.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: February 17, 2009
    Assignee: Elpida Memory, Inc.
    Inventors: Naonori Fujiwara, Hiroyuki Kitamura
  • Patent number: 7481230
    Abstract: A plasma processing method allows to suppress the drop of the etching rate of the depoless-process without performing an additional seasoning process right after the dry cleaning process. The method includes a first and a second plasma processing step carried out in a single chamber and a step of dry cleaning an inside of the chamber by using a dummy substrate between the first and the second plasma processing step. Deposits are substantially accumulated in the chamber during the first plasma processing step, while substantially no deposits are accumulated in the chamber during the second plasma processing step. The dry cleaning step is performed by supplying into the chamber a deposit removing gas for removing the deposits produced in the chamber during the first plasma processing step and a dummy substrate etching gas capable of etching the dummy substrate.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: January 27, 2009
    Assignee: Tokyo Electron Limited
    Inventor: Hiromi Sakima
  • Patent number: 7470594
    Abstract: A method is disclosed for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor device. The interfacial oxide layer is formed between an underlying substrate of single crystal silicon and an upper layer of polysilicon. The current gain and the emitter resistance of the transistor device are related to the thickness of the interfacial oxide layer. The oxide of the interfacial oxide layer is grown in a low pressure, low temperature pure oxygen (O2) environment that greatly reduces the oxidation rate. The low oxidation rate allows the thickness of the interfacial oxide layer to be precisely controlled and sources of variation to be minimized in the manufacturing process.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: December 30, 2008
    Assignee: National Semiconductor Corporation
    Inventors: Richard W. Foote, Jr., William Max Coppock, Darren Lee Rust, Charles A. Dark
  • Patent number: 7432215
    Abstract: A semiconductor device manufacturing method comprises a first step of forming, by a thermal chemical vapor deposition method, a silicon nitride film on an object disposed in a reaction container, with bis tertiary butyl amino silane and NH3 flowing into the reaction container, and a second step of removing silicon nitride formed in the reaction container, with NF3 gas flowing into the reaction container.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: October 7, 2008
    Assignee: Kokusai Electric Co., Ltd.
    Inventors: Norikazu Mizuno, Kiyohiko Maeda
  • Publication number: 20080216957
    Abstract: A cleaning method for a plasma processing apparatus includes introducing a cleaning gas containing Cl2 and N2 into the processing chamber by the gas supply mechanism; and removing aluminum-based deposits adhered to the inside of the processing chamber by generating a plasma of the cleaning gas by the plasma generating mechanism. The plasma processing apparatus includes a processing chamber for accommodating and processing a target substrate therein; a gas supply mechanism for supplying a gas into the processing chamber; a gas exhaust mechanism for evacuating the processing chamber; and a plasma generating mechanism for generating a plasma of the gas supplied in to the processing chamber.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 11, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kosuke Ogasawara, Takamichi Kikuchi
  • Patent number: 7402258
    Abstract: Methods of removing metal contaminants from a component for a plasma processing apparatus are provided. The method includes cleaning a surface of the component with a cleaning liquid that includes at least one acid selected from oxalic acid, formic acid, acetic acid, citric acid, and mixtures thereof.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: July 22, 2008
    Assignee: Lam Research Corporation
    Inventors: Mark W. Kiehlbauch, John E. Daugherty, Harmeet Singh
  • Patent number: 7381344
    Abstract: The invention teaches a multi-step method for shutting down the dry-etch process. The ICP rf power is reduced between each of these consecutive power-down steps of the dry-etch process, the complete power-down sequence consists of six steps. These six steps are executed in sequence and without interruption and form the totality of the dry-etch chamber power-down procedure.
    Type: Grant
    Filed: May 12, 1999
    Date of Patent: June 3, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chi Chin, Shy-Jay Lin
  • Patent number: 7371688
    Abstract: A process for the selective removal of a substance from a substrate for etching and/or cleaning applications is disclosed herein. In one embodiment, there is provided a process for removing a substance from a substrate comprising: providing the substrate having the substance deposited thereupon wherein the substance comprises a transition metal ternary compound, a transition metal quaternary compound, and combinations thereof; reacting the substance with a process gas comprising a fluorine-containing gas and optionally an additive gas to form a volatile product; and removing the volatile product from the substrate to thereby remove the substance from the substrate.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: May 13, 2008
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Bing Ji, Martin Jay Plishka, Dingjun Wu, Peter Richard Badowski, Eugene Joseph Karwacki, Jr.
  • Patent number: 7358196
    Abstract: Described herein are methods of forming a thin silicon dioxide layer having a thickness of less than eight angstroms on a semiconductor substrate to form the bottom layer of a gate dielectric. A silicon dioxide layer having a thickness of less than eight angstroms may be formed by two different methods. In one method, a sulfuric acid solution is applied to a semiconductor substrate to grow a silicon dioxide layer of less than eight angstroms. The growth of the silicon dioxide layer by the sulfuric acid solution is self-limiting. In another method, a hydrogen peroxide containing solution is applied to a semiconductor substrate for a time sufficient to grow a silicon dioxide layer having a thickness of greater than eight angstroms and then applying an etching solution to etch the silicon dioxide layer down to a thickness of less than eight angstroms.
    Type: Grant
    Filed: February 7, 2005
    Date of Patent: April 15, 2008
    Assignee: Applied Materials, Inc.
    Inventor: Steven Verhaverbeke
  • Patent number: 7354525
    Abstract: For a surface processing apparatus using a plasma, a mixed gas of a fluorine-containing gas and an oxygen gas is used as an ashing gas. A mixed gas of an oxygen gas and a fluorine-containing gas is introduced as an ashing gas. This allows the following steps to be carried out at the same time: removal of the silicon component left on the mask material surface and the mask material in the area including the cured mask layer and the like; and the removal of the carbon-based, and silicon-based deposits deposited on the inner wall of a vacuum chamber. In addition, the removal of the mask material is performed under low pressure, and in the subsequent step to a step using a mixed gas of a fluorine-containing gas and an oxygen gas, a plasma of only an oxygen gas is used. As a result, it becomes possible to reduce the damages (etching) to the film layer after etching.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: April 8, 2008
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Masatoshi Oyama, Yoshiyuki Ohta, Tsuyoshi Yoshida, Hironobu Kawahara
  • Patent number: 7332425
    Abstract: The present invention provides a method of forming a interconnect barrier layer 100. In the method, physical vapor deposition of barrier material 200 is performed within an opening 140 located in a dielectric layer 135 of a substrate 110. RF plasma etching of the barrier material 200 that is deposited in the opening 140 occurs simultaneously with conducting the physical vapor deposition of the barrier material 200.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: February 19, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Asad M. Haider, Alfred J. Griffin, Jr., Kelly J. Taylor
  • Patent number: 7323399
    Abstract: One embodiment of the present invention is a method for cleaning an electron beam treatment apparatus that includes: (a) generating an electron beam that energizes a cleaning gas in a chamber of the electron beam treatment apparatus; (b) monitoring an electron beam current; (c) adjusting a pressure of the cleaning gas to maintain the electron beam current at a substantially constant value; and (d) stopping when a predetermined condition has been reached.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: January 29, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Alexandros T. Demos, Khaled A. Elsheref, Josphine J. Chang, Hichem M'saad
  • Patent number: 7322368
    Abstract: A plasma cleaning gas for CVD chamber is a gas for cleaning silicon-containing deposits on the surface of a CVD chamber inner wall and the surfaces of members placed inside the CVD chamber after film forming treatment on a substrate by a plasma CVD apparatus. The cleaning gas includes 100% by volume of fluorine gas which gas can generate plasma by electric discharge. When 100% by volume of fluorine gas is plasma-generated by electric discharge and then used as a cleaning gas, an extremely excellent etching rate can be attained and further plasma can be stably generated even in the total gas flow rate of 1000 sccm and at a chamber pressure of 400 Pa. Further, the uniformity of cleaning can be also ensured in the above conditions. Additionally the fluorine gas concentration is 100% so that the apparatus is not complicated and thereby the cleaning gas has excellent practicability.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: January 29, 2008
    Inventors: Akira Sekiya, Yuki Mitsui, Yutaka Ohira, Taisuke Yonemura
  • Patent number: 7311109
    Abstract: A method for cleaning a processing chamber and manufacturing a semiconductor device by removing impurities from a substrate in the processing chamber with a plasma of a first gas including hydrogen gas. After the substrate is removed from the processing chamber, the processing chamber is etched with the plasma of a non-hydrogenous second gas. Thus, the etching selectivity can be improved and the particles are prevented from depositing and/or forming on the substrate.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: December 25, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-wook Kim, Hyeon-Deok Lee, Jin-Gi Hong, Ji-Soon Park, Eung-Joon Lee
  • Publication number: 20070238321
    Abstract: Provided is a method of manufacturing a semiconductor device. After a semiconductor wafer is placed over a wafer stage with which a dry cleaning chamber of a film forming apparatus is equipped, dry cleaning treatment is given over the surface of the semiconductor wafer with a reducing gas. Then, the semiconductor wafer is heat treated at a first temperature of from 100 to 150° C. by using a shower head kept at 180° C. The semiconductor wafer is then vacuum-transferred to a heat treatment chamber, wherein the semiconductor wafer is heat treated at a second temperature of from 150 to 400° C. A product remaining over the main surface of the semiconductor wafer is thus removed. The present invention makes it possible to manufacture a semiconductor device having improved reliability and production yield by reducing variations in the electrical properties of a nickel silicide layer.
    Type: Application
    Filed: April 10, 2007
    Publication date: October 11, 2007
    Inventors: Takuya Futase, Hideaki Tsugane, Mitsuo Kimoto, Hidenori Suzuki
  • Patent number: 7270761
    Abstract: A fluorine-free integrated process for plasma etching aluminum lines in an integrated circuit structure including an overlying anti-reflection coating (ARC) and a dielectric layer underlying the aluminum, the process being preferably performed in a single plasma reactor. The ARC open uses either BCl3/Cl2 or Cl2 and possibly a hydrocarbon passivating gas, preferably C2H4. The aluminum main etch preferably includes BCl3/Cl2 etch and C2H4 diluted with He. The dilution is particularly effective for small flow rates of C2H4. An over etch into the Ti/TiN barrier layer and part way into the underlying dielectric may use a chemistry similar to the main etch. A Cl2/O2 chamber cleaning may be performed, preferably with the wafer removed from the chamber and after every wafer cycle.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: September 18, 2007
    Assignee: Appleid Materials, Inc
    Inventors: Xikun Wang, Hui Chen, Anbei Jiang, Hong Shih, Steve S. Y. Mak
  • Patent number: 7267132
    Abstract: Described are methods, systems, and chemistries for removing layers of stubborn silicon and silicon-nitride contamination layers from the inside surfaces of such articles as deposition tubes. In such embodiments, a tube to be cleaned is gently rolled on it side while a portion the tube's interior surface is exposed to an etchant. The tube is only partially filled with etchant to reduce the requisite etchant volume, and the rolling motion evenly exposes the contaminated inner surface to the etchant.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: September 11, 2007
    Assignee: Quantum Global Technologies, LLC
    Inventor: David S. Zuck
  • Patent number: 7268089
    Abstract: A method of forming a PE-TEOS layer of a semiconductor IC device provides uniformly thick PE-TEOS layers on a batch of wafers. First, a loading wafer cassette is prepared to provide the wafers to be processed. Next, a process atmosphere is pre-created in a processing chamber. Then the wafers are supplied in sequence into the chamber from the loading wafer cassette and the wafers are mounted on a heater table in the chamber. Next, the PE-TEOS layer is deposited on the wafers by spraying a process gas into the chamber through showerheads. Next, the wafers are discharged from the chamber. Once the chamber is cleared of wafers, the inside of the chamber is cleaned by supplying a cleaning gas into the chamber, and exciting the cleaning gas with RF power. Subsequently, more TEOS gas is supplied into the chamber through the showerheads without being excited by RF power to especially reduce the temperature of the showerheads and that prevailing inside the chamber.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: September 11, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Bong-Jun Jang
  • Patent number: 7250114
    Abstract: Methods of surface finishing a component useful for a plasma processing apparatus are provided. The component includes at least one plasma-exposed quartz glass surface. The method includes mechanically polishing, chemically etching and cleaning the plasma-exposed surface to achieve a desired surface morphology. Quartz glass sealing surfaces of the component also can be finished by the methods. Plasma-exposed surface and sealing surfaces of the same component can be finished to different surface morphologies from each other.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: July 31, 2007
    Assignee: Lam Research Corporation
    Inventors: Mark W. Kiehlbauch, John E. Daugherty
  • Patent number: 7234476
    Abstract: A method of remote plasma cleaning a processing chamber of CVD equipment, which has high cleaning rates, low cleaning operational cost and high efficiency, is provided. The method comprises supplying cleaning gas to the remote plasma-discharge device; activating the cleaning gas inside the remote plasma-discharge device; and bringing the activated cleaning gas into the processing chamber and which is characterized in that a mixed gas of F2 gas and an inert gas are used as the cleaning gas. A concentration of the F2 gas is 10% or higher. The F2 gas, which is a cleaning gas, is supplied to the remote plasma-discharge device from an F2 gas cylinder by diluting F2 gas at a given concentration by an inert gas.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: June 26, 2007
    Assignee: ASM Japan K.K.
    Inventors: Hirofumi Arai, Hideaki Fukuda
  • Patent number: 7223446
    Abstract: In a parallel flat plate type plasma CVD apparatus, plasma damage of constituent parts in a reaction chamber due to irregularity of dry cleaning in the reaction chamber is reduced and the cost is lowered. In the parallel flat plate type plasma CVD apparatus in which high frequency voltages of pulse waves having mutually inverted waveforms are applied to an upper electrode and a lower electrode, and the inversion interval of the pulse wave can be arbitrarily changed, the interior of the reaction chamber is dry cleaned.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: May 29, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Mitsuhiro Ichijo
  • Patent number: 7211518
    Abstract: A method for forming features in dielectric layers and opening barrier layers for a plurality of wafers and cleaning an etch chamber after processing and removing each wafer of the plurality of wafers is provided. A wafer of the plurality of wafers is placed into the etch chamber wherein the wafer has a barrier layer over the wafer and a dielectric layer over the barrier layer. The dielectric layer is etched. The barrier layer is opened. The wafer is removed from the etch chamber. A waferless automatic cleaning of the etch chamber without the wafer is provided. The waferless automatic cleaning comprises providing a waferless automatic cleaning gas comprising oxygen and nitrogen to the etch chamber and forming a waferless automatic cleaning plasma from the waferless automatic cleaning gas to clean the etch chamber.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: May 1, 2007
    Assignee: Lam Research Corporation
    Inventors: Xiaoqiang Sean Yao, Bi-Ming Yen, Taejoon Han, Peter Loewenhardt
  • Patent number: 7207339
    Abstract: A method for plasma cleaning a CVD reactor chamber including providing a plasma enhanced CVD reactor chamber comprising residual deposited material; performing a first plasma process comprising an oxygen containing plasma; performing a second plasma process comprising an argon containing plasma; and, performing a third plasma process comprising a fluorine containing plasma.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: April 24, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Wen Chen, Shiu-Ko Jangjian, Hung-Jui Chang, Ying-Lang Wang
  • Patent number: 7201174
    Abstract: In a chamber (11), a SiOF film is formed on a wafer W using a plasma CVD method. A film remaining inside the chamber (11) is cleaned up using a gas containing NF3. A manometer (28) is prepared for the chamber (11). An end point of cleaning of the chamber (11) is detected by monitoring the pressure inside the chamber (11).
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: April 10, 2007
    Assignee: Tokyo Electron Limited
    Inventor: Noriaki Fukiage
  • Patent number: 7201807
    Abstract: Disclosed are a method for cleaning a deposition chamber by removing attached metal oxides, and a deposition apparatus for performing in situ cleaning. A first gas and a second gas are provided into the deposition chamber. The first gas is reacted with metal included in the metal oxide to generate reacting residues. The second gas then decomposes the reacting residues, and the decomposed residues are exhausted out of the chamber. Thus, this cleaning process can be rapidly accomplished while the deposition chamber is not opened or separated from a deposition apparatus.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: April 10, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Taek Yim, Young-Wook Park, In-Sung Park, Han-Mei Choi, Kyoung-Seok Kim
  • Patent number: 7202099
    Abstract: Provided is a method of fabricating a laser diode including a lower Al-containing semiconductor material layer, a active layer, and an upper Al-containing semiconductor material layer. The method includes thermally cleaning the inside of a deposition reactor in which a substrate on which the lower Al-containing semiconductor material layer is stacked is loaded. During the thermal cleaning process, the inside of the deposition reactor is thermally treated at a predetermined temperature in an atmosphere of a gas mixture of AsH3 and H2 that is injected into the deposition reactor.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: April 10, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-sung Kim, Yong-jo Park
  • Patent number: 7182819
    Abstract: Methods for cleaning a chamber of semiconductor device manufacturing equipment are disclosed. An illustrated method comprises supplying cleaning gas into a chamber to start a cleaning process; detecting the intensity of a wavelength for the cleaning gas; fixing a valve at a predetermined position to control the pressure in the chamber; detecting the pressure in the chamber during some period of the cleaning time, the cleaning time being from the beginning of the cleaning process to the time when the intensity of the wavelength is settled at a predetermined value; and stopping supplying the cleaning gas into the chamber to complete the cleaning process.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: February 27, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Seung Chul Choi
  • Patent number: 7168436
    Abstract: The invention relates to a gas for removing deposits by a gas-solid reaction. This gas includes a hypofluorite that is defined as being a compound having at least one OF group in the molecule. Various deposits can be removed by the gas, and the gas can easily be made unharmful on the global environment after the removal of the deposits, due to the use of a hypofluorite. The gas may be a cleaning gas for cleaning, for example, the inside of an apparatus for producing semiconductor devices. This cleaning gas comprises 1–100 volume % of the hypofluorite. Alternatively, the gas of the invention may be an etching gas for removing an unwanted portion of a film deposited on a substrate. The unwanted portion can be removed by this etching gas as precisely as originally designed, due to the use of a hypofluorite. The invention further relates to a method for removing a deposit by the gas.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: January 30, 2007
    Assignee: Central Glass Company, Limited
    Inventors: Isamu Mouri, Tetsuya Tamura, Mitsuya Ohashi
  • Patent number: 7163849
    Abstract: Upon formation of an impurity-added silicon film by a low-pressure CVD apparatus, diffusion of an impurity from another similar silicon film, which has already been formed over the inside walls of the deposition chamber, is suppressed in the following manner. After insertion of a semiconductor substrate, having a gate oxide film (insulating film) formed thereover, into the deposition chamber of a CVD apparatus (first film forming apparatus), the inside of the deposition chamber is heated while minimizing, relative to a time A required for heating of the inside of the deposition chamber under atmospheric pressure, a time B required for the subsequent heating in the deposition chamber under a pressure adjusted to vacuum or not greater than atmospheric pressure. The formation of an impurity-added silicon film is then started. At this time, the relation between A and B is controlled to satisfy the following equation: 0.1×B?A?13×B.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: January 16, 2007
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Renesas Northern Japan Semiconductor, Inc.
    Inventors: Hiroaki Kikuchi, Toshiaki Sawada, Hirohiko Yamamoto
  • Patent number: 7159597
    Abstract: A process for removing unwanted deposition build-up from one or more interior surfaces of a substrate processing chamber after depositing a layer of material over a substrate disposed in the chamber. In one embodiment the process comprises transferring the substrate out of the chamber; flowing a first gas into the substrate processing chamber and forming a plasma within the chamber from the first gas in order to heat the chamber; and thereafter, extinguishing the plasma, flowing an etchant gas into a remote plasma source, forming reactive species from the etchant gas and transporting the reactive species into the substrate processing chamber to etch the unwanted deposition build-up.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: January 9, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Zhong Qiang Hua, Zhengquan Tan, Zhuang Li, Kent Rossman
  • Patent number: 7156923
    Abstract: A thermal processing system (1) includes a reaction vessel (2) capable of forming a silicon nitride film on semiconductor wafers (10) through interaction between hexachlorodisilane and ammonia, and an exhaust pipe (16) connected to the reaction vessel (2). The reaction vessel 2 is heated at a temperature in the range of 500 to 900° C. and the exhaust pipe (16) is heated at 100° C. before disassembling and cleaning the exhaust pipe 16. Ammonia is supplied through a process gas supply pipe (13) into the reaction vessel (2), and the ammonia is discharged from the reaction vessel (2) into the exhaust pipe (16).
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: January 2, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Hitoshi Kato, Kohei Fukushima, Atsushi Endo, Tatsuo Nishita, Takeshi Kumagai
  • Patent number: 7150796
    Abstract: In a method of affecting cleaning or chamber process control to remove residues of fluorinated discharges from internal PECVD chamber hardware during manufacture of a semiconductor or integrated circuit, the improvement of removing the fluorinated discharges without opening the chamber and without causing chamber downtime, comprising: a) maximizing H-atom concentration in a gas mix of a plasma containing H2 through the use of high rf power and low pressure to obtain an in-situ H2 plasma; and b) subjecting a reactor chamber containing build-up residues from previous chamber treatment with a fluorinated plasma, with the in-situ H2 plasma from step a) without opening the chamber and without shutting down the chamber to remove the build-up residues of the fluorinated plasma.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: December 19, 2006
    Assignee: Infineon Technologies Richmond, LP
    Inventors: Bradley C. Smith, David James
  • Patent number: 7141512
    Abstract: A semiconductor device fabrication apparatus is cleaned after a conductive layer is formed on a metal oxide layer of a substrate. The substrate is disposed on a heater in a process chamber of the apparatus, and the conductive layer is formed by introducing source gases into the chamber. Then the substrate is transferred out of the process chamber. At least one by-product of a reaction between the source gases and the metal oxide layer adheres to a surface inside the chamber, such as to a region or regions of the heater. Once the semiconductor substrate has been transferred outside the process chamber of the semiconductor fabrication apparatus, the by-product(s) is/are removed by evaporation. The by-product(s) can be evaporated using gas, such as one of the source gases, so that the process chamber can remain closed.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: November 28, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-su Ha, Yoon-bon Koo, Hyun-seok Lim, Cheon-su Han, Seung-cheol Choi
  • Patent number: 7140374
    Abstract: A method for cleaning a processing chamber that includes heating an inner surface of the processing chamber to a first temperature. The first temperature can be sufficient to cause a first species to become volatile. The first species can be one of several species deposited on the inner surface. A cleaning chemistry is injected into the processing chamber. The cleaning chemistry can be reactive with a second one of the species to convert the second species to the first species. The volatilized first species can also be output from the processing chamber. A system for cleaning the process chamber is also described.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: November 28, 2006
    Assignee: Lam Research Corporation
    Inventors: Andrew D. Bailey, III, Shrikant P. Lohokare, Arthur M. Howald, Yunsang Kim
  • Patent number: 7125583
    Abstract: A method for improving thickness uniformity and throughput of a carbon doped oxide deposition process is described. That method comprises removing pre-deposition steps in a deposition phase. Moreover, helium plasma is added to a pre-clean phase to eliminate the production of dummy wafers.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: October 24, 2006
    Assignee: Intel Corporation
    Inventors: Ebrahim Andideh, Kevin L. Peterson, Jeff Bielefeld
  • Patent number: 7121286
    Abstract: A method for cleaning a manufacturing apparatus, includes introducing a cleaning gas including fluorine so as to flow from upstream toward an outlet port in a reaction chamber; and flowing a protective gas which reacts with the fluorine from a vicinity of the outlet port of the reaction chamber as an introduction position.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: October 17, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Nakao
  • Patent number: 7112546
    Abstract: The present invention provides, in one embodiment, a method of manufacturing semiconductor devices. The method comprises transferring one or more substrate into a deposition chamber and depositing material layers on the substrate. The chamber has an interior surface. The method further includes, between the transfers, cleaning the deposition chamber using an in situ ramped cleaning process when material layer deposits in the deposition chamber reaches a predefined thickness. The in situ ramped cleaning process comprises forming a reactive plasma cleaning zone by dissociating a gaseous fluorocompound introduced into a deposition chamber in a presence of a plasma. The cleaning process further includes ramping a flow rate of the gaseous fluorocompound in a presence of the plasma to move the reactive plasma cleaning zone throughout the deposition chamber, thereby preventing a build-up of localized metal compound deposits on the interior surface.
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: September 26, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Ignacio Blanco, Jin Zhao, Nathan Kruse
  • Patent number: 7110845
    Abstract: Manufacturing equipment performs different processes, including a first process that produces a reaction products and a second process that removes the reaction products, in a same chamber. The amount of reaction products in the chamber is monitored, and a priority order between the first and the second processes is set based on the monitored amount of the reaction products. The order of the first and the second processes is determined based on the set priority order. The amount of reaction products can be kept within an acceptable range without performing a long-period lot-to-lot cleaning, and a high manufacturing efficiency is realized.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: September 19, 2006
    Assignee: Kawasaki Microelectronics, Inc.
    Inventor: Koji Suzuki