Abstract: Silicon carbide films are grown by carburization of silicon to form insulative films. In one embodiment, the film is used to provide a gate insulator for a field effect transistor. The film is grown in a microwave-plasma-enhanced chemical vapor deposition (MPECVD) system. A silicon substrate is fast etched in dilute HF solution and rinsed. The substrate is then placed in a reactor chamber of the MPECVD system in hydrogen along with a carbon containing gas. The substrate is then inserted into a microwave generated plasma for a desired time to grow the film. The microwave power varies depending on substrate size. The growth of the film may be continued following formation of an initial film via the above process by using a standard CVD deposition of amorphous SiC. The film may be used to form gate insulators for FET transistors in DRAM devices and flash type memories. It may be formed as dielectric layers in capacitors in the same manner.

Abstract: Methods and apparatus for depositing low dielectric constant layers that are resistant to oxygen diffusion and have low oxygen contents are provided. The layers may be formed by exposing a low dielectric constant layer to a plasma of an inert gas to densify the low dielectric constant layer, by exposing the low dielectric constant layer to a nitrating plasma to form a passivating nitride surface on the layer, or by depositing a thin passivating layer on the low dielectric constant layer to reduce oxygen diffusion therein. The low dielectric constant layer may be deposited and treated in situ.

Abstract: Films of gallium manganese nitride are grown on a substrate by molecular beam epitaxy using solid source gallium and manganese and a nitrogen plasma. Hydrogen added to the plasma provides improved uniformity to the film which may be useful in spin-based electronics.

Abstract: A localised reduced lifetime region (1,25,41) is provided in a semiconductor device formed substantially of silicon. A predetermined concentration of carbon is provided in the region, and then the body is heated to incorporate a lifetime controlling impurity substantially within the carbon region. It is believed that the association between the impurity ions (M+) and the carbon atoms (C) on silicon lattice sites produces C-M+ complexes with significant capture cross-sections. The carbon may be provided by addition during epitaxial growth of silicon material, during bulk growth of the silicon, or by implantation and/or diffusion.

Abstract: Hermetic amorphous doped silicon carbide is deposited on an integrated circuit substrate in a PECVD reactor. Nitrogen-doping of an SiC film is conducted by flowing nitrogen-containing molecules, preferably nitrogen or ammonia gas, into the reactor chamber together with an organosilane, preferably tetramethylsilane, and forming a plasma. Oxygen-doping is conducted by flowing oxygen-containing molecules into the reaction chamber.

Abstract: A method is disclosed for treating a silicon carbide substrate for improved epitaxial deposition thereon and for use as a precursor in the manufacture of devices such as light emitting diodes. The method includes the steps of implanting dopant atoms of a first conductivity type into the first surface of a conductive silicon carbide wafer having the same conductivity type as the implanting ions at one or more predetermined dopant concentrations and implant energies to form a dopant profile, annealing the implanted wafer, and growing an epitaxial layer on the implanted first surface of the wafer.

Abstract: A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a dopant in the presence of an electric field. The as-deposited silicon carbide layer has a compressibility that varies as a function of the amount of dopant present in the gas mixture during later formation.

Abstract: A CMOS-compatible FET has a reduced electron affinity polycrystalline or microcrystalline SiC gate that is electrically isolated (floating) or interconnected. The SiC material composition is selected to establish the barrier energy between the SiC gate and a gate insulator. In a memory application, such as a flash EEPROM, the SiC composition is selected to establish a lower barrier energy to reduce write and erase voltages and times or accommodate the particular data charge retention time needed for the particular application. In a light detector or imaging application, the SiC composition is selected to provide sensitivity to the desired wavelength of light. Unlike conventional photodetectors, light is absorbed in the floating gate, thereby ejecting previously stored electrons therefrom. Also unlike conventional photodetectors, the light detector according to the present invention is actually more sensitive to lower energy photons as the semiconductor bandgap is increased.

Abstract: Ohmic contact formation on p-type Silicon Carbide is disclosed. The formed contact includes an initial amorphous Carbon film layer converted to graphitic sp2 Carbon during an elevated temperature annealing sequence. Decreased annealing sequence temperature, reduced Silicon Carbide doping concentration and reduced specific resistivity in the formed ohmic contact are achieved with respect to a conventional p-type Silicon Carbide ohmic contact. Addition of a Boron carbide layer covering the p-type Silicon Carbide along with the sp2 Carbon is also disclosed. Ohmic contact improvement with increased annealing temperature up to an optimum temperature near 1000° C. is included. Addition of several metals including Aluminum, the optimum metal identified, over the Carbon layer is also included; many other of the identified metals provide Schottky rather than the desired ohmic contacts, however.

Abstract: A structure and method for a voltage blocking device comprises a cathode region, a drift region positioned on the cathode region, a gate region positioned on the drift region, an anode region positioned on the gate region and a plurality of contacts positioned on each of the cathode region, the gate region, and the anode region, wherein the drift region comprises multiple epilayers having first doped type layers surrounding second doped type layers, wherein dopant concentrations of the first doped type layers are lower than dopant concentrations of the second doped type layers. The epilayers comprise at least one i-n-i layer and/or at least one i-p-i layer. Moreover, the multiple epilayers are operable to block voltages in the device.

Abstract: A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.

Abstract: A method for forming a silicon carbide film on a semiconductor substrate by plasma CVD includes (a) introducing a raw material gas containing silicon, carbon, and hydrogen and an inert gas into a reaction chamber at a predetermined mixture ratio of the raw material gas to the inert gas; (b) applying radio-frequency power at the mixture ratio, thereby forming a curable silicon carbide film having a dielectric constant of about 4.0 or higher; and (c) continuously applying radio-frequency power at a mixture ratio which is reduced from that in step (b), thereby curing the silicon carbide film to give a dielectric constant lower than that of the curable silicon carbide film.

Abstract: A method of separating two layers of material from one another in such a way that the two separated layers of material are essentially fully preserved. An interface between the two layers of material at which the layers of material are to be separated, or a region in the vicinity of the interface, is exposed to electromagnetic radiation through one of the two layers of material. The electromagnetic radiation is absorbed at the interface or in the region in the vicinity of the interface and the absorbed radiation energy induces a decomposition of material at the interface.

Abstract: A nanowire, nanosphere, metallized nanosphere, and methods for their fabrication are outlined. The method of fabricating nanowires includes fabricating the nanowire under thermal and non-catalytic conditions. The nanowires can at least be fabricated from metals, metal oxides, metalloids, and metalloid oxides. In addition, the method of fabricating nanospheres includes fabricating nanospheres that are substantially monodisperse. Further, the nanospheres are fabricated under thermal and non-catalytic conditions. Like the nanowires, the nanospheres can at least be fabricated from metals, metal oxides, metalloids, and metalloid oxides. In addition, the nanospheres can be metallized to form metallized nanospheres that are capable as acting as a catalyst.

Abstract: A method of epitaxially growing a SiC film on a Si substrate, including:

Abstract: Provided are a compound semiconductor crystal substrate capable of reducing planar defects such as twins and anti-phase boundaries occurring in epitaxially grown crystals without additional steps beyond epitaxial growth, and a method of manufacturing the same. A compound single crystal substrate, the basal plane of which is a nonpolar face, with said basal plane having a partial surface having polarity (a partial polar surface). Said partial polar surface is a polar portion of higher surface energy than said basal plane.

Abstract: Semiconductor power devices with improved electrical characteristics are disclosed including rectifying contacts on a specially prepared semiconductor surface with little or no additional exposure to other chemical treatments, with oxide passivation and edge termination at a face of the semiconductor substrate adjacent to and surrounding the power device. The edge termination region is preferably formed by implanting electrically inactive ions, such as argon, into the substrate face at sufficient energy and dose to amorphize a portion of the substrate face and preferably self-aligned to the device. The passivated, edge-terminated devices exhibit improved characteristics relative to passivated devices with characteristics approaching those of the native semiconductor with the additional advantages of passivation protection. Methods for making and using the devices are also disclosed.

Abstract: There are provided an electric part which can be produced through a production process which is excellent in an industrial productivity and a method of manufacturing the electric part, by including a matrix-shaped nonconductive base member, a carbon nanotube group that is sealed within the nonconductive base member and includes one carbon nanotube or plural carbon nanotubes which are electrically connected to each other, in which substantially only end portion of the one carbon nanotube or at least one carbon nanotube contained in the plural carbon nanotubes is exposed from one surface of the nonconductive base member, and an electrode that is connected to a side surface of the at least one carbon nanotube contained in the carbon nanotube group.

Abstract: A semiconductor component has a plurality of GaN-based layers, which are preferably used to generate radiation, produced in a fabrication process. In the process, the plurality of GaN-based layers are applied to a composite substrate that includes a substrate body and an interlayer. A coefficient of thermal expansion of the substrate body is similar to or preferably greater than the coefficient of thermal expansion of the GaN-based layers, and the GaN-based layers are deposited on the interlayer. The interlayer and the substrate body are preferably joined by a wafer bonding process.

Abstract: A method of manufacturing a semiconductor device includes the steps of: (X) forming a first hydrophobic insulating layer above a semiconductor substrate; (Y) hydrophilizing a surface of the first hydrophobic insulating layer; and (Z) forming a low dielectric constant insulating layer having a specific dielectric constant lower than the specific dielectric constant of silicon oxide on the first hydrophobic insulating layer having a bydrophilized surface. A semiconductor device manufacturing method which can suppress peel-off of a low dielectric constant insulating layer from an underlying hydrophobic layer is provided.

Abstract: Semiconductor devices useful in high temperature sensing applications include a silicon carbide substrate, a silicon dioxide layer, and an outer layer of crystalline doped silicon carbide. The device is a 3C—SiC/SiO2/SiC structure. This structure can be employed to fabricate high temperature devices such as piezoresistive sensors, minority carrier devices and so on. The crystalline doped silicon carbide is dielectrically isolated from the substrate. The devices are formed by processes that include bonding a pattern wafer to a substrate wafer, selective oxidation and removal of undoped silicon, and conversion of doped silicon to crystalline silicon carbide. The level of doping and the crystalline structure of the silicon carbide can be selected according to desired properties for particular applications.

Abstract: The present invention is directed to a silicon carbide anti-reflective coating (ARC) and a silicon oxycarbide ARC. Another embodiment is directed to a silicon oxycarbide ARC that is treated with oxygen plasma. The invention includes method embodiments for forming silicon carbide layers and silicon oxycarbide layers as ARC's on a semiconductor substrate surface. Particularly, the methods include introducing methyl silane materials into a process chamber where they are ignited as plasma and deposited onto the substrate surface as silicon carbide. Another method includes introducing methyl silane precursor materials with an inert carrier gas into the process chamber with oxygen. These materials are ignited into a plasma, and silicon oxycarbide material is deposited onto the substrate. By regulating the oxygen flow rate, the optical properties of the silicon oxycarbide layer can be adjusted. In another embodiment, the silicon oxycarbide layer can be treated with oxygen plasma.

Abstract: An opaque, low resistivity silicon carbide and a method of making the opaque, low resistivity silicon carbide. The opaque, low resistivity silicon carbide is a free-standing bulk material that may be machined to form furniture used for holding semi-conductor wafers during processing of the wafers. The opaque, low resistivity silicon carbide is opaque at wavelengths of light where semi-conductor wafers are processed. Such opaqueness provides for improved semi-conductor wafer manufacturing. Edge rings fashioned from the opaque, low resistivity silicon carbide can be employed in RTP chambers.

Abstract: In a SiC substrate (10), a first active region (12) composed of n-type heavily doped layers (12a) and undoped layers (12b), which are alternately stacked, and a second active region (13) composed of p-type heavily doped layers (13a) and undoped layers (13b), which are alternately stacked, are provided upwardly in this order. A Schottky diode (20) and a pMOSFET (30) are provided on the first active region (12). An nMOSFET (40), a capacitor (50), and an inductor (60) are provided on the second active region (13). The Schottky diode (20) and the MOSFETs (30, 40) have a breakdown voltage characteristic and a carrier flow characteristic due to a multilayer structure composed of &dgr;-doped layers and undoped layers and are integrated in a common substrate.

Abstract: Edge termination for a silicon carbide Schottky rectifier is provided by including a silicon carbide epitaxial region on a voltage blocking layer of the Schottky rectifier and adjacent a Schottky contact of the silicon carbide Schottky rectifier. The silicon carbide epitaxial layer may have a thickness and a doping level so as to provide a charge in the silicon carbide epitaxial region based on the surface doping of the blocking layer. The silicon carbide epitaxial region may form a non-ohmic contact with the Schottky contact. The silicon carbide epitaxial region may have a width of from about 1.5 to about 5 times the thickness of the blocking layer. Schottky rectifiers with such edge termination and methods of fabricating such edge termination and such rectifiers are also provided. Such methods may also advantageously improve the performance of the resulting devices and may simplify the fabrication process.

Abstract: To produce a SiC crystal in a shape which is used as a wafer, a guide is disposed around a SiC crystal substrate so as to cover a peripheral portion of the SiC crystal substrate. Temperature of the guide may be made higher than the sublimation temperature of the SiC when a SiC crystal is disposed upon and caused to grow on the SiC crystal substrate, thereby controlling and restricting the SiC crystal growth in the direction of the guide. Additionally, when the guide is formed in a substantially hexagonal tube shape, the SiC crystal can be produced in a hexagonal pole shape. In this case, when alignment is made between each diagonal passing through a center of the hexagon shape of the guide and specific direction (<11{overscore (2)}0> or <1{overscore (1)}00> of the SiC crystal substrate), the SiC crystal becomes aligned accordingly.

Abstract: A semiconductor configuration with ohmic contact-connection includes a first and a second semiconductor region made of silicon carbide, each having a different conduction type. A first and a second contact region serve for contact-connection. The first contact region and the second contact region have an at least approximately identical material composition which is practically homogeneous within the respective contact region. A method is provided for contact-connecting n-conducting and p-conducting silicon carbide, in each case with at least approximately identical material.

Abstract: J-FET having a first semiconductor region (2, 3), which comprises a first contact (7) with a highly doped contact layer (8) serving as a source disposed between two second contacts (9) serving as a gate on its first surface (4). The three contacts (7, 9) are each connected to a respective second semiconductor region (5, 6). The first and second semiconductor regions (2, 3, 5, 6) are of opposite conductivity types. The second semiconductor regions (5) connected to the second contacts (9) extend in the first semiconductor region (2, 3) below the second semiconductor region (6) that is connected to the first contact (7), with the result that the three second semiconductor regions (5, 6) at least partially overlap in a projection onto a horizontal plane and a channel region (11) is formed between the three second semiconductor regions (5, 6) in the first semiconductor region (2, 3).

Abstract: Semiconductor devices useful in high temperature sensing applications include a silicon carbide substrate, a silicon dioxide layer, and an outer layer of crystalline doped silicon carbide. The device is a 3C-SiC/SiO2/SiC structure. This structure can be employed to fabricate high temperature devices such as piezoresistive sensors, minority carrier devices and so on. The crystalline doped silicon carbide is dielectrically isolated from the substrate. The devices are formed by processes that include bonding a pattern wafer to a substrate wafer, selective oxidation and removal of undoped silicon, and conversion of doped silicon to crystalline silicon carbide. The level of doping and the crystalline structure of the silicon carbide can be selected according to desired properties for particular applications.

Abstract: A semiconductor substrate with integrated circuit devices on its front side and a high thermal conductivity layer such as diamond on its back side, with components such as capacitors embedded in the high thermal conductivity layer and coupled to the front side integrated circuits with vias through the substrate.

Abstract: This invention relates semiconductor devices incorporating an intermediate etch stop layer between two dielectric layers in which the dielectric constant of each of the layers is k≦3.5 and the etch stop layer has a selectivity of at least 2.5:1 relative to the upper layer. Methods and apparatus for forming nitrogen doped silicon carbide films, for example, for use as etch stop layers are described.

Abstract: A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.

Abstract: Hermetic amorphous doped silicon carbide is deposited on an integrated circuit substrate in a PECVD reactor. Nitrogen-doping of an SiC film is conducted by flowing nitrogen-containing molecules, preferably nitrogen or ammonia gas, into the reactor chamber together with an organosilane, preferably tetramethylsilane, and forming a plasma. Oxygen-doping is conducted by flowing oxygen-containing molecules into the reaction chamber.

Abstract: A silicon carbide lateral metal-oxide-semiconductor field-effect transistor (SiC LMOSFET) having a self-aligned drift region and method for forming the same is provided. Specifically, the SiC LMOSFET includes a source region, a drift region and a drain region. The source and drain regions are implanted using non self-aligned technology (i.e., prior to formation of the gate electrode and the gate oxide layer), while the drift region is implanted using self-aligned technology (i.e., after formation of the gate electrode and the gate oxide layer). By self-aligning the drift region to the gate electrode, the overlap between the two is minimized, which reduces the capacitance of the device. When capacitance is reduced, performance is improved.

Abstract: Silicon carbide semiconductor power devices having epitaxially grown guard rings edge termination structure are provided. Forming the claimed guard rings from an epitaxially grown SiC layer avoids the traditional problems associated with implantation of guard rings, and permits the use of self aligning manufacturing techniques for making the silicon carbide semiconductor power devices.

Abstract: A structure and method for creating an integrated circuit passivation structure including, a circuit, a dielectric, and metal plates over which an insulating layer is disposed that electrically isolates the circuit, and a discharge layer that is deposited to form the passivation structure that protects the circuit from electrostatic discharges caused by, e.g., a finger, is disclosed. The discharge layer additionally contains dopants selectively deposited to increase electrostatic discharge carrying capacity while maintaining overall sensing resolution.

Abstract: Methods of constructing silicon carbide semiconductor devices in a self-aligned manner. According to one aspect of the invention, the method may include forming a mesa structure in a multi-layer laminate including at least a first and second layer of silicon carbide material. The mesa structure may then be utilized in combination with at least one planarization step to construct devices in a self-aligned manner. According to another aspect of the present invention, the mesa structure may be formed subsequent to an ion implantation and anneal steps to construct devices in a self-aligned manner. According to another aspect of the present invention, a high temperature mask capable of withstanding the high temperatures of the anneal process may be utilized to form devices in a self-aligned manner.

Abstract: A method for forming a strain layer on an underside of a channel in an MOS transistor in order to produce a mechanical stress in the channel, increasing a mobility of carriers in the channel and an apparatus produced from such a method.

Abstract: The present invention is related to a method for removal of silicon carbide layers and in particular amorphous SiC of a substrate. Initially, the exposed part of a carbide-silicon layer is at least partly converted into an oxide-silicon layer by exposing the carbide-silicon layer to an oxygen containing plasma. The oxide-silicon layer is then removed from the substrate.

Abstract: A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled pocket implant, the edge blocking material (24) blocks some dopant from entering the semiconductor body (10) and the dopant (18) placed under the edge blocking material is located at a given distance below the surface of the semiconductor body (10).

Abstract: A semiconductor device, comprising: a semiconductor substrate comprising silicon carbide of a first conductivity type; a silicon carbide epitaxial layer of the first conductivity type; a first semiconductor region formed on the semiconductor substrate and comprising silicon carbide of a second conductivity type; a second semiconductor region formed on the first semiconductor region, comprising silicon carbide of the first conductivity type and separated from the semiconductor substrate of the first conductivity type by the first semiconductor region; a third semiconductor region formed on the semiconductor region, connected to the semiconductor substrate and the second semiconductor region, comprising silicon carbide of the first conductivity type, and of higher resistance than the semiconductor substrate; and a gate electrode formed on the third semiconductor region via an insulating layer; wherein the third semiconductor layer is depleted when no voltage is being applied to the gate electrode so that said s

Abstract: A method of preparing a semiconductor using ion implantation comprises: (a) providing a first material comprising (i) a first Si wafer, (ii) at least one indigenous SiC layer, (iii) at least one non-indigenous SiC layer applied to the indigenous SiC layer, and (iv) at least one oxide layer applied to the non-indigenous SiC layer; (b) implanting ions in the non-indigenous SiC layer, thereby establishing an implant region which defines first and second portions of the non-indigenous SiC layer; (c) providing another material comprising (i) a second Si wafer, and (ii) an oxide layer applied to a face of the second wafer; (d) providing an assembly by bonding the oxide layers of the first material and the other material; and (e) separating the first and second portions of the non-indigenous SiC layer at the implant region.

Abstract: Semiconductor devices useful in high temperature sensing applications include a silicon carbide substrate, a silicon dioxide layer, and an outer layer of crystalline doped silicon carbide. The device is a 3C—SiC/SiO2/SiC structure. This structure can be employed to fabricate high temperature devices such as piezoresistive sensors, minority carrier devices and so on. The crystalline doped silicon carbide is dielectrically isolated from the substrate. The devices are formed by processes that include bonding a pattern wafer to a substrate wafer, selective oxidation and removal of undoped silicon, and conversion of doped silicon to crystalline silicon carbide. The level of doping and the crystalline structure of the silicon carbide can be selected according to desired properties for particular applications.

Abstract: Openings are formed in a laminate of a polycrystalline silicon film and an LTO film on a channel layer. While the laminate is used as a mask, impurities are implanted into a place in the channel layer which is assigned to a source region. Also, impurities are implanted into another place in the channel layer which is assigned to a portion of a second gate region. A portion of the polycrystalline silicon film which extends from the related opening is thermally oxidated. The LTO film and the oxidated portion of the polycrystalline silicon film are removed. While a remaining portion of the polycrystalline silicon film is used as a mask, impurities are implanted into a place in the channel layer which is assigned to the second gate region. Accordingly, the source region and the second gate region are formed on a self-alignment basis which suppresses a variation in channel length.

Abstract: A method for bonding diamond heat distribution structures to integrated circuit packages using optical contacting. In one embodiment, a heat spreader comprising diamond slab has a flat contact surface which is polished to a high degree of smoothness. An integrated circuit's package also has a flat contact surface which is polished to a high degree of smoothness. The contact surfaces of the diamond slab and the package are thoroughly cleaned and are then placed in contact with each other, establishing an optical contact bond between them. In one embodiment, the contact surfaces of the diamond and package which are to be bonded together are first polished, then a layer of an intermediate material such as silicon carbide is deposited on the polished surfaces. The silicon carbide layers on the contact surfaces are cleaned and placed in contact with each other to establish an optical contact bond.

Abstract: A silicon semiconductor die comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conduction type disposed on the substrate. The upper layer comprises a well region of a second, opposite conduction type adjacent an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon. Both the well region and adjacent edge termination zone are disposed at an upper surface of the upper layer, and an oxide layer overlies the upper layer and the edge termination zone. A process for forming a silicon die having improved edge termination. The process comprises forming an upper layer comprising doped silicon of a first conduction type on a heavily doped silicon substrate, and forming an edge termination zone that comprises a layer of a material having a higher critical electric field than silicon at an upper surface of the upper layer.

Abstract: Light emitting device die having a mesa configuration on a substrate and an electrode on the mesa are attached to a submount in a flip-chip configuration by forming predefined pattern of conductive die attach material on at least one of the electrode and the submount and mounting the light emitting device die to the submount. The predefined pattern of conductive die attach material is selected so as to prevent the conductive die attach material from contacting regions of having opposite conductivity types when the light emitting device die is mounted to the submount. The predefined pattern of conductive die attach material may provide a volume of die attach material that is less than a volume defined by an area of the electrode and a distance between the electrode and the submount. Light emitting device dies having predefined patterns of conductive die attach material are also provided.

Abstract: A method of fabricating a compound semiconductor device having an ohmic electrode of a low contact potential includes a first cleaning step of heating a compound semiconductor substrate containing a first conductivity type impurity in a temperature range of not more than 250° C. and etching its surface with hydrogen chloride at the temperature of not more than 250° C., and a second cleaning step of performing a radical hydrotreatment on the compound semiconductor substrate at a temperature not more than 250° C., after the first cleaning step. The first cleaning step removes an oxide film but leaves chlorine on the surface of the substrate. The second cleaning step removes the chlorine. The temperature of not more than 250° C. avoids damaging other layers such as an active layer on the opposite surface of the substrate.

Abstract: A pressure sensor is prepared by:

Abstract: Improved etch selectivity, barrier metal wetting and reduced interconnect capacitance are achieved by implementing damascene processing employing a graded middle etch stop layer comprising a first silicon carbide layer, a silicon-rich layer on the first silicon carbide, and a second silicon carbide layer on the silicon-rich layer. Embodiments include sequentially depositing a porous low-k dielectric layer over a lower capped Cu line, depositing the graded middle-etch stop layer, depositing a porous low-k dielectric layer on the graded middle-etch stop layer, forming a dual damascene opening exposing the silicon-rich surface at the bottom of the trench opening, depositing a seed layer, depositing a barrier middle layer, such as Ta or a Ta/TaN composite, and filling the opening with Cu.