Abstract: An aspect of the present invention includes a first conductive type semiconductor region formed in a semiconductor substrate, a gate electrode formed on the first conductive type semiconductor region, a channel region formed immediately below the gate electrode in the first conductive type semiconductor region, and a second conductive type first diffusion layers constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which the germanium concentration of at least one of the source side and the drain side is higher than that of the central portion.

Abstract: A semiconductor substrate, a field effect transistor and their manufacturing methods provided with, in order to lower penetrating dislocation density and reduce surface roughness to a practical level, an Si substrate 1, a first SiGe layer 2 on the Si substrate, and a second SiGe layer 3 arranged on the first SiGe layer either directly or with an Si layer in between; wherein, the first SiGe layer has a film thickness that is thinner than twice the critical film thickness, which is the film thickness at which dislocation occurs resulting in lattice relaxation due to increased film thickness, the Ge composition ratio of the second SiGe layer is at least lower than the intralayer maximum value of the Ge composition ratio in the first SiGe layer or in the first SiGe layer at the contact surface with the Si layer, and the second SiGe layer has an incremental composition region in which the Ge composition ratio gradually increases towards the surface at least in a portion thereof.

Abstract: A method of estimating substrate temperature according to this invention includes the steps of epitaxially growing a Si-containing layer (103) on a SiGe layer (102) formed on a substrate for temperature estimation (101) constituted of a Si substrate under a reaction control condition; finding a relationship between a rate of growth of the Si-containing layer and a substrate temperature of the substrate for temperature estimation; epitaxially growing a Si-containing layer on a substrate for device fabrication as a subject of substrate temperature estimation under a reaction control condition; and estimating a substrate temperature of the substrate for device fabrication based on the rate of growth of the latter Si-containing layer and the relationship between the rate of growth of the former Si-containing layer (103) and the substrate temperature of the substrate for temperature estimation.

Abstract: A method of manufacturing a transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a channel region of a transistor at a low energy level, forming an amorphous germanium implantation region in a top surface of the workpiece, and forming a crystalline germanium implantation region beneath the amorphous germanium implantation region. The workpiece is annealed using a low-temperature anneal to convert the amorphous germanium region to a crystalline state while preventing a substantial amount of diffusion of germanium further into the workpiece, also removing damage to the workpiece caused by the implantation process. The resulting structure includes a crystalline germanium implantation region at the top surface of a channel, comprising a depth below the top surface of the workpiece of about 120 ? or less. The transistor has increased mobility and a reduced effective oxide thickness (EOT).

Abstract: A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer.

Abstract: A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed by an oxidation step. The method yields excellent thickness control of high quality gate dielectrics for Ge-based field effect devices, such as MOS transistors. Structures of devices having the thin germanium oxynitride gate dielectric and processors made with such devices are disclosed, as well.

Abstract: A method of forming a finFET transistor using a sidewall epitaxial layer includes forming a silicon germanium (SiGe) layer above an oxide layer above a substrate, forming a cap layer above the SiGe layer, removing portions of the SiGe layer and the cap layer to form a feature, forming sidewalls along lateral walls of the feature, and removing the feature.

Abstract: The invention provides a method of producing a structure of a thin layer of semiconductor material on a support substrate. The thin layer is obtained from a donor substrate and includes an upper layer of semiconductor material. The method includes forming on the upper layer a bonding layer of a material that accepts diffusion from an element of the material of the upper layer, bonding the donor substrate from the side on which the bonding layer is formed on the upper layer to the support substrate, and diffusing the element from the upper layer into the bonding layer to homogenize the concentration of the element in the bonding layer and the upper layer. The result is that the thin layer of the structure is joined by the bonding layer to the upper layer.

Abstract: A strained silicon p-type MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon germanium regions are formed on the silicon germanium layer adjacent to ends of the strained silicon channel region, and shallow source and drain extensions are implanted in the silicon germanium material. The shallow source and drain extensions do not extend into the strained silicon channel region. By forming the source and drain extensions in silicon germanium material rather than in silicon, source and drain extension distortions caused by the enhanced diffusion rate of boron in silicon are avoided.

Abstract: The present invention relates to a semiconductor layer applicable to a hetero-junction bipolar transistor, a forming method thereof, and a semiconductor device and a manufacturing method thereof, for example. The semiconductor layer and the forming method thereof according to the present invention includes a first SiGe film or SiGeC film containing Ge of which the concentration become equal to a thermal expansion coefficient of silicon oxide and a second SiGe film or SiGeC film formed on the first film. In a semiconductor device according to the present invention and a manufacturing method thereof, first and second layers are laminated on an oxide film having an opening, and the first layer has the substantially same thermal expansion coefficient as that of the oxide film and has a thermal expansion coefficient different from that of the second layer.

Abstract: In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.

Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. An SiGe layer is grown in the channel of the nFET channel and a Si:C layer is grown in the pFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component in an overlying grown epitaxial layer. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel. In a further implementation, the SiGe layer is grown in both the nFET and pFET channels. In this implementation, the stress level in the pFET channel should be greater than approximately 3 GPa.

Abstract: A semiconductor device with an undercut relaxed SiGe layer having voids beneath the SiGe layer. The voids may be filled with a dielectric such as SiO2. A strained Si layer may be epitaxially grown on the relaxed SiGe layer to combine the benefits of a defect-free strained Si surface and a silicon-on-insulator substrate. The relaxed SiGe layer may be relatively thin, with a thickness below the critical thickness. Thus, the structure accommodates shallow junctions, which exhibit reduced junction capacitance.

Abstract: Ge/Si and other nonsilicon film heterostructures are formed by hydrogen-induced exfoliation of the Ge film which is wafer bonded to a cheaper substrate, such as Si. A thin, single-crystal layer of Ge is transferred to Si substrate. The bond at the interface of the Ge/Si heterostructures is covalent to ensure good thermal contact, mechanical strength, and to enable the formation of an ohmic contact between the Si substrate and Ge layers. To accomplish this type of bond, hydrophobic wafer bonding is used, because as the invention demonstrates the hydrogen-surface-terminating species that facilitate van der Waals bonding evolves at temperatures above 600° C. into covalent bonding in hydrophobically bound Ge/Si layer transferred systems.

Abstract: A process for producing a structure of a thin layer of semiconductor material obtained from a composite structure donor wafer. The donor wafer includes a lattice parameter matching layer of a matching substrate that advantageously has an upper layer of semiconductor material having a first lattice parameter. A film of semiconductor material having a second, nominal, lattice parameter that is substantially different from the first lattice parameter is strained by the matching layer. A region of weakness is created in the matching substrate to facilitate splitting. A relaxed layer has a nominal lattice parameter that is substantially identical to the first lattice parameter. The relaxed layer is transferred to a receiving substrate. A number of different wafers can be made by this process.

Abstract: A process for forming a useful layer (6) from a wafer (10), the wafer (10) comprising a supporting substrate (1) and a strained layer (2) that are chosen respectively from crystalline materials. The process includes a first step of forming a region of perturbation (3) in the supporting substrate (1) at a defined depth by creating structural perturbations that cause at least relative relaxation of the elastic strains in the strained layer (2). A second step of supplying energy causes at least relative relaxation of the elastic strains in the strained layer (2). A portion of the wafer (10) is removed from the opposite side from the relaxed strained layer (2?), the useful layer (6) being the remaining portion of the wafer (10). The present invention also relates to an application of the process and to wafers produced during the process.

Abstract: An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

Abstract: A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally include an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying a bias across the electrodes, and thus information may be stored using the structure.

Abstract: A method of forming a relaxed silicon—germanium layer for use as an underlying layer for a subsequent overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon—germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon—germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon—germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon—germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon—germanium layer progresses.

Abstract: The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.

Abstract: A semiconductor-based device includes a channel layer, which includes a distal layer and a proximal layer in contact with the distal layer. The distal layer supports at least a portion of hole conduction for at least one p-channel component, and the proximal layer supports at least a portion of electron conduction for at least one n-channel component. The proximal layer has a thickness that permits a hole wave function to effectively extend from the proximal layer into the distal layer to facilitate hole conduction by the distal layer. A method for fabricating a semiconductor-based device includes providing a distal portion of a channel layer and providing a proximal portion of the channel layer.

Abstract: One embodiment of the present invention provides a system for co-fabricating strained and relaxed crystalline, poly-crystalline, and amorphous structures in an integrated circuit device using common fabrication steps. The system operates by first receiving a substrate. The system then fabricates multiple layers on this substrate. A layer within these multiple layers includes both strained structures and relaxed structures. These strained structures and relaxed structures are fabricated simultaneously using common fabrication steps.

Abstract: A structure for use as a MOSFET employs an SOI wafer with a SiGe island resting on the SOI layer and extending between two blocks that serve as source and drain; epitaxially grown Si on the vertical surfaces of the SiGe forms the transistor channel. The lattice structure of the SiGe is arranged such that the epitaxial Si has little or no strain in the direction between the S and D and a significant strain perpendicular to that direction.

Abstract: A method of manufacturing a semiconductor device may include forming a fin on an insulator and forming a gate oxide on sides of the fin. The method may also include forming a gate structure over the fin and the gate oxide and forming a dielectric layer adjacent the gate structure. Material in the gate structure may be removed to define a gate recess. A width of a portion of the fin below the gate recess may be reduced, and a metal gate may be formed in the gate recess.

Abstract: Chemical vapor deposition processes utilize higher order silanes and germanium precursors as chemical precursors. The processes have high deposition rates yet produce more uniform films, both compositionally and in thickness, than films prepared using conventional chemical precursors. In preferred embodiments, higher order silanes are employed to deposit SiGe-containing films that are useful in the semiconductor industry in various applications such as transistor gate electrodes.

Abstract: The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves a first amount of oxygen (typically 1×1013?1×1015/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface.

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

Abstract: A photodetector device includes a plurality of Ge epilayers that are grown on a substrate and annealed in a defined temperature range. The Ge epilayers form a tensile strained Ge layer that allows the photodetector device to operate efficiently in the C-band and L-band.

Abstract: A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.

Abstract: In the process for producing low-defect semiconductor layers based on III-V nitride semiconductor material, a substrate (1) made from a material which is not based on III-V nitride semiconductors is provided, and then a mask layer (2) is applied to the substrate in order to form unmasked regions (2c) and masked regions (2a, 2b) on the substrate. Then, starting from the unmasked regions (2c) of the substrate (1), the III-V nitride semiconductor layer (3) is grown. To avoid the formation of stress-induced cracks during the cooling phase from the growth temperature to room temperature, the mask layer (2) is formed on the substrate (1) in such a manner that some of the masked regions (2b) are wide enough to prevent the III-V nitride semiconductor layer (3) from growing together over these wide masked regions (2b), whereas the III-V nitride semiconductor layer does grow together only over the other, narrow masked regions (2a).

Abstract: A strained silicon layer fabrication and a method for fabrication thereof employ a strained insulator material layer formed over a strained silicon layer in turn formed upon a strained silicon-germanium alloy material layer which is formed upon a relaxed material substrate. The strained insulator material layer provides increased fabrication options which provide for enhanced fabrication efficiency when fabricating the strained silicon layer fabrication.

Abstract: A method of manufacturing an integrated circuit having a gate structure above a substrate that includes germanium utilizes at least one layer as a seal. The layer advantageously can prevent back sputtering and outdiffusion. A transistor can be formed in the substrate by doping through the layer. Another layer can be provided below the first layer. Layers of silicon dioxide, silicon carbide, silicon nitride, titanium, titanium nitride, titanium/titanium nitride, tantalum nitride, and silicon carbide can be used.

Abstract: The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g.

Abstract: The formation of shallow trench isolations in a strained silicon MOSFET includes implantation of a dopant into overhang portions of the strained silicon layer and silicon germanium layer at the edges of trenches in which shallow trench isolations are to be formed. The conductivity type of the dopant is chosen to be opposite the conductivity type of the source and drain dopants. The implanted dopant increases the threshold voltage Vt beneath the ends of the gate in overhang portions of the strained silicon layer so that it is approximately equal to or greater than that of the remainder of the MOSFET. The resulting strained silicon MOSFET exhibits reduced leakage current beneath the ends of the gate.

Abstract: An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the gate electrode in the first conductive type semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the gate electrode.

Abstract: The present invention provides a method for manufacturing a semiconductor substrate, comprising the step of: forming a first buffer Si layer on a substrate having a silicon surface; epitaxially growing, in sequence, a first strained SiGe layer and a first Si layer above the first buffer Si layer; implanting ions into the resulting substrate followed by annealing so as to relax the lattice of the first strained SiGe layer and to thereby providing tensile strain in the first Si layer and so that tensile strain is provided in the first Si layer; and epitaxially growing, in sequence, a second buffer Si layer and a second SiGe layer above the resulting substrate; and forming a second Si layer having tensile strain on the second SiGe layer.

Abstract: A laser system includes a laser diode with a low dimensional nanostructure, such as quantum dots or quantum wires, for emitting light over a wide range of wavelengths. An external cavity is used to generate laser light at a wavelength selected by a wavelength-selective element. The system provides a compact and efficient laser tunable over a wide range of wavelengths.

Abstract: The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least partially filled with a semiconductive material that comprises at least one atomic percent of an element other than silicon. The mask is removed and a first semiconductor circuit component is formed over the first portion of the substrate. Also, a second semiconductor circuit component is formed over the semiconductive material that at least partially fills the trench. The invention also includes semiconductor constructions.

Abstract: On an Si substrate 1, a buffer layer 2, a SiGe layer 3, and an Si cap layer 4 are formed. A mask is formed on the substrate, and then the substrate is patterned. In this manner, a trench 7a is formed so as to reach the Si substrate 1 and have the side faces of the SiGe layer 3 exposed. Then, the surface of the trench 7a is subjected to heat treatment for one hour at 750° C. so that Ge contained in a surface portion of the SiGe layer 3 is evaporated. Thus, a Ge evaporated portion 8 having a lower Ge content than that of other part of the SiGe layer 3 is formed in part of the SiGe layer 3 exposed at part of the trench 7a. Thereafter, the walls of the trench 7a are oxidized.

Abstract: A method to obtain thin (less than 300 nm) strain-relaxed Si1-xGex buffer layers on Si or silicon-on-insulator (SOI) substrates. These buffer layers have a homogeneous distribution of misfit dislocations that relieve the strain, remarkably smooth surfaces, and a low threading dislocation (TD) density, i.e. less than 106 cm2. The approach begins with the growth of a pseudomorphic or nearly pseudomorphic Si1-xGex layer, i.e., a layer that is free of misfit dislocations, which is then implanted with He or other light elements and subsequently annealed to achieve the substantial strain relaxation. The very effective strain relaxation mechanism operating with this method is dislocation nucleation at He-induced platelets (not bubbles) that lie below the Si/Si1-xGex interface, parallel to the Si(001) surface.

Abstract: A method of forming a silicon-germanium layer on an insulator includes preparing a silicon substrate; depositing a layer of silicon-germanium on the silicon substrate to form a silicon/silicon-germanium portion; implanting hydrogen ions in the silicon-germanium layer; preparing an insulator substrate; bonding the silicon/silicon-germanium portion to the insulator substrate with the silicon-germanium layer in contact with the insulator substrate to form a bonded entity; curing the bonded entity; and thermally annealing the bonded entity to split the bonded entity into a silicon/silicon germanium portion and a silicon-germanium-on-insulator portion and to relax the silicon germanium layers.

Abstract: A GaInP epitaxial stacking structure and fabrication method thereof, and a FET transistor using this structure are provided wherein, stacked upon a GaAs single-crystal substrate are at least a buffer layer, a GaZIn1-ZAs (0<Z?1) channel layer, and a GaYIn1?YP (0<Y?1) electron-supply layer joined to the channel layer, wherein the GaInP epitaxial stacking structure includes a region within the electron-supply layer wherein the gallium composition ratio (Y) decreases from the side of the junction interface with the channel layer toward the opposite side.

Abstract: A method of forming a relaxed SiGe-on-insulator substrate having enhanced relaxation, significantly lower defect density and improved surface quality is provided. The method includes forming a SiGe alloy layer on a surface of a first single crystal Si layer. The first single crystal Si layer has an interface with an underlying barrier layer that is resistant to Ge diffusion. Next, ions that are capable of forming defects that allow mechanical decoupling at or near said interface are implanted into the structure and thereafter the structure including the implanted ions is subjected to a heating step which permits interdiffusion of Ge throughout the first single crystal Si layer and the SiGe layer to form a substantially relaxed, single crystal and homogeneous SiGe layer atop the barrier layer. SiGe-on-insulator substrates having the improved properties as well as heterostructures containing the same are also provided.

Abstract: A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.

Abstract: A method of bonding a germanium (Ge) wafer to a semiconductor wafer. A Ge wafer having a cleaving plane defined by ion implantation is provided. A surface activation on at least one surface of the Ge wafer is performed. A semiconductor wafer is provided. A surface activation on at least one surface of the semiconductor wafer is performed. The Ge wafer is bonded to the semiconductor wafer to form a bonded wafer pair. A first annealing is performed to the bonded wafer pair. The first annealing occurs at a temperature approximately between 50-100° C. A second annealing is performed to the bonded wafer pair. The second annealing occurs at a temperature approximately between 110-170° C. The second annealing cleaves the Ge wafer at the cleaving plane.

Abstract: A method in which a defective semiconductor crystal material is subjected to an amorphization step followed by a thermal treatment step is provided. The amorphization step amorphizes, partially or completely, a region, including the surface region, of a defective semiconductor crystal material. A thermal treatment step is next performed so as to recrystallize the amorphized region of the defective semiconductor crystal material. The recrystallization is achieved in the present invention by solid-phase crystal regrowth from the non-amorphized region of the defective semiconductor crystal material.

Abstract: In a method of manufacturing a semiconductor light-emitting device involving the steps of: forming a first semiconductor layer; forming a light-emitting layer of superlattice structure by laminating a barrier layer being made of InY1Ga1-Y1N (Y1≧0) and a quantum well layer being made of InY2Ga1-Y2N (Y2>Y1 and Y2>0) on the first semiconductor layer; and forming a second semiconductor layer on the light-emitting layer, an uppermost barrier layer, which will become an uppermost layer of the light-emitting layer, is made thicker than the other barrier layers. Further, at the time of forming the second semiconductor layer, an upper surface of such uppermost barrier layer is caused to disappear so that the thickness of the uppermost barrier layer becomes substantially equal to those of the other barrier layers.

Abstract: The filling of sub-0.25 &mgr;m trenches with dielectric material may lead to the formation of a void. Typically, the void may be closed by oxidation. When the trench includes non-oxidizable sidewall portions, insufficient closure may result. Therefore, an oxidizable spacer layer is conformally deposited prior to depositing the bulk dielectric, so that the sidewalls of the trench may be oxidized along the entire depth of the trench, thereby allowing the complete closure of the void.

Abstract: An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.

Abstract: Diffusion of As in SiGe of MOS transistors based on Si/SiGe is prevented by ion implanting boron. Embodiments include forming As source/drain extension implants in a strained Si/SiGe substrate, ion implanting boron at between the As source/drain extension implant junctions and subsequently annealing to activate the As source/drain extensions, thereby preventing distortion of the originally formed junction.