Abstract: Pinholes in a silicon oxynitride film are reduced by PECVD deposition of a plurality of silicon oxynitride sub-layers in a PECVD apparatus containing multiple chambers. Embodiments include forming a layer of amorphous carbon over a conductive layer, such as doped polycrystalline silicon, on a substrate, transferring the substrate to a multi-chamber PECVD tool and depositing 2 to 7, e.g., 5, sub-layers of dense silicon oxynitride at a total thickness of 300 to 700 ?.

Abstract: A method for preventing formation of photoresist scum. First, a substrate on which a dielectric layer is formed is provided. Next, a non-nitrogen anti-reflective layer is formed on the dielectric layer. Finally, a photoresist pattern layer is formed on the non-nitrogen anti-reflective layer. During the formation of the photoresist pattern layer, the non-nitrogen anti-reflective layer does not react with the photoresist pattern layer, thus not forming photoresist scum. This prevents undesired etching profile and critical dimension (CD) change due to presence of photoresist scum. The non-nitrogen anti-reflective layer can be silicon-rich oxide (SiOx) or hydrocarbon-containing silicon-rich oxide (SiOxCy:H).

Abstract: A flash memory cell and fabrication method thereof are disclosed. An example fabrication method deposits a pad oxide layer and a pad nitride layer on a semiconductor substrate, patterns the pad nitride layer, implants ions into the substrate to form an ion implant region, forms spacers on sidewalls of the pad nitride layer pattern, removes some part of the pad oxide layer and the top portion of the substrate through an etching process using the spacers as a mask to form a trench that divides the ion implant region into two parts. The example fabrication method also forms a gap filling insulating layer over the resulting substrate, and forms a trench isolation layer and junction regions simultaneously by removing the spacers, the pad nitride layer pattern, the pad oxide layer, and the top portion of the gap filling insulating layer.

Abstract: In order to shorten the period for the development and manufacture of a semiconductor integrated circuit device, at the time of transferring integrated circuit patterns onto a wafer by an exposure process, a photomask PM1 is used which is provided partially with light shielding patterns 3a formed of a resist film, in addition to light shielding patterns formed of a metal.

Abstract: On a multilayer film formed on a lower electrode layer, a resist layer having cutaway parts at a lower portion is formed, and on parts of the upper surface of the multilayer film which are not overlapped with the resist layer except for areas inside the cutaway parts, first gap layers are formed. Accordingly, a predetermined gap T1 can be formed between the first gap layers in the track width direction. Next, in the following step, two end surfaces of the multilayer film and the first gap layers in the track width direction are milled. Hence, according to the present invention, compared to the case in the past, the predetermined gap T1 provided between the first gap layers can be formed into a minute size with superior accuracy, the current path-squeezing structure can be easily formed, and a magnetic sensor having superior change in resistance (?R) and reproduction output can be manufactured.

Abstract: The invention relates generally to lithographic patterning of very small features. In particular, the invention relates generally to patterning of semiconductor circuit features smaller than lithographically defined using either conventional optical lithography or next generation lithography techniques. The invention relates more particularly, but not by way of limitation, to lateral trimming of photoresist images.

Abstract: A process for producing a pattern of negative electron beam resist comprises: depositing a layer of plasma polymerized fluoropolymer on a face of a substrate, the plasma polymerized fluoropolymer forming the negative electron beam resist; producing an electron beam; moving the electron beam on the layer of plasma polymerized fluoropolymer to define the pattern, the layer then having exposed fluoropolymer areas defining the pattern and unexposed fluoropolymer areas; and removing the unexposed fluoropolymer areas to leave only the pattern on the face of the substrate.

Abstract: Disclosed is a method of forming the dual damascene pattern in the semiconductor device. After forming the trench, a photoresist pattern in which a via hole region is defined is formed by exposure and development processes in a state that a photoresist is thinly coated, in a dual damascene process for first forming the trench than a via hole. Therefore, the present invention can prevent degradation of resolution due to a thickness of a photoresist pattern in a trench region and improve reliability of the entire process by simultaneously smoothly performing an etching process even with a thin photoresist pattern due to a good etching tolerance property.

Abstract: In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet etched, removing the upper or first layer of silicon dioxide. The patterned and etch upper of first layer of silicon dioxide is used as a hardmask to remove the central layer of silicon nitride applying a wet etch. A wet etch is then applied to remove the remaining lower of second layer of silicon dioxide, completing the patterning of the layer of RPO.

Abstract: The present invention provides a method of forming a TFT and a reflective electrode having recesses or projections with reduced manufacturing cost and a reduced number of manufacturing steps, and provides a liquid crystal display device to which the method is applied. A photosensitive film 8 is formed on a metal film 7. Then, remaining portions 81, 82 and 83 are formed from the photosensitive film 8. Then, the metal film 7 is etched by using the remaining portions 81, 82 and 83 as masks. And then, a photosensitive film 9 and a reflective electrode film 10 are formed without removing the remaining portions 81, 82 and 83.

Abstract: A method for forming a contact opening is provided. After forming transistors on a substrate, a stacked resist layer including a resist layer without a silicon element and a resist layer with a silicon element covers the transistors and the substrate. The stacked resist layer is defined to cover a region of a contact opening to be formed as a mask. A selective growth process, such as a liquid phase oxide deposition (LPOD), is carried out to form a selective silicon oxide layer on the silicon-containing surface and fills the space between the stacked resist layer. After the stacked resist layer is removed, a contact opening is formed in the silicon oxide layer and a step of the etching process is eliminated.

Abstract: A method to relax the alignment accuracy requirement in an integrate circuit manufacturing is described. The method comprises forming a mask layer over a substrate, and the mask layer comprises a plurality of first openings. Thereafter, a buffer layer fills the first opening, followed by forming a photoresist layer over the substrate. The photoresist layer is then patterned to form a second opening that corresponds to the first opening, and the second opening exposes a portion of the buffer layer. Isotropic etching is then performed to remove the buffer layer exposed by the second opening to expose a sidewall of the first opening that corresponds to the second opening. The photoresist layer is further removed to expose the mask layer that comprises the embedded buffer layer and the opening pattern, which is used as a hard mask layer in a subsequent process.

Abstract: A method for making a semiconductor device is described. That method includes forming a sacrificial layer on a substrate, then forming a layer of photoresist on the sacrificial layer. After the photoresist layer is patterned, to form a patterned photoresist layer that has a first opening, a first part of the sacrificial layer is removed to generate an etched sacrificial layer that has a tapered etch profile. A second part of the sacrificial layer is then removed to generate an etched sacrificial layer that has a second opening that is substantially smaller than the first opening.

Abstract: A mask and method for contact hole exposure. First, a mask including a transparent substrate, a phase shift layer installed on the transparent substrate to define a series of patterns having contact hole areas set in array, an a plurality of metal lines installed on the phase shift layer between the adjacent contact hole areas is provided. Then, an exposure is performed by transmitting a light source, such as deep ultraviolet (UV), extreme ultraviolet, or X-ray, through the mask after the metal lines absorb high degree diffraction waves.

Abstract: Successive use is made of a layer of radiation-sensitive resin at points intended to form wide semi-conductor patterns in a still intact layer, under at least one hard mask, then of a resin sensitive to particle bombardment over fine patterns to be formed in this same layer, which may be juxtaposed to those previously mentioned. The first resin patterns are exposed collectively and rapidly by insolation, while electron bombardment allows fine patterns to be formed with great precision. Another hard mask is deposited before the second resin and forms flanks around the wide patterns, which protect the wide patterns from lateral attacks during etching.

Abstract: A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxide layer is formed over the silicon nitride layer and the silicon dioxide and silicon nitride layers are patterned using a patterned mask having a width, thereby forming sidewalls in the two layers. The nitride and oxide layers are subjected to an oxygen plasma which treats the sidewalls and leaves a portion of the silicon nitride layer between the sidewalls untreated. The silicon dioxide and the untreated portion of the silicon nitride layer are removed thereby resulting in pillars of treated silicon nitride. Finally, the polycrystalline silicon is etched using the pillars as a mask. The patterned polycrystalline silicon layer thereby comprises features having widths narrower than the width of the original mask.

Abstract: A method is provided for manufacturing a magnetic head for recording information on a magnetic recording medium in the form of a direction of magnetization, which enables manufacture of a magnetic head with gaps between turns of a conductive material constituting a coil being filled with an insulating material without any void and heat generation in the coil being suppressed. A photoresist with a higher flowability than an insulating material containing a metal element is applied to the coil. A part of the photoresist applied to the coil which covers the conductive material constituting the coil is removed by exposure and development, and on the conductive material, an insulating metal compound layer made of an insulating material containing a metal element and having a higher thermal conductivity than the photoresist is formed and polished for flattening.

Abstract: A method for forming shallow trench isolation (STI) features to reduce or avoid divot formation at STI trench corners including providing a shallow trench isolation (STI) feature included in a semiconductor process surface the STI feature including an anisotropically etched trench formed into a semiconductor substrate extending through a thickness including a thermally grown silicon dioxide layer overlying the semiconductor substrate and a metal nitride hardmask layer overlying the thermally grown silicon dioxide layer said anisotropically etched trench being back filled with a silicon dioxide filling material; removing excess silicon dioxide filling material overlying the hardmask layer according to a chemical mechanical polishing (CMP) process; removing the hard mask layer according to a wet chemical etching process; and, re-growing the thermally grown silicon dioxide layer including re-oxidizing to at least an originally formed thermally grown silicon dioxide layer thickness.

Abstract: A method of micro-structuring a surface of a sample of ferroelectric material, the method comprising: (a) taking a sample of ferroelectric material having a −z face which is to be etched; (b) illuminating the −z face with ultraviolet light to define illuminated and unilluminated parts of the surface; and (c) immersing the −z face in an etchant to selectively remove the unilluminated parts of the −z face at a greater rate than the illuminated parts. The method can be carried out using pulsed ultraviolet light to etch lithium niobate crystals cut for etching on the −z face, and may further be combined with ablation to produce multi-level surface structures.

Abstract: An electrical element may be made by providing a hardmask unit that has a double gate stack with a first gate layer, a first hardmask layer formed over the first gate layer, a second gate layer formed over the first hardmask layer, and a second hardmask layer formed over the second gate layer. A first spacer for a first element is formed at a location at least partially determined by the presence of the second hardmask layer, and a second structure for a second element is formed at a location at least partially determined by the presence of the first hardmask layer.

Abstract: A method is described for decreasing the critical dimensions of integrated circuit features in which a first masking layer (101) is deposited, patterned and opened in the manner of typical feature etching, and a second masking layer (201) is deposited thereon prior to etching the underlying insulator. The second masking layer is advantageously coated in a substantially conformal manner. Opening the second masking layer while leaving material of the second layer on the sidewalls of the first masking layer as spacers leads to reduction of the feature critical dimension in the underlying insulator. Ashable masking materials, including amorphous carbon and organic materials are removable without CMP, thereby reducing costs. Favorable results are also obtained utilizing more than one masking layer (101, 301) underlying the topmost masking layer (302) from which the spacers are formed. Embodiments are also described in which slope etching replaces the addition of a separate spacer layer.

Abstract: Three-dimensional structures of arbitrary shape are fabricated on the surface of a substrate through a series of processing steps wherein a monolithic structure is fabricated in successive layers. A first layer of photoresist material is spun onto a substrate surface and is exposed in a desired pattern corresponding to the shape of a final structure, at a corresponding cross-sectional level in the structure. The layer is not developed after exposure; instead, a second layer of photoresist material is deposited and is also exposed in a desired pattern. Subsequent layers are spun onto the top surface of prior layers and exposed, and upon completion of the succession of layers each defining corresponding levels of the desired structure, the layers are all developed at the same time leaving the three-dimensional structure.

Abstract: Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a layer of highly absorbing silicon rich nitride to serve as a hardmask between a semiconductor substrate and a photoresist. The highly absorbing layer of silicon rich nitride has an extinction coefficient (k)>0.5. As reflected light passes through the layer of silicon rich nitride, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the silicon rich nitride in accordance with the pattern formed on the photoresist.

Abstract: A method of fabricating a mask forms a rectangular opening within etch resistant material that overlays a substrate. The mask preferably comprises two layers of photoresist separated by a layer of light blocking material. One of the layers of photoresist is patterned per a longitudinal exposure strip, and the other per an overlap of a lateral exposure strip with the longitudinal exposure strip, so as to provide an opening for the mask where the two overlap. With this mask over a substrate, the substrate is etched to form a container therein with a rectangular cross-section corresponding to the aperture of the mask. The container is then lined with electrically conductive material, dielectric, and electrically conductive material respectively to form a capacitor in the container—e.g., a container-cell capacitor for a DRAM device.

Abstract: To provide a method of manufacturing a semiconductor device for manufacturing a minute pattern with high accuracy using a stencil mask. An input layout data is classified into rectangles according to pattern width or the like, a boundary is created that divides a periphery or an inside of each classified graphics, an input pattern is fractionized by the boundary, and a complementary mask with fractionized patterns on both sides of the boundary distributed into different layers is used to form a pattern.

Abstract: A method of forming a conductor pattern on a base with uneven topography includes placing conductor material on the base, placing a hard mask material on the conductor material, planarizing an exposed surface of the hard mask material, and placing a layer of resist on the hard mask material. The resist is patterned and the patterned resist is used in selectively etching the hard mask material, with the hard mask material used in selectively etching the underlying conductor material. By planarizing the hard mask material prior to placing a layer of resist thereupon, uniformity of the resist coating is enhanced and depth of focus problems in exposing the resist are reduced.

Abstract: Disclosed is a method for forming contact by using the ArF lithography technology using a low-k dielectric sacrifice layer. The method comprises forming a layer to be etched on the semiconductor substrate, successively forming a low-k dielectric sacrifice layer and a hard mask on the etched layer, forming an anti-reflective layer and a photoresist pattern on the hard mask by using ArF lithography technology, selectively etching the anti-reflective layer and the hard mask and simultaneously removing the photoresist pattern when etching the hard mask, forming a contact hole exposing a surface of the semiconductor substrate by etching the low-k dielectric sacrifice layer and the layer by using the hard mask as a mask and removing the hard mask and the low-k dielectric sacrifice layer.

Abstract: A method for forming a thin film transistor (TFT) is disclosed. A gate electrode, insulating layer, semiconductor layer, doped silicon layer and metal layer are formed on a substrate. A first photoresist layer with a first absorptivity is formed on the metal layer. A second photoresist layer with a second absorptivity is formed on the first photoresist layer. The second absorptivity is higher than the first absorptivity. An exposure process and a development process are performed to form a first pattern on the first photoresist layer and a second pattern on the second photoresist layer at the same time. An etching process is then performed to transfer the first pattern into the semiconductor layer, the doped silicon layer and the metal layer and transfer the second pattern into the doped silicon layer and the metal layer. After performing the etching process, the first photoresist layer and the second photoresist layer are removed.

Abstract: A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxide layer is formed over the silicon nitride layer and the silicon dioxide and silicon nitride layers are patterned using a patterned mask having a width, thereby forming sidewalls in the two layers. The nitride and oxide layers are subjected to an oxygen plasma which treats the sidewalls and leaves a portion of the silicon nitride layer between the sidewalls untreated. The silicon dioxide and the untreated portion of the silicon nitride layer are removed thereby resulting in pillars of treated silicon nitride. Finally, the polycrystalline silicon is etched using the pillars as a mask. The patterned polycrystalline silicon layer thereby comprises features having widths narrower than the width of the original mask.

Abstract: A method of fabricating a mask forms a rectangular opening within etch resistant material that overlays a substrate. The mask preferably comprises two layers of photoresist separated by a layer of light blocking material. One of the layers of photoresist is patterned per a longitudinal exposure strip, and the other per an overlap of a lateral exposure strip with the longitudinal exposure strip, so as to provide an opening for the mask where the two overlap. With this mask over a substrate, the substrate is etched to form a container therein with a rectangular cross-section corresponding to the aperture of the mask. The container is then lined with electrically conductive material, dielectric, and electrically conductive material respectively to form a capacitor in the container—e.g., a container-cell capacitor for a DRAM device.

Abstract: Disclosed is a method for producing semiconductor elements including a metal layer (10) configured on a semiconductor substrate (5). The inventive method consists of the following steps: a silicon layer (15) is deposited on a metal layer (10); an etch mask is applied in order to structure the silicon layer (1%); the silicon layer is selectively etched (15) using the etch mask (25); and the metal layer (10) is structured in an etching process using a selectively etched silicon layer (15) as a hard mask.

Abstract: A method of fabricating a mask forms a rectangular opening within etch resistant material that overlays a substrate. The mask preferably comprises two layers of photoresist separated by a layer of light blocking material. One of the layers of photoresist is patterned per a longitudinal exposure strip, and the other per an overlap of a lateral exposure strip with the longitudinal exposure strip, so as to provide an opening for the mask where the two overlap. With this mask over a substrate, the substrate is etched to form a container therein with a rectangular cross-section corresponding to the aperture of the mask. The container is then lined with electrically conductive material, dielectric, and electrically conductive material respectively to form a capacitor in the container—e.g., a container-cell capacitor for a DRAM device.

Abstract: A resist mask pattern having a reduced thickness is formed overlying on a silicon oxynitride film during formation of a memory gate. The resist mask pattern has a resist thickness (3000 to 4000 Angstroms) sufficient to withstand removal during etching of the silicon oxynitride film. The silicon oxynitride film, having a thickness of about 800 to 1500 Angstroms, is etched based on the resist mask pattern and then used as a mask pattern to etch the polysilicon gate layer underlying the silicon oxynitride layer, to expose a portion of an isolation region aligned relative to the resist mask pattern. The portion of the resist mask remaining after etching, in combination with the etched silicon oxynitride film, have a sufficient overall thickness to serve as a channel implant mask. Use of the resist mask pattern having the reduced thickness improves yield by minimizing the occurrence of misregistration, and enables reliable formation of spaces in the mask pattern having widths of less than 0.

Abstract: A germanium and silicon alloy is employed as an antireflective coating material for use in active area lithography and gate area lithography steps in the formation of a semiconductor integrated circuit. A layer composed of an alloy of germanium-silicon is deposited over an active area nitride layer or over a gate area nitride layer, and a photoresist layer is then formed on the germanium-silicon alloy layer. The photoresist layer is than exposed and developed. During exposure, the germanium-silicon alloy layer substantially reduces reflection from the underlying nitride layer, thereby relieving the dependency of exposure energy and resulting line width on the underlying nitride layer thickness.

Abstract: An inorganic film with a double-layers structure is used as an etching mask in an EEPROM area to pattern a double-layers gate, while a thin inorganic film obtained by removing one layer of the double-layers inorganic film by etching is used as an etching mask in a CMOS logic circuit area. Therefore, the gate pattern can be formed with high precision by using a thin etching mask in the CMOS logic circuit area.

Abstract: A method of fabricating a mask forms a rectangular opening within etch resistant material that overlays a substrate. The mask preferably comprises two layers of photoresist separated by a layer of light blocking material. One of the layers of photoresist is patterned per a longitudinal exposure strip, and the other per an overlap of a lateral exposure strip with the longitudinal exposure strip, so as to provide an opening for the mask where the two overlap. With this mask over a substrate, the substrate is etched to form a container therein with a rectangular cross-section corresponding to the aperture of the mask. The container is then lined with electrically conductive material, dielectric, and electrically conductive material respectively to form a capacitor in the container—e.g., a container-cell capacitor for a DRAM device.

Abstract: A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. A cantilevered portion of a second, thicker silicon nitride layer suppresses the upward movement of the flexible foot during the later stages of the oxidation when the growth rate has slowed, thereby inhibiting the growth of the birds beak. Shear stresses responsible for dislocation generation are reduced as much as fifty fold. This stress reduction is accompanied by an improvement in surface topography as well as suppression of the narrow oxide thinning effect.

Abstract: The present invention is a method for fabricating a semiconductor device having an elevated source/drain scheme which includes the steps of: forming a first photoresist film on a top surface of a semiconductor substrate; forming a second photoresist film on the first photoresist film; forming the second photoresist film; forming a second photoresist film pattern so that a portion corresponding to a field region has a first opening and a region in which a gate electrode is to be formed has a second opening by exposing the second photoresist film to a first light, thereby developing the second photoresist film; forming a first photoresist film pattern so that a portion corresponding to the field region has a third opening by exposing the first photoresist film to a second light, thereby developing the first photoresist film; forming a first trench at the first opening position and a second trench at the second opening position on the semiconductor substrate by etching the semiconductor substrate using the first

Abstract: In one aspect, the invention provides a method of exposing a material from which photoresist cannot be substantially selectively removed utilizing photoresist. In one preferred implementation, a first material from which photoresist cannot be substantially selectively removed is formed over a substrate. At least two different material layers are formed over the first material. Photoresist is deposited over the two layers and an opening formed within the photoresist over an outermost of the two layers. First etching is conducted through the outermost of the two layers within the photoresist opening to outwardly expose an innermost of the two layers and form an exposure opening thereto. After the first etching, photoresist is stripped from the substrate. After the stripping, a second etching is conducted of the innermost of the two layers within the exposure opening.

Abstract: Disclosed is a method for producing semiconductor elements including a metal layer (10) configured on a semiconductor substrate (5). The inventive method consists of the following steps: a silicon layer (15) is deposited on a metal layer (10); an etch mask is applied in order to structure the silicon layer (1%); the silicon layer is selectively etched (15) using the etch mask (25); and the metal layer (10) is structured in an etching process using a selectively etched silicon layer (15) as a hard mask.

Abstract: In one embodiment, the present invention relates to a method of forming a shallow trench, involving the steps of providing a semiconductor substrate comprising a barrier oxide layer over at the semiconductor substrate and a nitride layer over the barrier oxide layer; depositing an ultra-thin photoresist over the nitride layer, the ultra-thin photoresist having a thickness of about 2,000 Å or less; patterning the ultra-thin photoresist to expose a portion of the nitride layer and to define a pattern for the shallow trench; etching the exposed portion of the nitride layer with an etchant having a nitride:photoresist selectivity of at least about 10:1 to expose a portion of the barrier oxide layer; etching the exposed portion of the barrier oxide layer to expose a portion of the semiconductor substrate; and etching the exposed portion of the semiconductor substrate to provide the shallow trench.

Abstract: Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a layer of highly absorbing silicon rich nitride to serve as a hardmask between a semiconductor substrate and a photoresist. The highly absorbing layer of silicon rich nitride has an extinction coefficient (k)>0.5. As reflected light passes through the layer of silicon rich nitride, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photolithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the silicon rich nitride in accordance with the pattern formed on the photoresist.

Abstract: A method for fabricating a crown capacitor is able to form a deep UV photoresist layer having a cylindrical structure by using only one mask. A conductive layer, the main structure of a bottom electrode, is formed on the sidewall of the deep UV photoresist layer by performing a silylation process. A fairly small and high cylindrical structure is formed by the invention, so that the crown capacitor can be used in DRAM having a storage capacity higher than 64 MB. Also, there is no problem of registration because only one mask is used.

Abstract: A structure is provided comprising a semiconductor substrate, a gate oxide layer on the substrate, and a polysilicon layer on the gate oxide layer. A masking layer is formed on the polysilicon layer. The masking layer is then patterned into a mask utilizing conventional photolithographic techniques, but without patterning the polysilicon layer. The photoresist layer is then removed, whereafter the mask, which is patterned out of the masking layer, is utilized for patterning the polysilicon layer. The use of a carbon free mask for patterning the polysilicon layer, instead of a conventional photoresist layer containing carbon, results in less breakthrough through the gate oxide layer when the polysilicon layer is patterned. Less breakthrough through the gate oxide layer allows for the use of thinner gate oxide layers, and finally fabricated transistors having lower threshold voltages.

Abstract: A germanium and silicon alloy is employed as an antireflective coating material for use in active area lithography and gate area lithography steps in the formation of a semiconductor integrated circuit. A layer composed of an alloy of germanium-silicon is deposited over an active area nitride layer or over a gate area nitride layer, and a photoresist layer is then formed on the germanium-silicon alloy layer. The photoresist layer is than exposed and developed. During exposure, the germanium-silicon alloy layer substantially reduces reflection from the underlying nitride layer, thereby relieving the dependency of exposure energy and resulting line width on the underlying nitride layer thickness.

Abstract: A method for controlling the mask bias of a photoresist mask is described whereby a polymer coating is formed over the patterned photoresist mask immediately prior to etching the mask's pattern into a subjacent layer. The polymer coating is formed by treatment of the photoresist mask with a plasma, struck in within a reactive ion etching tool, in a gas mixture containing chlorine and helium. The etch durability and the thickness of the polymer coating determines the dimensional bias of the mask with respect to the pattern formed in the subjacent layer. By varying the polymer formation parameters a controllable etch bias between -0.01 and +0.03 microns can be achieved. This capability is particularly useful for patterning in integrated circuits where critical dimensions approach the resolution limits of the photolithography. The method is applied to the patterning of a silicon nitride hardmask employed in the formation of field oxide isolation (LOCOS) where a zero bias condition is achieved.

Abstract: A process for reducing dimensions of circuit elements in a semiconductor device. The process reduces feature sizes by using an intermediate etchable mask layer between a photo-resistive mask and a layer to be etched. The etchable mask layer below the photo-resistive mask is etched and portions remain which undercut the pattern on the photo-resistive mask. After removing the photo-resistive mask, the remaining mask portions are then used to mask the layer to be etched. By undercutting the photo-resistive mask, the mask portions form a pattern having features with widths that are less than widths of features in the photo-resistive mask. The layer to be etched can then be etched to provide circuit elements with reduced dimensions.

Abstract: The invention includes methods of patterning substrates. In one implementation, an electrically conductive etch mask layer is formed over a substrate. A resist layer, for example photoresist, is formed over the etch mask layer. The etch mask layer is etched into through an opening formed in the patterned resist. The etching preferably comprises dry etching within a dual source, high density plasma etcher using an oxygen containing gas. Substrate layers beneath the electrically conductive base layer are preferably etched through one or more openings formed in the conductive layer at least in part by the preferred dry etching. The etch mask layer and resist are ultimately removed from the substrate.

Abstract: A lower resist film, which is made of PMMA for EB exposure and has a thickness of about 200 nm, is applied onto a substrate, and then an upper resist film to be exposed to i-rays is applied on the lower resist film. Thereafter, a mixed layer, in which the upper and lower resist films are mixed, is formed in the interface between the upper and lower resist films. Next, the upper resist film, except for the head-forming region thereof, is exposed to i-rays and developed, thereby forming an upper-layer opening. And then the mixed layer and a leg-forming region of the lower resist film are exposed to EB and developed, thereby forming a lower-layer opening having an upper part like a taper progressively expanding upward.

Abstract: A formation method of a contact/through hole is provided, which is able to form a contact or through hole without raising such problems related to a resist mask. After forming a dielectric layer on a semiconductor substructure having a lower electrical conductor, a metal layer is formed on the dielectric layer. A patterned resist film is formed on the metal layer. Then, the metal layer is selectively etched using a patterned resist film as a mask to transfer the pattern of the resist film to the metal layer, forming a hole pattern to penetrate the metal layer. The patterned resist film is removed from the etched metal layer. The dielectric layer is selectively etched using the etched metal layer as a mask to thereby transfer the hole pattern of the metal layer to the dielectric layer. Thus, a contact/through hole is formed to penetrate the dielectric layer and to extend to the lower electrical conductor.