Abstract: Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a microelectronic device. There is then formed over the microelectronic device a passivating dielectric layer formed from a passivating dielectric material selected from the group consisting of fluorosilicate glass (FSG) passivating dielectric materials, atmospheric pressure chemical vapor deposited (APCVD) passivating dielectric materials, subatmospheric pressure chemical vapor deposited (SACVD) passivating dielectric materials and spin-on-glass (SOG) passivating dielectric materials to form from the microelectronic device a passivated microelectronic device. Finally, there is then annealed thermally, while employing a thermal annealing method employing an atmosphere comprising hydrogen, the passivated microelectronic device to form a stabilized passivated microelectronic device.

Abstract: A new method is provided for the creation of interfacing and adjacent surfaces when creating damascene interconnects. Under the first embodiment of the invention, the surface area of the Intra Metal Dielectric (IMD) in which the copper metal pattern has been created is partially removed thereby reducing and sub-dividing the surface area of the interfacing surface. Under the second embodiment of the invention, the surface area of the IMD is sub-divided into a multiplicity of squares that now form the interfacing surface area. Under the third embodiment of the invention, the surface area of the Intra Metal Dielectric (IMD) in which the copper metal pattern has been created is essentially removed leaving sidewalls of the IMD material on the formed pattern of copper interconnects.

Abstract: A new method of forming a non-shrinkable metal passivation layer that will eliminate metal voiding and improve electromigration lifetime of the integrated circuit device is described. Semiconductor device structures are provided in and on a semiconductor substrate and covered by an insulating layer. A metal layer is deposited overlying the insulating layer and patterned to form metal lines wherein there is a gap between two of the metal lines. A non-shrinkable passivation layer is formed according to the following steps: 1) a HDP-CVD oxide layer is deposited overlying the metal lines wherein the gap is filled by the HDP-CVD oxide layer. 2) A silicon nitride layer is deposited by plasma-enhanced chemical vapor deposition overlying the HDP-CVD oxide layer. Or, 1) a PECVD oxide layer is deposited over the metal lines. 2) A silicon nitride layer is deposited by PECVD over the oxide layer to fill the gap and complete the passivation. Then, the fabrication of the integrated circuit device is completed.

Abstract: A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material. The electronic circuit is of the type that calls for formation above the major surface of at least one dielectric multilayer. The dielectric multilayer includes a layer of amorphous planarizing material having a continuous portion extending between two contiguous areas with a more internal first area and a more external second area in the morphological structure. The device edge morphological structure includes in the substrate an excavation on the side of the major surface at the more internal first area of the morphological structure in a zone in which is present the continuous portion of the dielectric multilayer.

Abstract: A method for in-situ removing photoresist material. An etching process for patterning a passivation layer of a CMOS photosensor is performed on an etching machine. Oxygen is in-situ used to remove the parched photoresist material. The etching process and the in-situ O2 process are performed, for example, on a Tegal-903 etching machine. The Tegal-903 has better stability than an Asher etching machine for removing the parched photoresist material using oxygen plasma. A stable etching rate is thus obtained to prevent the acrylic material layer from being damaged by over-etching and to prevent the photoresist material from remaining.

Abstract: Various methods of fabricating a circuit structure utilizing silicon nitride are provided. In one aspect, a method of fabricating a circuit structure is provided that includes forming a silicon nitride film on a silicon surface, annealing the silicon nitride film in an ammonia ambient and annealing the silicon nitride film in a nitrous oxide ambient to form a thin oxide layer at an interface between the silicon nitride film and the silicon surface. The process of the present invention enables the manufacture of thin silicon nitride films with highly uniform morphology for use as gate dielectrics or other purposes. The thin oxide film is self-limiting in thickness and improves differential mechanical stresses.

Abstract: A method of exposing a bond pad includes: providing an integrated circuit having a bond pad, a first passivation layer overlying an area portion of the bond pad, and a second passivation layer overlying the first passivation layer; removing a portion of the second passivation layer above the area portion of the bond pad exposing an area of the first passivation layer; curing the second passivation; and etching a portion of the exposed area of the first passivation layer to expose the top surface of the bond pad. A method of coupling an integrated circuit chip to a chip package is also disclosed as is a method of probing the bond pads of an integrated circuit. A probe card is further disclosed, including a probe assembly coupled to a printed circuit board, the probe assembly having a sloped sidewall portion with a plurality of probing beams extending from the sidewall portion.

Abstract: A method and apparatus for forming thin copolymer layers having low dielectric constants on semiconductor substrates includes in situ formation of p-xylylenes, or derivatives thereof, from solid or liquid precursors such as cyclic p-xylylene dimer, p-xylene, 1,4-bis(formatomethyl)benzene, or 1,4-bis(N-methyl-aminomethyl)benzene. P-xylylene is copolymerized with a comonomer having labile groups that are converted to dispersed gas bubbles after the copolymer layer is deposited on the substrate. Preferred comonomers comprise diazocyclopentadienyl, diazoquinoyl, formyloxy, or glyoxyloyloxy groups.

Abstract: The present invention comprises means for sublimating and handling ammonium chloride (NH.sub.4 Cl) vapor, a bi-product of a silicon nitride growth process, thereby preventing backstreaming into the reactor and ingestion of vapor and particulates by the vacuum pump. The exhaust circuit comprises a novel combination of valves, sublimation and cold traps, cooling and heating elements to facilitate reduction of condensed NH.sub.4 Cl volume from a first path trap thus reducing maintenance, increasing production up-time and enhancing product yield.

Abstract: Borderless vias are formed in electrical connection with a lower metal feature of a metal pattern gap filled with HSQ. Heat treatment in an inert atmosphere is conducted before filling the through-hole to outgas water absorbed during solvent cleaning of the through-hole, thereby reducing via void formation and improving via integrity.

Abstract: An integrated circuit passivation layer including a first passivation layer portion of silicon nitride treated with nitrous oxide and a second passivation layer portion of polyimide. Also, a method of passivating an integrated circuit wafer including depositing a first passivation layer over the top surface of an integrated circuit wafer having a scribe street area between adjacent integrated circuit device portions, depositing a second passivation layer over the first passivation layer, and patterning the first passivation layer and the second passivation layer to expose the scribe street area.

Abstract: A method, suitable for forming metal contacts on a semiconductor substrate at positions for defining radiation detector cells, includes the steps of forming one or more layers of material on a surface of the substrate with openings to the substrate surface at the contact positions; forming a layer of metal over the layer(s) of material and the openings; and removing metal overlying the layer(s) of material to separate individual contacts. Optionally, a passivation layer to be left between individual contacts on the substrate surface may be applied. Etchants used for removing unwanted gold (or other contact matter) are preferably prevented from coming into contact with the surface of the substrate, thereby avoiding degradation of the resistive properties of the substrate.

Abstract: The method for forming an insulating film having a low dielectric constant, which is suitable for intermetal insulating film applications, by plasma enhanced chemical vapor deposition (PECVD) includes the step of supplying a first source gas containing fluorine and carbon to a dual-frequency, high density plasma reactor. The method also includes the step of supplying a second source gas containing silicon dioxide to the reactor. In this manner a fluorocarbon/silicon dioxide film is formed on a substrate in the reactor.

Abstract: Borderless vias are formed in electrical connection with a lower metal feature of a metal patterned later gap filled with HSQ. Vacuum baking is conducted before filling the through-hole to outgas water absorbed during solvent cleaning, thereby reducing void formation and improving via integrity. Embodiments include vacuum baking at a temperature of about 300.degree. C. to about 400.degree. C., for about 45 seconds to about 2 minutes, at a pressure of no greater than about 10.sup.-6 Torr, preferably in the same tool employed for depositing the barrier layer in filling the through-hole.

Abstract: A method of passivating an outer portion of a semiconductor wafer comprises: a) applying and patterning a metal layer to define conductive metal runners projecting atop the wafer, the conductive metal runners projecting outwardly from the wafer at given distances; b) applying an insulating dielectric layer atop the wafer to a thickness which is greater than the given distance of a furthest projecting metal runner; c) global planarizing the insulating dielectric layer to some point on the wafer which is elevationally above the underlying conductive metal runners; the preferred method is by chemical mechanical polishing; and d) applying a planar layer of an effective mechanical protection, chemical diffusion barrier and moisture barrier material atop the globally planarized layer of insulating dielectric.

Abstract: A underlayer process for high O.sub.3 /TEOS interlayer dielectric deposition is disclosed. First, a layer of metal pattern is defined on a semiconductor substrate, then a layer of dielectric underlayer is deposited, next, a high O.sub.3 /TEOS interlayer dielectric is formed to achieve planarization. The key point of this process is to apply materials with higher refraction index than conventional PE-TEOS for forming interlayer dielectric underlayer. The mentioned material can be PE-SiH.sub.4 with a constant or decreasing refraction index with the distance from the semiconductor substrate. The underlayer can also be bi-layer structure consisting of high refraction index bottom layer and low refraction index surface layer. This invention can effectively suppress the problem caused from high surface sensitivity of O.sub.3 /TEOS, and improve the quality of interlayer dielectric planarization process dramatically.

Abstract: The uniformity of the thickness of a deposition layer, generated by a chemical vapor deposition (CVD) process, on a semiconductor wafer is enhanced by providing an undercoating on the deposition chamber. The undercoating is formed at a deposition rate significantly faster than the deposition rate of the material on the wafer. A thin precoat is typically formed over the undercoating. Another method of providing uniformity of thickness includes altering the temperature of the wafer or a series of wafers to alter the deposition rate. The alteration of the temperature of the wafer may include the use of a temperature ramp which increases or decreases the deposition temperature between two or more wafers in a series of wafers.

Abstract: A method of manufacturing a semiconductor device by forming first and second resistor layers of polycrystalline silicon including impurities on a first insulation film with a predetermined distance therebetween. The resistor layer have a resistance ratio set to a predetermined value. A second insulation film is formed on the first and second resistor layers and has an opening in a predetermined region. A metal layer electrically connected to the first and second resistor layers is formed in the opening and extends onto the second insulation film. The metal layer is patterned to form a first metal interconnection layer electrically connected to the first resistor layer and a second metal interconnection layer electrically connected to the second resistor layer. The first metal interconnection layer partially covers the first resistor layer. The second metal interconnection layer partially covers the second resistor layer.

Abstract: A metal layer (24) is formed on an isolation layer (22) to act as interconnections. Subsequently, a thin liner layer (26) is optionally formed along the surface of the metal layer (24) to serve as a buffer layer. An undoped silicate glass (USG) layer (28) is deposited on the liner layer (26). The USG layer (28) is formed using ozone and tetraethylorthosilicate (TEOS) as a source at a temperature of approximately 380 to 420.degree. C. Oxygen gas is used as a carrier for the ozone. The flow rate of the oxygen gas is approximately 4000 to 6000 sccm. Helium gas is used as a carrier for the TEOS. The flow rate of the helium is approximately 3000 to 5000 sccm. A silicon nitride layer (30) is deposited on the USG layer (28) using plasma enhanced chemical vapor deposition (PECVD). The silicon nitride layer (30) serves as a main passivation layer. The thickness of the silicon nitride layer (30) is approximately 3000 to 7000 angstroms.

Abstract: The invention relates to a method of manufacturing a semiconductor device whereby an upper side of a wafer of semiconductor material (12) is provided with semiconductor elements in passivated mesa structures (2), which semiconductor elements are provided each with a connection electrode (7') in that according to the invention conductive contact bodies (3') are provided on upper sides (7) of the mesa structures (2), and an insulating material (18) is provided in spaces (17) between the contact bodies, whereupon the wafer (1) is split up into individual semiconductor bodies (10) which comprise passivated mesa structures (2) and contact bodies (3') surrounded by insulation. The contact bodies (3') have dimensions such that the semiconductor bodies (10) are suitable for surface mounting. The semiconductor devices made by the method according to the invention are resistant to comparatively high voltages between the connection electrodes (7', 4).

Abstract: A substrate for forming a compound semiconductor device is placed in a reaction chamber. An MOCVD method or a GS-MBE method is used to grow compound semiconductor layers on the substrate. The grown layers include, for example, a GaN buffer layer, an n-GaN layer, an InGaN active layer, a p-AlGaN layer, and a p.sup.+ -GaN contact layer. After the growth of the layers, the substrate is kept in the reaction chamber, and a passivation film of, for example, SiNx, SiO2, or SiON is formed on top of the grown layers according to a CVD or GS-MBE method. Since the top of the grown layers is not exposed to air outside the reaction chamber, no oxidization or contamination occurs on the top of the grown layers. The compound semiconductor device is manufactured through simpler processes compared with a prior art that needs separate apparatuses for growing and forming the layers and passivation film.

Abstract: A planarized passivation layer is described. A planarized passivation layer of the present invention preferably includes a fluorosilicate glass (FSG) layer and a silicon nitride layer. The FSG layer is preferably deposited using triethoxyfluorosilane (TEFS) and tetraethoxyorthosilicate (TEOS). The inclusion of fluorine in the process chemistry provides good gap-fill characteristics in the film thus formed. The TEFS-based process employed by the present invention employs a low deposition rate, on the order of less than about 4500 .ANG./min, and preferably above 3000 .ANG./min, when depositing the FSG layer. The use of low deposition rate results in a positively sloped profile, preventing the formation of voids during the deposition of the FSG layer and the silicon nitride layer.

Abstract: A method for forming a UV transmission passivation coating on an integrated circuit, such as EPROM, after completion of the active device and metal routing circuitry comprises depositing a first barrier dielectric layer over the integrated circuit; smoothing out underlying features by applying a layer of flowable dielectric over the first dielectric layer; and depositing a second dielectric layer over the flowable dielectric. Next a photoresist pattern is made over the second dielectric coating, having an opening layer over the at least one conductive pad. A wet etch process is used to remove portions of the second dielectric layer exposed by the opening. A dry etch process is used to remove portions of the remaining layers exposed through the opening, including the remaining portions of the second dielectric layer, the flowable dielectric layer and the first dielectric layer, down to the conductive pad. Finally, the photoresist is removed.

Abstract: An inorganic seal for encapsulation of an organic layer during passivation of an integrated circuit device and method for making the same is disclosed. The seal creates a structure which forms an inorganic to inorganic passivation seal over Reactive Ion Etched (RIE) edges in an all organic planar back end of the line (BEOL) insulator. The edge seal prevents the delamination of the passivation layer from the integrated circuit device or a metallization ring which may lead to subsequent formation of moisture-filled channels and corrosion of the metal lines of the device and the failure of the integrated circuit.

Abstract: A method of passivating an outer portion of a semiconductor wafer comprises: a) applying and patterning a metal layer to define conductive metal runners projecting atop the wafer, the conductive metal runners projecting outwardly from the wafer at given distances; b) applying an insulating dielectric layer atop the wafer to a thickness which is greater than the given distance of a furthest projecting metal runner; c) global planarizing the insulating dielectric layer to some point on the wafer which is elevationally above the underlying conductive metal runners; the preferred method is by chemical mechanical polishing; and d) applying a planar layer of an effective mechanical protection, chemical diffusion barrier and moisture barrier material atop the globally planarized layer of insulating dielectric.

Abstract: A passivation layer of semiconductor device, which comprises a chrome oxide on a silicon nitride or both on and beneath a silicon nitride. The chrome oxide is deposited in a physical vapor deposition technique, relieving the compressive stress of the silicon nitride so as to prevent cracks from occurring therein.

Abstract: A method for improved adhesion between dielectric material layers at their interface during the manufacture of a semiconductor device, comprising operations for forming a first layer (1) of a dielectric material, specifically silicon oxynitride or silicon nitride, on a circuit structure (7) defined on a substrate of a semiconductor material (6) and subsequently forming a second layer (3) of dielectric material (silicon oxynitride or silicon nitride particularly) overlying the first layer (1). Between the first dielectric material layer and the second, a thin oxide layer (2), silicon dioxide in the preferred embodiment, is formed in contact therewith. This interposed oxide (2) serves an adhesion layer function between two superimposed layers (1,3).

Abstract: A method of manufacturing a semiconductor device which starts with a semiconductor wafer which is provided with a layer of semiconductor material lying on an insulating layer at a first side. Semiconductor elements and conductor tracks are formed on this first side of the semiconductor wafer. Then the semiconductor wafer is fastened with this first side to a support wafer, and material is removed from the semiconductor wafer from its other, second side until the insulating layer has been exposed. The method starts with a semiconductor wafer whose insulating layer is an insulating as well as a passivating layer. The semiconductor device must be provided with a usual passivating layer after its manufacture in order to protect it against moisture and other influences. In the method described here, such a passivating layer is present already before the manufacture of the semiconductor device starts.

Abstract: A majority carrier device includes a bulk active region and a thin-film passivating layer on the bulk active region. The thin-film passivating layer includes a Group 13 element and a chalcogenide component. In one embodiment, the majority carrier device is a metal, passivating layer, semiconductor, field-effect transistor. The transistor includes an active layer and thin-film passivating layer on the active layer. The thin-film passivating layer includes a Group 13 element and a chalcogenide component. Source and drain contacts are disposed on the active layer or the passivating layer. A gate contact is disposed on the passivating layer between the source contact and the drain contact.

Abstract: A method for making a device and the device itself which utilizes a passivation layer displaying improved crack resistance is disclosed. This is accomplished through the incorporation of boron into a PSG passivation layer. The temperature of the passivation deposition may need to be kept to a temperature low enough so that the boron compound used for the boron source does not decompose prior to reacting with other reactants.

Abstract: A conductive layer in a semiconductor device is protected against chemical attack by a photoresist developer by forming a protective film overlying the conductive layer. The protective film is formed using a chemical reaction that occurs through defects in a passivation layer that was previously formed overlying the conductive layer. The chemical reaction substantially occurs at the surface of the conductive layer and chemically converts portions thereof in forming the protective film. Preferably, the conductive layer is aluminum or an alloy thereof containing copper and/or silicon, and the protective film is aluminum oxide formed on the aluminum layer to protect it from corrosion by tetramethyl ammonium hydroxide (TMAH). The passivation layer is TiN, and the chemical reaction used is oxidation of the aluminum layer through defects in the overlying TiN layer by placing in an ozone asher.

Abstract: A process for forming a thin film by chemical vapor deposition which comprises repeating a substrate processing step on one or more substrates placed inside a reaction chamber by introducing a reaction gas inside the reaction chamber. The process includes a step of introducing a passivation gas or the like for passivating the surface of a thin film deposited on the fixing jig or other peripheral members between substrate processing steps. The passivation gas is, for example, an adsorbent gas or an oxidizing gas. More specifically, an example of an adsorbent gas is a mixture of an inert gas and from 0.1 to 10% of NH.sub.3 gas or SiH.sub.2 Cl.sub.2 gas, and an example of an oxidizing gas is a mixture of an inert gas and at least one selected from the group of oxygen, nitrogen, monoxide, and nitrogen dioxide. The inert gas may also be replaced with N.sub.2 gas.

Abstract: A new method of forming controlled voids within the intermetal dielectric and within the passivation layer of an integrated circuit is achieved. A first layer of patterned metallization is provided over semiconductor device structures in and on a semiconductor substrate. An intermetal dielectric layer is deposited overlying the first patterned metal layer wherein the thickness of the intermetal dielectric layer is large enough so as to cause the formation of voids within the intermetal dielectric and wherein said voids are completely covered by said intermetal dielectric. A second layer of metallization is deposited over the intermetal dielectric and patterned. A passivation layer is deposited overlying the second patterned metal layer. The thickness of the passivation layer is large enough so as to cause the formation of voids within the passivation layer wherein said voids are completely covered by said passivation layer.

Abstract: The invention relates to a method for contacting SIPOS-passivated semiconductor zones on a semiconductor body, where the removal of the oxide layer from the wafer surface takes place at the same time as the oxide etching before SIPOS passivation. The double-layered SIPOS passivation consists here of a N-SIPOS layer and a O-SIPOS layer. For contact opening, only the N-SIPOS layer is removed by wet chemical etching. By annealing the previously vaporized and structured metallization, a good contact results which can also carry a high current. The process according to the invention involves a simple sequence of operations and an underetching of the passivation layers and the disadvantages resulting from this are reliably avoided.

Abstract: Bond pads (394, 106) and bond pad openings (62, 108) are formed such that the bond pad openings (62, 108) are asymmetric to the conductive sections (398, 106) of the bond pads (394, 106). If the bond pads are more likely to lift from the scribe line side of the bond pad (394, 106), the bond pad openings (62, 108) are formed such that the passivation layer (52) overlies more of the conductive section (398, 106) near the scribe line (40). If the bond pads (394, 106) are more likely to lift from the other side, the passivation layer (52) overlies more of the other side of the conductive section (398, 106). In addition to reducing the risk of lifting, contamination problems should also be reduced.

Abstract: In a method of producing a solar cell, a photovoltaic thin semiconductor crystalline film is formed on an underlying substrate and hydrogen passivated throughout the film thickness direction of the photovoltaic film whereby a high efficiency solar cell is obtained. In addition, since the passivation process is performed before forming a rear surface electrode on the thin semiconductor crystalline film, the passivation process is not limited by the rear surface electrode. Thereby, a solar cell having a higher energy conversion efficiency is obtained. The passivation process is performed by exposing the thin semiconductor crystalline film to a hydrogen ion ambient having a low acceleration energy, below 2 KeV, or to a plasma ambient. Therefore, the uniformity of the passivation process at a wafer surface is improved and a large area wafer can be efficient processed.

Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

Abstract: A method for passivating diamond films to substantially prevent them from oxidizing at temperatures up to 800.degree. C. in an oxygen atmosphere. The method involves depositing one or more passivating layers over the diamond film wherein one of the layers is nitride and the other layer is quartz. The passivation technique is directly applicable to diamond sensor pressure transducers and enable them to operate at temperatures above 800.degree. C. in oxygen environments. The passivation technique also provides an economical and simple method for patterning diamond films.

Abstract: A thin conformal passivating dielectric film is deposited by ECR-CVD on an IC chip comprising semiconductor devices each of which includes a sub-micron-width irregularly shaped gate electrode. A protective layer of patterned resist is formed overlying each passivated device. Additional dielectric material is then deposited by ECP-CVD, at a temperature below the glass transition temperature of the resist, on the surface of the chip. Subsequently, in a lift-off step, the patterned resist together with the additional dielectric material overlying the resist is removed from the chip.