Chalcogen (i.e., Oxygen (o), Sulfur (s), Selenium (se), Tellurium (te)) Containing Patents (Class 438/95)
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Publication number: 20140332080Abstract: A main object of the present invention is to provide a CZTS-based compound semiconductor whose band gap is different from that of a conventional CZTS-based compound semiconductor and a photoelectric conversion device prepared with the CZTS-based compound semiconductor. The present invention is a CZTS-based compound semiconductor in which a ratio of the number of moles of Cu to the total number of moles of Cu, Zn and Sn is larger than a ratio of the number of moles of Cu to the total number of moles of Cu, Zn and Sn configuring Cu2ZnSnS4, and a photoelectric conversion device prepared with the CZTS-based compound semiconductor.Type: ApplicationFiled: November 30, 2012Publication date: November 13, 2014Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, JAPAN FINE CERAMICS CENTERInventors: Takenobu Sakai, Hiroki Awano, Ryosuke Maekawa, Taro Ueda, Seiji Takahashi
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Publication number: 20140332070Abstract: A method for manufacturing a thin-film solar cell module includes a rear surface electrode layer deposition step for depositing a rear surface electrode layer on a substrate, an alkali metal adding step for adding an alkali metal to the rear surface electrode layer, a light absorbing layer deposition step for depositing a light absorbing layer on the rear surface electrode layer, a division groove forming step for forming a division groove that divides the light absorbing layer and exposing a front surface of the rear surface electrode layer in the division groove, an alloying step for alloying the rear surface electrode layer and the alkali metal on the front surface of the rear surface electrode layer exposed in the division groove, and a transparent conductive film deposition step for depositing a transparent conductive film on the light absorbing layer and in the division groove.Type: ApplicationFiled: November 22, 2012Publication date: November 13, 2014Inventors: Hiroki Sugimoto, Keisuke Ishikawa, Masashi Kondou
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Publication number: 20140335649Abstract: A compound semiconductor precursor ink composition includes an ink composition for forming a chalcogenide semiconductor film and a peroxide compound mixed with the ink composition. A method for forming a chalcogenide semiconductor film and a method for forming a photovoltaic device each include using the compound semiconductor precursor ink composition containing peroxide compound to form a chalcogenide semiconductor film.Type: ApplicationFiled: May 9, 2013Publication date: November 13, 2014Inventors: Feng-Yu Yang, Ching Ting, Yueh-Chun Liao
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Patent number: 8883549Abstract: Exemplary embodiments of the present disclosure are directed to improve p-type doping (p-doping) of cadmium telluride (CdTe) for CdTe-based solar cells, such as cadmium Sulfide (Cds)/CdTe solar cells. Embodiments can achieve improved p-doping of CdTe by creating a high density of cadmium (Cd) vacancies (VCd) and subsequently substituting a high density of substitutional defects and/or defect complexes for the Cd vacancies that were created. Formation of a high density of substitutional defects and defect complexes as a p-dopant can improve light-to-electricity conversion efficiency, doping levels or hole concentrations, junction band bending, and/or ohmic contact associated with p-type CdTe (p-CdTe) based solar cells.Type: GrantFiled: June 21, 2011Date of Patent: November 11, 2014Assignee: New Jersey Institute of TechnologyInventor: Ken K. Chin
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Patent number: 8883602Abstract: Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.Type: GrantFiled: December 3, 2010Date of Patent: November 11, 2014Assignee: Micron Technology, Inc.Inventors: Jun Liu, Michael P. Violette
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Patent number: 8883550Abstract: Processes for making a solar cell by depositing various layers of components on a substrate and converting the components into a thin film photovoltaic absorber material. Processes of this disclosure can be used to control the stoichiometry of metal atoms in making a solar cell for targeting a particular concentration and providing a gradient of metal atom concentration. A selenium layer can be used in annealing a thin film photovoltaic absorber material.Type: GrantFiled: September 15, 2011Date of Patent: November 11, 2014Assignee: Precursor Energetics, Inc.Inventors: Kyle L. Fujdala, Zhongliang Zhu, David Padowitz, Paul R. Markoff Johnson, Wayne A. Chomitz, Matthew C. Kuchta
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Publication number: 20140326319Abstract: The present disclosure relates to a Se or S based thin film solar cell and a method for fabricating the same, which may improve the structural and electrical characteristics of an upper transparent electrode layer by controlling a structure of a lower transparent electrode layer in a thin film solar cell having a Se or S based light absorption layer. In the Se or S based thin film solar cell having a light absorption layer and a front transparent electrode layer, the front transparent electrode layer comprises a lower transparent electrode layer and an upper transparent electrode layer, and the lower transparent electrode layer comprises an oxide-based thin film obtained by blending an impurity element into a mixed oxide in which Zn oxide and Mg oxide are mixed (also, referred to as an ‘impurity-doped Zn—Mg-based oxide thin film’).Type: ApplicationFiled: July 16, 2013Publication date: November 6, 2014Inventors: Won Mok KIM, Jin-soo KIM, Jeung-hyun JEONG, Jong-Keuk PARK, Young Joon BAIK
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Publication number: 20140326299Abstract: An intermediate band solar cell is provided. The intermediate band material of the intermediate band solar cell consists of a collection of quantum dots of a semiconductor material that are immersed in a volume of a second semiconductor material. The first semiconductor material has a rock salt-type crystalline structure, and the second semiconductor material has a zinc blende structure. The quantum dots are produced by the immiscibility of the first semiconductor material in the second semiconductor material. A combination of the first and second semiconductor materials with a very similar lattice constant can therefore be selected such that the layer of intermediate band material does not have mechanical stress accumulation.Type: ApplicationFiled: May 10, 2012Publication date: November 6, 2014Inventors: Elisa Antolín Fernández, Antonio Martí Vega, Antonio Luque López, Íñigo Ramiro González, Pablo García-Linares Fontes
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Publication number: 20140326317Abstract: A method of fabricating a CIGS thin film for solar cells using a simplified co-vacuum evaporation process and a CIGS thin film fabricated by the method are disclosed. The method includes: (a) depositing Cu, Ga and Se on a substrate having a substrate temperature ranging from 500° C. to 600° C. through co-vacuum evaporation, (b) depositing Cu, Ga, Se and In through co-vacuum evaporation while maintaining the same substrate temperature as in step (a), and (c) depositing Ga and Se through co-vacuum evaporation, followed by depositing Se alone through vacuum evaporation while lowering the temperature of the substrate. The method can realize crystal growth and band-gap grading by Ga composition distribution while simplifying process steps and significantly reducing a film-deposition time, as compared with a conventional co-vacuum evaporation process, thereby providing improvement in process efficiency.Type: ApplicationFiled: February 5, 2013Publication date: November 6, 2014Inventors: Jihye Gwak, Jae-Ho Yun, SeJin Ahn, Kyung Hoon Yoon, Kee Shik Shin, Guk-Yeong Jeong, SeoungKyu Ahn, Ara Cho, Hisun Park, Sung Woo Choi
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Patent number: 8878155Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle.Type: GrantFiled: December 9, 2011Date of Patent: November 4, 2014Assignee: Micron Technology, Inc.Inventors: Jun Liu, Kristy A. Campbell
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Publication number: 20140322859Abstract: A semiconductor thin-film and method for producing a semiconductor thin-films comprising a metallic salt, an ionic compound in a non-aqueous solution mixed with a solvent and processing the stacked layer in chalcogen that results in a CZTS/CZTSS thin films that may be deposited on a substrate is disclosed.Type: ApplicationFiled: July 3, 2014Publication date: October 30, 2014Inventor: Raghu Nath Bhattacharya
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Patent number: 8871561Abstract: Provided is a method for manufacturing a variable resistance nonvolatile storage device, which prevents electrical conduction between lower electrodes and upper electrodes of variable resistance elements in the memory cell holes. The method includes: forming lower copper lines; forming a third interlayer insulating layer; forming memory cell holes in the third interlayer insulating layer, an opening diameter of upper portions of the memory cell holes being smaller than bottom portions; forming a metal electrode layer on the bottom of each memory cell holes by sputtering; embedding and forming a variable resistance layer in each memory cell hole; and forming upper copper lines connected to the variable resistance layer embedded and formed in each memory cell hole.Type: GrantFiled: January 30, 2012Date of Patent: October 28, 2014Assignee: Panasonic CorporationInventors: Ichirou Takahashi, Takumi Mikawa
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Patent number: 8872147Abstract: A method for manufacturing a nonvolatile semiconductor storage device according to an embodiment includes laminating a first wire extending in a first direction, and a film made into a variable resistance element made of a metallic material, which are laminated in order on a semiconductor substrate, dividing, into a plurality of pieces, the film made into the variable resistance element, in the first direction and a second direction, forming an interlayer insulating film between the plurality of pieces formed by dividing the film made into the variable resistance element in the second direction, and oxidizing the metallic material of the film made into the variable resistance element, and laminating an upper electrode and a second wire extending in the second direction, which are laminated in order on the film made into the variable resistance element and the interlayer insulating film.Type: GrantFiled: August 13, 2012Date of Patent: October 28, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Toshiharu Tanaka
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Patent number: 8871559Abstract: Provided is a method for fabricating a phase change memory device. The method includes forming a plurality of bottom electrodes on a substrate, forming a first mold layer on the substrate to extend in a first direction where the bottom electrodes are exposed, forming a second mold layer on the substrate, the second mold layer extending in a second direction orthogonal to the first direction to expose parts of the bottom electrodes, forming a phase change material layer on the first and second mold layers to be connected to parts of the bottom electrodes dividing the phase change material layer as a plurality of phase change layers respectively connected to the parts of the bottom electrodes and forming a plurality of top electrodes on the phase change layers.Type: GrantFiled: June 7, 2011Date of Patent: October 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hideki Horii, Hyun-Suk Kwon, Hyeyoung Park
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Patent number: 8871574Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.Type: GrantFiled: August 5, 2013Date of Patent: October 28, 2014Assignee: Micron Technology, Inc.Inventor: Chandra Mouli
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Patent number: 8872149Abstract: A memory cell and method includes a first electrode formed in an opening in a first dielectric layer, the first dielectric layer being formed on a substrate including a metal layer, the opening being configured to allow physical contact between the first electrode and the metal layer, the first electrode having a first width W1 and extending a distance beyond a region defined by the opening, a resistive layer formed on the first electrode and having substantially the first width W1, a capping layer, having a second width W2 less than the first width W1, formed on the resistive layer, a second electrode formed on the capping layer and having substantially the second width W2, a first composite spacer region having at least two different dielectric layers formed on the resistive layer between the first width W1 and the second width W2, and a via coupled to the second electrode.Type: GrantFiled: July 30, 2013Date of Patent: October 28, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Pei Hsieh, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 8871560Abstract: Embodiments relate to a method for annealing a solar cell structure including forming an absorber layer on a molybdenum (Mo) layer of a solar cell base structure. The solar cell base structure includes a substrate and the Mo layer is located on the substrate. The absorber layer includes a semiconductor chalcogenide material. Annealing the solar cell base structure is performed by exposing an outer layer of the solar cell base structure to a plasma.Type: GrantFiled: August 9, 2012Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Shafaat Ahmed, Sukjay Chey, Hariklia Deligianni, Lubomyr T. Romankiw
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Patent number: 8866122Abstract: In one embodiment, a resistive switching device includes a bottom electrode, a switching layer, a buffer layer, and a top electrode. The switching layer is disposed over the bottom electrode. The buffer layer is disposed over the switching layer and provides a buffer of ions of a memory metal. The buffer layer includes an alloy of the memory metal with an alloying element, which includes antimony, tin, bismuth, aluminum, germanium, silicon, or arsenic. The top electrode is disposed over the buffer layer and provides a source of the memory metal.Type: GrantFiled: June 14, 2012Date of Patent: October 21, 2014Assignee: Adesto Technologies CorporationInventors: Wei Ti Lee, Chakravarthy Gopalan, Yi Ma, Kuei-Chang Tsai, Jeffrey Shields, Janet Wang
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Patent number: 8866120Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.Type: GrantFiled: December 7, 2011Date of Patent: October 21, 2014Assignee: Renesas Electronics CorporationInventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
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Patent number: 8865506Abstract: A method for fabricating a solar cell commences by bonding a first metal-coated substrate to a second metal-coated substrate to provide a bonded substrate. The bonded substrate is then coated with a first precursor solution to provide a coated bonded substrate. Finally, the procedure de-bonds the coated bonded substrate to provide a first solar cell device and a second solar cell device. A system for fabricating the solar cell comprises a first precursor solution deposition system containing a first precursor solution for deposition on a substrate, a first heating element for heating the substrate after deposition of the first precursor solution, a second precursor solution deposition system containing a second precursor solution for deposition on the substrate, and a second heating element for heating the substrate after deposition of the second precursor solution.Type: GrantFiled: January 24, 2012Date of Patent: October 21, 2014Assignee: Magnolia Solar, Inc.Inventors: Gopal G. Pethuraja, Roger E. Welser, Ashok K. Sood
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Patent number: 8865514Abstract: The concentration of a constituent within a chalcogenide film used to form a chalcogenide containing semiconductor may be adjusted post deposition by reacting the chalcogenide film with a material in contact with the chalcogenide film. For example, a chalcogenide film containing tellurium may be coated with a titanium layer. Upon the application of heat, the titanium may react with the tellurium to a controlled extent to reduce the concentration of tellurium in the chalcogenide film.Type: GrantFiled: November 9, 2010Date of Patent: October 21, 2014Assignee: Micron Technology, Inc.Inventors: Davide Erbetta, Camillo Bresolin, Silvia Rossini
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Publication number: 20140306306Abstract: A method for forming a photovoltaic device includes forming an absorber layer with a granular structure on a conductive layer; conformally depositing an insulating protection layer over the absorber layer to fill in between grains of the absorber layer; and planarizing the protection layer and the absorber layer. A buffer layer is formed on the absorber layer, and a top transparent conductor layer is deposited over the buffer layer.Type: ApplicationFiled: April 12, 2013Publication date: October 16, 2014Applicant: International Business Machines CorporationInventors: Talia S. Gershon, Supratik Guha, Jeehwan Kim, Mahadevaiyer Krishnan, Byungha Shin
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Publication number: 20140308774Abstract: A method for fabricating a thin film photovoltaic device is provided. The method includes providing a substrate comprising a surface region made of a thin-film photovoltaic absorber including copper, indium, gallium, selenium, and sulfur species. Additionally, the method includes applying a dip-in chemical bath deposition process for forming a buffer layer containing at least zinc-oxygen-sulfide material but substantially free of cadmium species. Furthermore, the method includes producing a chemical bath including steps of heating a bath of water to about 75° C., adding aqueous ammonia to mix with the bath of water, adding a solution of sodium hydroxide, adding zinc salt solution, and adding a solution of thiourea. The dip-in chemical bath deposition process includes immersing a plurality of substrates formed with the thin-film photovoltaic absorber substantially vertically in the chemical bath for 30 minutes to form the zinc-oxygen-sulfide buffer layer followed by a cleaning and drying process.Type: ApplicationFiled: January 14, 2014Publication date: October 16, 2014Applicant: Stion CorporationInventors: Robert D. Wieting, Jason Todd Jackson
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Patent number: 8859344Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.Type: GrantFiled: December 7, 2011Date of Patent: October 14, 2014Assignee: Renesas Electronics CorporationInventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
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Patent number: 8860111Abstract: An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings.Type: GrantFiled: April 12, 2012Date of Patent: October 14, 2014Assignees: Macronix International Co., Ltd., International Business Machines CorporationInventors: Hsiang-Lan Lung, Chung Hon Lam, Matthew J. Breitwisch
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Patent number: 8859323Abstract: A method for high temperature selenization of Cu—In—Ga metal precursor films comprises ramping the precursor film to a temperature between about 300 C and about 400 C in a Se containing atmosphere and at a pressure between about 600 torr and 800 torr. A partial selenization is performed at a temperature between about 300 C and about 400 C in a Se-containing atmosphere. The film is then ramped to a temperature between about 400 C and about 550 C in a Se containing atmosphere and at a pressure between about 600 torr and 800 torr. The film is then annealed at a temperature between about 550 C and about 650 C in an inert gas.Type: GrantFiled: July 31, 2012Date of Patent: October 14, 2014Assignee: Intermolecular, Inc.Inventor: Haifan Liang
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Publication number: 20140302633Abstract: The present invention relates to a process for selective wet chemical etching of a thin-film substrate comprising a CIGS surface layer. The present invention also relates to a process for producing cells in series for thin-film photovoltaic modules, which process implements the selective wet chemical etching process according to the invention. The present invention furthermore relates to a process for creating small patterns, such as for example monolithic interconnects, in thin-film photovoltaic devices, which process implements the selective wet chemical etching process according to the invention.Type: ApplicationFiled: March 1, 2012Publication date: October 9, 2014Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUET ET AUX ENERGIES ALTERNATIVESInventors: Dario Rapisarda, Joël Dufourcq, Simon Perraud, Olivier Poncelet
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Publication number: 20140302634Abstract: A method and apparatus for forming a solar cell. The apparatus includes a housing defining a vacuum chamber and a rotatable substrate apparatus configured to hold a plurality of substrates on a plurality of surfaces. A first sputtering source is configured to deposit a plurality of absorber layer atoms of a first type over at least a portion of a surface of each one of the plurality of substrates. An evaporation source is configured to deposit a plurality of absorber layer atoms of a second type over at least a portion of the surface of each one of the plurality of substrates.Type: ApplicationFiled: June 23, 2014Publication date: October 9, 2014Inventors: Edward TENG, Ying-Chen CHAO, Chih-Jen YANG, Kuo-Jui HSIAO
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Patent number: 8852992Abstract: A method of manufacturing a solar cell having increased light efficiency due to increased gallium distribution on a surface of a light absorption layer, the method including forming a first electrode on a substrate, forming a precursor that includes at least one of copper, gallium, and indium on the first electrode, forming a preliminary light absorption layer by providing selenium to the precursor, forming the preliminary light absorption layer further including performing a heat treatment, and forming a liquid state CuSe compound, forming a light absorption layer by providing a compound including at least one of gallium and indium to the preliminary light absorption layer, and forming a second electrode on the light absorption layer.Type: GrantFiled: May 11, 2011Date of Patent: October 7, 2014Assignees: Samsung SDI Co., Ltd., Samsung Display Co., Ltd.Inventors: Woo-Su Lee, Sang-Cheol Park, Byoung-Dong Kim, Jung-Gyu Nam, Gug-Il Jun, Dong-Gi Ahn, In-Ki Kim
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Patent number: 8852991Abstract: Provided is a method of manufacturing a solar cell. The method includes: preparing a substrate with a rear electrode; and forming a copper indium gallium selenide (CIGS) based light absorbing layer on the rear electrode at a substrate temperature of room temperature to about 350° C., wherein the forming of the CIGS based light absorbing layer includes projecting an electron beam on the CIGS based light absorbing layer.Type: GrantFiled: December 30, 2011Date of Patent: October 7, 2014Assignee: Electronics and Telecommunications Research InstituteInventor: Yong-Duck Chung
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Publication number: 20140283913Abstract: Photovoltaic (PV) devices and solution-based methods of making the same are described. The PV devices include a CIGS-type absorber layer formed on a molybdenum substrate. The molybdenum substrate includes a layer of low-density molybdenum proximate to the absorber layer. The presence of low-density molybdenum proximate to the absorber layer has been found to promote the growth of large grains of CIGS-type semiconductor material in the absorber layer.Type: ApplicationFiled: November 8, 2013Publication date: September 25, 2014Applicant: Nanoco Technologies Ltd.Inventors: Stephen Whitelegg, Takashi Iwahashi, Paul Kirkham, Cary Allen, Zugang Liu, Stuart Stubbs, Jun Lin
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Publication number: 20140284750Abstract: A photovoltaic device includes a substrate, a transparent conductive oxide, an n-type window layer, a p-type absorber layer and an electron reflector layer. The electron reflector layer may include zinc telluride doped with copper telluride, zinc telluride alloyed with copper telluride, or a bilayer of multiple layers containing zinc, copper, cadmium and tellurium in various compositions. A process for manufacturing a photovoltaic device includes forming a layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process includes forming an electron reflector layer over a p-type absorber layer.Type: ApplicationFiled: March 20, 2014Publication date: September 25, 2014Applicant: FIRST SOLAR, INC.Inventors: San Yu, Veluchamy Palaniappagounder, Pratima Addepalli, Imran Khan
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Publication number: 20140287550Abstract: The present invention generally provides a method for forming a photovoltaic device including evaporating a source material to form a large molecule processing gas and flowing the large molecule processing gas through a gas distribution showerhead and into a processing area of a processing chamber having a substrate therein. The method includes generating a small molecule processing gas, and reacting the small molecule processing gas with a film already deposited on a substrate surface to form a semiconductor film. Additionally, apparatuses that may use the methods are also provided to enable continuous inline CIGS type solar cell formation.Type: ApplicationFiled: June 3, 2014Publication date: September 25, 2014Inventors: Byung-sung KWAK, Kaushal K. SINGH, Stefan BANGERT, Nety M. KRISHNA
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Publication number: 20140283907Abstract: The invention is a method of forming a cadmium sulfide based buffer on a copper chalcogenide based absorber in making a photovoltaic cell. The buffer is sputtered in two steps the first being at low rates or relatively high pressures and the second at high rates or relatively low pressures. The resulting cell has good efficiency and according to one embodiment is characterized by a narrow interface between the absorber and buffer layers. The buffer is further characterized according to a second embodiment by a relatively high oxygen content.Type: ApplicationFiled: October 22, 2012Publication date: September 25, 2014Applicant: Dow Global Technologies LLCInventors: Melissa A. Mushrush, Todd R. Bryden, Kevin P. Capaldo, Scott A. Sprague
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Patent number: 8841160Abstract: Disclosed are methods for producing chalcopyrite compound (e.g., copper indium selenide (CIS), copper indium gallium selenide (CIGS), copper indium sulfide (CIS) or copper indium gallium sulfide (CIGS)) thin films. The methods are based on solution processes, such as printing, particularly, multi-stage coating of pastes or inks of precursors having different physical properties. Chalcopyrite compound thin films produced by the methods can be used as light-absorbing layers for thin-film solar cells. The use of the chalcopyrite compound thin films enables the fabrication of thin-film solar cells with improved efficiency at low costs.Type: GrantFiled: November 28, 2012Date of Patent: September 23, 2014Assignee: Korea Institute of Science and TechnologyInventors: Byoung Koun Min, Hee Sang An, Yun Jeong Hwang
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Publication number: 20140261651Abstract: Disclosed herein are CIGS-based photon-absorbing layers disposed on a substrate. The photon-absorbing layers are useful in photovoltaic devices. The photon absorbing-layer is made of a semiconductor material having empirical formula AB1-xB?xC2-yC?y, where A is Cu, Zn, Ag or Cd; B and B? are independently Al, In or Ga; C and C? are independently S, or Se, and wherein 0?x?1; and 0?y?2. The grain size of the semiconductor material and the composition of the semiconductor material both vary as a function of depth across the layer. The layers described herein exhibit improved photovoltaic properties, including increased shunt resistance and decreased backside charge carrier recombination.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: Nanoco Technologies, Ltd.Inventor: Stephen Whitelegg
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Publication number: 20140261667Abstract: A back electrode for a PV device and method of formation are disclosed. A ZnTe material is provided over an absorber material and a MoNx material is provided over the ZnTe material. A Mo material may also be included in the back electrode above or below the MoNx layer and a metal layer may be also provided over the MoNx layer.Type: ApplicationFiled: March 13, 2014Publication date: September 18, 2014Applicant: FIRST SOLAR, INC.Inventors: Benyamin Buller, Igor Sankin, Long Cheng, Jigish Trivedi, Jianjun Wang, Kieran Tracy, Scott Christensen, Gang Xiong, Markus Gloeckler, San Yu
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Publication number: 20140261669Abstract: An article made by: depositing a bottom contact onto a flexible glass substrate, and depositing a photovoltaic material on the bottom contact.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Jason D. Myers, Jesse A. Frantz, Robel Y. Bekele, Jasbinder S. Sanghera
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Publication number: 20140261668Abstract: An article made by: sputtering molybdenum onto a flexible glass substrate, and depositing a photovoltaic material on the molybdenum by sputtering, thermal evaporation, multi-target ternary or binary sputtering, or nanoparticle techniques.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Jason D. Myers, Jesse A. Frantz, Robel Y. Bekele, Jasbinder S. Sanghera
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Publication number: 20140273337Abstract: Materials and methods for preparing Cu2ZnSnS4 (CZTS) layers for use in thin film photovoltaic (PV) cells are disclosed herein. The CZTS materials are nanoparticles prepared by a colloidal synthesis in the presence of a labile organothiol. The organothiol serves as both a sulphur source and as a capping ligand for the nanoparticles.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: Nanoco Technologies, Ltd.Inventors: Nathalie Gresty, Ombretta Masala, James Harris, Nigel Pickett
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Publication number: 20140273336Abstract: A method for synthesizing Cu(InxGa1-x)S2 and Cu(InxGa1-x)Se2 nanopowders using flame spray pyrolysis to form solar cell absorber materials. The flame spray product is the oxide nanoparticles of the absorber materials (copper indium gallium oxide). The oxide nanoparticles may be deposited directly onto glass substrates. The oxide nanoparticles are then sulfurdized or selenized with a post deposition anneal directly on the substrate to form the absorber layer for a solar cell device.Type: ApplicationFiled: February 27, 2014Publication date: September 18, 2014Inventors: Colin C. Baker, Woohong Kim, Shyam S. Bayya, Jasbinder S. Sanghera, Ishwar D. Aggarwal
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Publication number: 20140273335Abstract: An apparatus for deposition of a plurality of elements onto a solar cell substrate comprising: a housing; a transporting apparatus to transport said substrate in and out of said housing; a first tubing apparatus to deliver powders of a first elements to said housing wherein said first tubing apparatus is comprised of a first feeder tube located outside of said housing and joined to said housing; a first source material tube located outside of said housing and joined to said feeder tube; a valves located inside of said first source material tube sufficient to block access between said first source material tube and said first feeder tube; a first heating tube located inside of said housing and connected to said first feeder tube; a second tubing apparatus to deliver powders of a second elements to said housing wherein said second tubing apparatus is comprised of a second feeder tube located outside of said housing and joined to said housing; a second source material tube located outside of said housing and joiType: ApplicationFiled: February 18, 2014Publication date: September 18, 2014Inventor: Jehad A. Abushama
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Publication number: 20140261688Abstract: A photovoltaic device is disclosed including at least one Cadmium Sulfide Telluride (CdSxTe1-x) layer as are methods of forming such a photovoltaic device.Type: ApplicationFiled: March 13, 2014Publication date: September 18, 2014Applicant: FIRST SOLAR, INCInventors: Arnold Allenic, Zhigang Ban, Benyamin Buller, Markus Gloeckler, Benjamin Milliron, Xilin Peng, Rick C. Powell, Jigish Trivedi, Oomman K. Varghese, Jianjun Wang, Zhibo Zhao
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Publication number: 20140261665Abstract: Methods and semiconductor materials produced by such methods that are suitable for use in photovoltaic cells, solar cells fabricated with such methods, and solar panels composed thereof. Such methods include a wet-chemical synthesis method capable of producing a Group I-III-VI2 semiconductor material by forming a solution containing an organic solvent, at least one Group I precursor of at least one Group I element, and at least one Group III precursor of at least one Group III element. The Group I precursor is present in the solution in an amount of less than 120% of a stoichiometric ratio of the Group I element in the Group I-III-VI2 semiconductor material, and the Group III precursor is present in the solution in an amount of greater than 55% of a stoichiometric ratio of the Group III element in the Group I-III-VI2 semiconductor material.Type: ApplicationFiled: March 12, 2014Publication date: September 18, 2014Inventor: Suneel Girish Joglekar
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Publication number: 20140261676Abstract: A method of making a back contact to a Group IIB-VIA compound layer employed in a device such as a solar cell and in particular a CdTe solar cell. The method involves deposition of a contact buffer layer comprising an ionic conductor over a surface of a CdTe film, which is the absorber of the solar cell. A highly conductive contact layer is deposited over the contact buffer layer. In some examples, the compound device is a device such as a solar cell and in particular a CdTe solar cell in a sub-strate configuration or structure. The method involves deposition of a contact buffer layer comprising an ionic conductor on a surface of a highly conductive contact layer. A CdTe film, which is the absorber layer of the solar cell is then deposited over the contact buffer layer.Type: ApplicationFiled: March 17, 2014Publication date: September 18, 2014Applicant: ENCORESOLAR, INC.Inventor: Bulent M. BASOL
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Patent number: 8835852Abstract: A manufacture having an electrical response to incident photons includes a semiconductor substrate; a chalcogen-doped semiconductor active layer on a first side of the substrate; a first contact in electrical contact with the active layer; and a second contact in electrical contact with the substrate; wherein, photons incident upon the active layer cause a variation in current between the first and second contacts.Type: GrantFiled: January 7, 2011Date of Patent: September 16, 2014Assignees: President and Fellows of Harvard College, U.S. Army RDECOM-ARDECInventors: Aurore J. Said, Daniel L. Recht, Jeffrey M. Warrender, Michael J. Aziz
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Patent number: 8835212Abstract: Methods for developing and investigating materials and processes for various layers used in manufacturing CdTe, CIGS, and CZTS TFPV superstrate devices using high productivity combinatorial techniques is described. Typical layers subjected to the HPC techniques include the buffer layers, absorber layers, and the contact interface layers.Type: GrantFiled: September 19, 2011Date of Patent: September 16, 2014Assignee: Intermolecular, Inc.Inventor: Upendra Avachat
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Publication number: 20140256082Abstract: A method of depositing CIGS thin films for solar panel construction comprising: providing a chamber; providing a substrate and placing said substrate inside said chamber; providing a material source; placing said material source inside said chamber; reducing pressure within said chamber; heating said substrate and said material source using electromagnetic heating (RF and Microwaves) source; perform deposition of said material source oto said substrate.Type: ApplicationFiled: February 11, 2014Publication date: September 11, 2014Inventor: Jehad A. Abushama
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Publication number: 20140252529Abstract: The disclosure describes methods for preparing lead salt materials which are sensitive to the mid-infrared spectrum which can be used to manufacture high-uniformity, high-detectivity, polycrystalline lead salt photoconductive and photovoltaic photodetectors.Type: ApplicationFiled: February 28, 2014Publication date: September 11, 2014Inventors: Zhisheng Shi, Jijun Qiu, Binbin Weng, Zijian Yuan
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Patent number: 8828774Abstract: Herein disclosed is a method of forming a thermoelectric material having an optimized stoichiometry, the method comprising: reacting a precursor material including a population of nanocrystals with a first ionic solution and a second ionic solution to form a reacted mixture.Type: GrantFiled: April 19, 2013Date of Patent: September 9, 2014Assignee: Evident Technologies Inc.Inventors: Susanthri Perera, Dave Socha, Adam Z. Peng, Clinton T. Ballinger