Abstract: A method of fabricating integrated circuit wafers, in accordance with this invention comprises the following steps. Provide an integrated circuit wafer having devices formed therein covered with a metal layer and a photoresist layer over the metal layer which is selectively exposed and developed forming a photoresist mask. Introduce the wafer into a multi-chamber system, patterning the metal layer by etching and then exposing the mask to light in a cooled chamber wherein the light is derived from a source selected from a mercury lamp and a laser filtered to remove red and infrared light therefrom before exposure of the wafer thereto. The chamber is cooled by a refrigerant selected from water and liquefied gas. Then remove the wafer, and load it into a photoresist stripping tank to remove the photoresist mask with a wet photoresist stripper. Place the wafer in a batch type plasma chamber after removing the photoresist mask.

Abstract: The reverse of a wafer is processed after adhering a protecting sheet and a reinforcing plate to the obverse of a wafer. The wafer is mounted on a frame for dicing via a dicing sheet and diced. Then, the protecting sheet is separated from the wafer after irradiating the wafer with ultraviolet light.

Abstract: A new cleaning chemistry based on a choline compound, such as choline hydroxide, is provided in order to address the problem of dual damascene fabrication. An etch stop inorganic layer at the bottom of a dual damascene structure protects the underlying interconnect of copper and allows a better cleaning. A two step etch process utilizing the etch stop layer is used to achieve the requirements of UISI manufacturing in a dual damascene structure.

Abstract: In a process for treating a workpiece such as a semiconductor wafer, a processing fluid is selectively applied or excluded from an outer peripheral margin of at least one of the front or back sides of the workpiece. Exclusion and/or application of the processing fluid occurs by applying one or more processing fluids to the workpiece while the workpiece and a reactor holding the workpiece are spinning. The flow rate of the processing fluids, fluid pressure, and/or spin rate are used to control the extent to which the processing fluid is selectively applied or excluded from the outer peripheral margin.

Abstract: In a method of manufacturing a contact element, provision is made of a laminated body which has an insulating film, an electrically conductive layer stacked on the insulating film, and bump holes opened. A treatment is carried out so as to removen organic materials and the like from an interior of the bump holes and/or a surface of the insulating film before bumps are formed on the bump holes. The treatment may be a plasma treatment or an X-ray irradiation.

Abstract: A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact region beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. There is then etched the silicon oxide layer while employing a reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) an etched silicon oxide layer which exposes the contact region without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the etched silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer while employing a downstream plasma etch method employing a second etchant gas composition comprising a fluorocarbon etchant gas and oxygen.

Abstract: A method for cleaning bonding pads on a semiconductor device, as disclosed herein, includes treating the bonding pads with a CF4 and water vapor combination. In the process, the water vapor breaks up and the hydrogen from the water vapor couples to fluorine residue on the bonding pad surface creating a volatile HF vapor. In addition, fluorine from the CF4 exchanges with the titanium in the metallic polymer residue making the polymer more soluble for the organic strip operation which follows. Next, the resist is ashed and then an organic resist stripper is applied to the bonding pad area, thereby creating a clean bonding pad surface. Thereafter, a reliable bond wire connection can be made to the bonding pad.

Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

Abstract: The present invention relates to a method of etching a layer on a fabricated thin film transistor in liquid crystal display, which prevents failure of patterns by removing the residues generated from organic material in the air or the remainders of photoresist before patterning a layer. The present invention includes the steps of defining a photoresist pattern on a predetermined region of a layer on substrate, leaving an etch-resistant residue on at least a portion of the layer outside the predetermined region, removing residue by ashing with plasma, patterning the layer with an etchant, where the the photoresist pattern acts as an etch mask.

Abstract: A method for stripping photoresist and/or removing post etch residues from an exposed low k dielectric layer of a semiconductor wafer in the presence or absence of copper. The method comprises creating an oxygen free plasma by subjecting an oxygen free gas to an energy source to generate the plasma having electrically neutral and charged particles, The charged particles are then selectively removed from the plasma. The electrically neutral particles react with the photoresist and/or post etch residues to form volatile gases which are then removed from the wafer by a gas stream. The oxygen free, plasma gas composition for stripping photoresist and/or post etch residues comprises a hydrogen bearing gas and a fluorine bearing wherein the fluorine bearing gas is less than about 10 percent by volume of the total gas composition.

Abstract: A method for removal of post reactive ion etch sidewall polymer rails on a Al/Cu metal line of a semiconductor or microelectronic composite structure comprising:

Abstract: A method of improving an etch back process. A substrate having a metal layer formed thereon is provided. A main etching is performed over the metal layer to form an interconnect. A first over etching is performed over a metal residue left after the main etching. A gas flush and second over etch are performed.

Abstract: A method for removing impurities and deposits formed in a contact hole of a semiconductor device. The method comprises the step of bathing the semiconductor device in a solution having concentrations of between about 25 to 35 weight percent of Isopropyl Alcohol (IPA), 2 to 4 weight percent of H2O2, 0.05 to 0.25 weight percent of HF, and the remaining percent of deionized water. Such bathing is preferably carried out with the solution maintained at a constant temperature of between about 20 to 25° C. for about 1 to 5 minutes.

Abstract: A method for forming an opening in a semiconductor device is provided. A silicon-oxy-nitride layer is formed on a dielectric layer and then a photoresist layer with a first opening is formed on the silicon-oxy-nitride layer. A polymer film is formed on sidewalls of the first opening. A second opening narrower than the first opening is formed in the dielectric layer with the photoresist layer and the polymer film.

Abstract: A method and an apparatus for manufacturing a semiconductor integrated circuit in which semiconductor elements (2) and a wiring structure connecting the semiconductor elements (2) one another are located on a semiconductor substrate (1). In the method or apparatus, a series of wiring elements (4,6,7,9,10), each of which constructs the wiring structure is formed sequentially, then the semiconductor integrated circuit under manufacturing process is washed by neutral solution containing oxidant during the process of forming of the wiring elements (4,6,7,9,10).

Abstract: The present invention is to provide a method for fabricating a semiconductor device, including the steps of: (a) forming an insulating layer on a semiconductor substrate; (b) selectively removing the insulating layer and then forming an opening and the residual insulating layer on a bottom of the opening; (c) removing the residual insulating layer by wet etching in order to expose the semiconductor substrate; and (d) burying a conductive layer in the opening and then forming a conductive layer pattern connected to the semiconductor substrate.

Abstract: The formation and/or growth of dendrites emanating from Cu or Cu alloy lines into a bordering open dielectric field are prevented or substantially reduced by chemically removing a portion of the surface from the dielectric field and from between the lines after CMP with a solution comprising acetic acid and ammonium fluoride. Embodiments include removing up to 60 .ANG., e.g. about 10 .ANG. to about 30 .ANG., of silicon oxide by immersing the wafer in a solution containing at least about 90 wt. % acetic acid and up to about 10 wt. % ammonium fluoride.

Abstract: In a method of manufacturing a semiconductor device including a semiconductor element formed on a semiconductor substrate, an SiOF film is formed at least on the top surfaces of metal wirings under condition that an in-chamber pressure is 5 mTorr or lower. The SiOF film can thus be buried into a space between the metal wirings without causing any void and the capacitance between the wirings can be prevented from increasing, while preventing the metal wirings from being damaged and preventing the aspect ratio from increasing.

Abstract: A method for stripping positive photoresist from a keyhole 17 in a passivation layer 18 before a heating process using NMP solvent strips after a photoresist strip. The process is summarized by the 5 steps as follows: (1) Photoresist strip 1 (e.g., EKC 830), (2) Photoresist strip 2 (e.g., EKC 830 photoresist stripper), (3) N-methly-2-pyrolidone (NMP) solvent strip-agitated (solvent is preferably the same solvent in the photoresist stripper (1 &2) (4) NMP solvent strip-agitated and (5) H.sub.2 O rinse. The NMP solvent strip steps (3) and (4) remove photoresist residue (16, FIG. 1) in the key hole 17. This prevents the formation of photoresist extrusions 24 while annealing the metal lines 14.

Abstract: The present invention comprises means for sublimating and handling ammonium chloride (NH.sub.4 Cl) vapor, a bi-product of a silicon nitride growth process, thereby preventing backstreaming into the reactor and ingestion of vapor and particulates by the vacuum pump. The exhaust circuit comprises a novel combination of valves, sublimation and cold traps, cooling and heating elements to facilitate reduction of condensed NH.sub.4 Cl volume from a first path trap thus reducing maintenance, increasing production up-time and enhancing product yield.

Abstract: Methods of forming electrically interconnected lines using organic compound cleaning agents include the steps of forming a first electrically conductive line on a substrate and then forming a first electrically insulating layer on the first electrically conductive line to electrically isolate the first conductive line from adjacent regions and lines. An organic spin-on-glass (SOG) passivation layer is then formed as a planarization layer on the first electrically insulating layer. The organic SOG layer is then etched-back to define a first etched surface thereon, using a carbon-fluoride gas which also preferably contains argon. The organic SOG layer may even be sufficiently etched back to expose an upper surface of the first electrically insulating layer. The first etched surface is then exposed to an organic compound cleaning agent so that organic residues can be removed from the etched surface so that layers subsequently formed on the etched surface are less susceptible to lift-off and flaking.

Abstract: Etching residue, etching mask and silicon nitride and/or silicon dioxide are etched or removed employing a composition containing a fluoride containing compound, water and certain organic solvents.

Abstract: A method for cleaning polymer film residues from in-process integrated circuit devices is disclosed. Specifically, a method for forming a contact via in an integrated circuit is disclosed in which the formation of a metallization conductive element is exposed through a dry anisotropic etch. During the etch, a polymer film residue forms from masking materials, and coats the newly-formed via. The polymer film may have metals incorporated metals therein from the metallization conductive element. A fluorine based etchant is used to remove the polymer film. Protection of the metallization conductive element during the cleaning process is accomplished with passivation additives comprising straight, branched, cyclic, and aromatic hydrocarbons. Attached to the hydrocarbons are functional groups comprising at least 3 hydroxyls.

Abstract: A method (200) of making a flash memory device without poly stringers includes forming a stacked gate region (202) on a substrate (102) and forming one or more word lines (122a, 122b, 204) in the stacked gate region. The method further includes performing a self-aligned etch (206) in regions adjacent to the one or more word lines (122a, 122b) and subsequently performing an isotropic etch (208) to remove any poly stringers (128) in the regions adjacent the one or more word lines (122a, 122b).

Abstract: A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a low dielectric constant dielectric layer, where the low dielectric constant dielectric layer is formed from a silsesquioxane spin-on-glass (SOG) dielectric material. There is then formed over the low dielectric constant dielectric layer a patterned photoresist layer. There is then etched through use of a fluorine containing plasma etch method while employing the patterned photoresist layer as a photoresist etch mask layer the low dielectric constant dielectric layer to form a patterned low dielectric constant dielectric layer having a via formed therethrough. The fluorine containing plasma etch method employing a fluorine containing etchant gas composition which simultaneously forms a fluorocarbon polymer residue layer upon a sidewall of the via.

Abstract: A forced plug process for high aspect ratio structures. The process comprises the steps of providing a liquid plug in a high aspect ratio structure; increasing a gas pressure to force the liquid plug down into the high aspect ratio structure; and suddenly decreasing the gas pressure allowing the liquid plug to be ejected from the high aspect ratio structure. The process is useful for removing unwanted particles from a high aspect ratio structure, as well as for etching and coating the side walls of the structure.

Abstract: A method for making a stacked gate electrode structure for a semiconductor device provides for three layers of the stacked structure including a first conductive layer, an insulating layer, and a second conductive layer. The layers of the stacked structure are to be of uniform width. The method includes forming on a gate oxide layer on the surface of the semiconductor substrate a first conductive layer, an insulating layer, and a second conductive layer in order. A photoresist is formed on the second conductive layer and patterning of the second conductive layer and the insulating layer using the photoresist as an etching mask is carried out. Side wall covering layers which result from the insulating layer patterning which cover the sides of both the second conductive layer and the insulating layer are removed. Thereafter, the first conductive layer is patterned using the photoresist as an etching mask.

Abstract: A method for etching access opening to aluminum alloy wire bonding pads of integrated circuit chips is described wherein a polymer layer is in-situ deposited into the opening after the bonding pad has been exposed by dry etching of a passivation layer. The passivation layer, is first etched with fluorocarbon etchants and then a TiN ARC layer is removed from over the aluminum bonding pad with etchants which may contain chlorine either as etch components or as a contaminant in an etchant such as SF.sub.6 non-volatile chlorine containing residues including AlCl.sub.3 and trapped Cl.sub.2, are left behind after the ARC layer has been removed. These cause corrosion of the bonding pad when exposed to atmospheric moisture. The polymer layer deposited immediately after the pad surface is exposed by the etchant, provides a temporary seal over the aluminum bonding pad, protecting it from exposure to moisture during subsequent processing steps.

Abstract: Method of improving the resistance of a metal against degradation from exposure to fluorine released from a fluorine-containing material by forming a fluorine-barrier layer between the insulator material and the metal. The invention is especially useful in improving corrosion and poisoning resistance of metallurgy, such as aluminum metallurgy, in semiconductor structures. The invention also covers integrated circuit structures made by this method.

Abstract: A method of plasma etching photoresist and sidewall polymer with an etch gas mixture comprising a fluorine containing gas (CF.sub.4 or NF.sub.3) and H.sub.2 O demonstrating very aggressive ashrate of photoresist but maintains an exceptionally low etch rate for titanium nitride and other metals is provided. The very low TiN etch rate permits the inventive method to effectively breakdown sidewall polymer without removing any significant amount of these metals. The invention is particularly suited for stripping sidewall polymer from etched via holes and from etched metal lines. Vias fabricated with this technique exhibit exceptionally low resistance.

Abstract: A method for forming a patterned polysilicon layer employed within an integrated circuit structure. There is first provided a semiconductor substrate having formed thereupon a topographic substrate layer. There is then formed over the semiconductor substrate including the topographic substrate layer a polysilicon layer. There is then formed over the polysilicon layer an etch mask layer. There is then etched the polysilicon layer within a first reactive ion etch (RIE) plasma employing a first etchant gas composition which comprises a chlorine containing etchant species to form a patterned polysilicon layer and a patterned polysilicon containing layer residue. Finally, there is then over-etched the patterned polysilicon layer and the patterned polysilicon containing layer residue within a second reactive ion etch (RIE) plasma employing a second etchant gas composition which comprises an oxygen containing etchant species and a bromine containing etchant species.

Abstract: A method for preparing a semiconductor substrate and a polysilicon gate for subsequent silicide formation. In one embodiment, the present invention performs an oxide etch to remove oxide from source and drain diffusion regions of the semiconductor substrate and from the top surface of the polysilicon gate. Next, the present invention subjects the semiconductor substrate and the polysilicon gate to an ashing environment. In the present invention, the ashing environment is comprised of H.sub.2 O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas. In so doing, contaminants introduced into the source and drain diffusion regions of the semiconductor substrate and into the top surface of the polysilicon gate during the oxide etch are removed. Next, the present invention performs a semiconductor wafer surface clean step. The semiconductor wafer surface clean step provides a semiconductor wafer surface which is substantially similar to a virgin silicon surface.

Abstract: A method for fabrication of a lightly-doped-drain (LDD) structure for self aligned polysilicon gate MOSFETs is described wherein a polymer layer, formed along the sidewall during the patterning process of the polysilicon gate electrode, is used to mask the source/drain ion implant. The sidewall polymer layer replaces the conventional silicon oxide sidewall as an LDD spacer and offers improved thickness control as well as an improved sequence of processing steps whereby the deposition of a spacer oxide layer onto the gate oxide is eliminated. A cap oxide layer first deposited over the gate polysilicon layer. This oxide layer is then patterned and etched using RIE under conditions which form a polymer sidewall layer along the edges of the cap oxide pattern. The polysilicon layer is then etched, and has a pattern concentric with the cap oxide pattern but wider by the thickness of the polymer sidewall.

Abstract: A refractory metal layer on a silicon oxide layer is exposed to gaseous etchant containing SF.sub.6, Cl.sub.2 and CO so as to be patterned; F radical and Cl radical effectively etch the refractory metal, and a reaction product of CO gas does not allow the dry etching to sidewardly proceed so that the dry etching achieves good anisotropy, a large etching rate and a large selectivity to silicon oxide.

Abstract: This is a method for improving contact openings during the manufacture of an integrated circuit. The process of forming a contact in an integrated circuit is often carried out rapidly, with imperfect control. As a result, incomplete removal of the insulating material may occur within the contact opening. In addition, the substrate material may be damaged to some extent within the contact opening by the contact formation process. In either case, high electrical resistance within the contact may result. Photo-resist may leave residue within the contact opening, low surface dopant concentrations, and insulative layer discontinuities may cause increased electrical resistance within the contact. A sequential application of two types of aqueous etchants will smooth the contact sidewall and remove a thin layer of relatively low dopant concentration at the surface of the substrate and other debris which may remain from the contact formation process and thereby allow lower resistance contacts to be formed.

Abstract: An etching method includes providing a first surface and a second surface with the second surface lying substantially vertical to the first surface. A material is provided over at least a portion of the first and second surface. The material is anisotropically etched from at least the first surface resulting in a blocking material formed over at least a portion of the material on the second surface. The blocking material is removed and the portion of the material formed over the second surface is isotropically etched. The blocking material may be a polymer material, and the removing step may include oxidizing the polymer material.

Abstract: A method of producing a high quality silicon surface prior to carrying out a selective epitaxial growth of silicon process for forming an active device region on a substrate. The process flow of the present invention eliminates the need for the sacrificial oxidation layer typically used in such processes. After the etching of a seed hole through the isolation oxide layer using a reactive ion etch a short, low power C.sub.2 F.sub.6 etch is performed. The present invention provides a simple and cost-effective way to eliminate reactive ion etch damage prior to SEG growth because the dry C.sub.2 F.sub.6 etch can be done in the same etch reactor in which the seed hole oxide etch is performed. In addition, the re-oxidation (sacrificial oxide) step is eliminated, reducing the number of process steps.

Abstract: An improved method for selecting etch endpoint when dry etching conductive material layers for use in semiconductor device circuits has been created. The more precise endpoint selection procedure produces metallization patterns which are free from residues (resulting from under-etching) and free from sidewall attack and/or pattern degradation (resulting from over-etching). The method avoids costly and time consuming pre-sorting of substrates according to product pattern density.

Abstract: A method is provided for the removal of the surface layer of the residual photoresist mask pattern used for metal subtractive etching which uses the same reactor equipment but employs reactive fluorine-containing gases to form volatile compounds with the surface layer, so that subsequently a conventional oxygen plasma stripping process can be used for complete resist residue removal without requiring excessive temperature exposure of the integrated circuit devices.

Abstract: Pitting in active regions along the edges of a gate electrode when etching a composite comprising an anti-reflective coating on polysilicon is avoided by etching the anti-reflective coating with an etchant that forms a protective passivating coating on at least the sidewalls of the etched anti-reflective pattern and on the underlying polysilicon layer. Subsequently, anisotropic etching is conducted to remove the protective passivating coating from the surface of the polysilicon layer, leaving the etched anti-reflective pattern protected from the main polysilicon etch on at least its sidewalls by the passivating coating to prevent interaction. In another embodiment, the anti-reflective coating is etched without formation of a passivating coating, and the polysilicon layer subsequently etched with an etchant that forms a passivating coating.

Abstract: There is provided a method of fabricating a semiconductor device, including the steps of (a) forming impurity-diffused layers at a surface of a silicon semiconductor substrate in selected regions, (b) forming a refractory metal film over the impurity-diffused layers, (c) carrying out first thermal annealing in nitrogen atmosphere to convert the refractory metal film into a refractory metal silicide layer, (d) causing damage to a denaturated layer having been formed over the refractory metal film due to the first thermal annealing, (e) etching both the denaturated layer and non-reacted portions of the refractory metal film with a solution containing ammonia and hydrogen peroxide therein, and (f) carrying out second thermal annealing in nitrogen atmosphere to reduce resistance of the refractory metal silicide layer. For instance, the damage is caused to the denaturated layer by arsenic (As) ion implantation. The damage may be caused to the denaturated layer by exposing to oxygen plasma.

Abstract: A method for processing a layer of a silicon-based material on a wafer by which a sidewall protective film may be removed sufficiently and efficiently. An etching gas capable of yielding chlorine- or bromine-based chemical species and oxygen-based chemical species is used for dry etching a polycide film formed on a gate insulating film, plasma processing with an oxygen-based gas is then carried out for ashing the resist mask and removing carbonaceous components in the sidewall protective film. In addition, the sidewall protective film is oxidized so that the composition to that of stoichiometrically stable SiO.sub.2 is approached. Subsequently, the modified sidewall protective film is removed by processing with a dilute hydrofluoric acid solution. Since this sufficiently removes the sidewall protective film, it becomes possible to reduce the amount of dust and to improve coverage of a film to be formed by the next step.

Abstract: Stripping and cleaning agent for removing dry-etching photoresist residues, and a method for forming an aluminum based line pattern using the stripping and cleaning agent. The stripping and cleaning agent contains (a) from 5 to 50% by weight of an organocarboxlic ammonium salt or an amine carboxylate, represented by the formula [R.sup.1 ]m[COONH.sub.p (R.sup.2)q]n, where R.sup.1 is hydrogen, or an alkyl or aryl group having from 1 to 18 carbon atoms; R.sup.2 is hydrogen, or an alkyl group having from 1 to 4 carbon atoms; m and n independently are integers of from 1 to 4, p is integer of from 1 to 4, q is integer of from 1 to 3, and p+q=4 and (b) from 0.5 to 15% by weight of a fluorine compound. The inventive method is advantageously applied to treating a dry-etched semiconductor substrate with the stripping and cleaning agent. The semiconductor substrate comprises a semiconductor wafer having thereon a conductive layer containing aluminum.