Abstract: A time synchronization method and apparatus includes determining a time difference between reference time and system time of an artificial intelligence device, where the reference time is timed by an internal clock of the artificial intelligence device and is aligned based on a satellite timing signal, or the reference time is timed by an internal clock of the artificial intelligence device; and adjusting the system time based on a preset step value if the time difference is greater than a preset value.

Abstract: An electronic marking for verifying the authenticity of an object, including an antenna, an analogue transceiver circuit, a microcontroller, and at least one secure cryptoprocessor, in which the antenna is connected to the analogue transceiver circuit; the microcontroller is connected both to the analogue transceiver circuit and the at least one secure cryptoprocessor; the at least one secure cryptoprocessor is designed to securely generate a digital signature; the electronic marking has one or more electrical sensor conductors; the at least one secure cryptoprocessor is connected to at least one of the sensor conductors and designed to determine at least one electrical property of the connected at least one sensor conductor; and the one or more electrical sensor conductor(s) are distinct from the antenna and are positioned to overlap, at least partly, with said antenna.

Abstract: Methods, systems, and devices for wireless communications are described in which UEs may communicate with satellites and base stations or gateways in a non-terrestrial network (NTN). Due to the large distances between transmitting devices and receiving devices in a NTN, timing adjustments to account for propagation delay communications links via a satellite may include a propagation delay between a UE and a satellite, a propagation delay between a base station and a satellite, as well as a variation in the propagation delays due to movement of the satellite. In accordance with various techniques discussed herein, a UE may account for variation in propagation delay, in addition to determined propagation delay, when determining an uplink timing for uplink communications via a satellite.

Abstract: An apparatus for in-phase and quadrature phase (“IQ”) generation comprises a CMOS clock distributor for providing a clock input. A first IQ divider circuit is configured for receiving the clock input and dividing the clock input into in-phase and quadrature phase (IQ) output. A clock processing circuit is configured for processing the clock input. A second IQ divider circuit is configured for receiving the processed clock input and dividing the processed clock input into in-phase and quadrature phase (IQ) output. A multiplexer circuit is coupled to the first IQ divider circuit and the second IQ divider circuit for selecting the IQ output from the first IQ divider circuit or the second IQ divider circuit.

Abstract: In a wireless power transmitting device, a control circuit outputs a control signal for setting a frequency and a phase of an F-PLL signal generated by an F-PLL, the F-PLL generates the F-PLL signal having the frequency and the phase set by the control signal output from the control circuit, and a frequency conversion circuit generates a transmission signal by converting a frequency of the F-PLL signal generated by the F-PLL.

Abstract: The present disclosure relates to a data driving device and a method of driving the data driving device and, more particularly, to a data driving device and a method of driving the same in which a tuning of a set value of an internal circuit is automatically performed.

Abstract: The present invention provides a fractional-N frequency synthesizer comprising a divider controller comprising a multistage noise Shaping (MASH) digital delta-sigma modulator comprising L error feedback modulator (EFM) stages, wherein the jth EFM stage is configured to receive as an input the sum of the error of the preceding EFM stage and a high amplitude dither signal derived from the error of the kth EFM stage, where 1?j?k?L.

Abstract: Systems, methods, and circuitries are provided for generating a frequency hopping radar signal. In one example, a radar signal modulator include a frequency offset generator, a phase locked loop, and a bandwidth compensation circuitry. The frequency offset generator is configured to generate a sequence of frequency offsets. The bandwidth compensation circuitry is configured to combine a modulation signal and the sequence of frequency offsets to generate a bandwidth compensated signal. The PLL is configured to receive the bandwidth compensated signal and generate a frequency hopping radar signal based on the bandwidth compensated signal.

Abstract: A transmitter circuit includes a phase locked loop circuit, having one or more operational characteristics indicative of an operating state of the phase locked loop circuit. The phase locked loop circuit is configured to generate a frequency signal. The transmitter circuit also includes a power amplifier configured to selectively drive an antenna with a drive signal according to the frequency signal, and a programmable delay circuit configured to controllably extend a propagation delay between the frequency signal and the drive signal of the power amplifier. The programmable delay circuit is programmed such that a first value of a particular operational characteristic of the phase locked loop circuit is substantially equal to a second value of the operational characteristic of the phase locked loop circuit. The first value is measured with the power amplifier not driving the antenna. The second value is measured with the power amplifier driving the antenna.

Abstract: A clock adjusting device includes an oscillator, a first counter, a second counter, a count comparator and a threshold comparator. The oscillator transmits an operation clock signal. The first counter counts a reference clock signal, to obtain a reference clock count value. The second counter counts the operation clock signal to obtain an operation clock count value. The count comparator compares the reference clock count value with the operation clock count value, to obtain a candidate correction value. The oscillator adjusts the operation clock signal according to an output correction value. The threshold comparator compares the candidate correction value and an updated threshold. When the candidate correction value is lower than the updated threshold, the candidate correction value is used as the output correction value, and when the candidate correction value exceeds the updated threshold, a current correction value is used as the output connection value.

Abstract: An integrated circuit includes phase locked loop (PLL) circuitry, voltage controlled oscillator (VCO) circuitry, and interface circuitry. The PLL circuitry includes a reference signal input terminal, a reference frequency divider circuit, a reference signal output terminal, a switch, a phase detector, a charge pump, and a control voltage output terminal. The reference frequency divider circuit is coupled to the reference signal input terminal. The switch is coupled to the reference frequency divider circuit and to the reference signal output terminal. The switch is configured to switchably connect the reference frequency divider circuit to the reference signal output terminal. The VCO circuitry includes a control voltage input terminal, a VCO, calibration circuitry, and a calibration input/output (I/O) terminal. The VCO is coupled to the control voltage input terminal. The calibration circuitry is coupled to the VCO. The calibration I/O terminal is coupled to the calibration circuitry.

Abstract: A system and method of performing temperature compensation based on temperature of a crystal. An integrated circuit includes a clock circuit, a memory, an interface developing a sense voltage indicative of a temperature of the crystal, and a controller. The memory stores compensation values including nominal values based on a nominal third order polynomial that defines a nominal frequency versus temperature relationship of a crystal design representing multiple crystals, and a pair of adjustment values derived from two temperature-frequency error points. The controller determines a temperature value based on the sense voltage, calculates a frequency offset using the temperature value and the compensation values to solve a compensated third order polynomial defining a compensated frequency versus temperature relationship of the crystal, and adjusts a clock signal of the clock circuit using the frequency offset. A Wi-Fi device may be optimized for industrial IoT operating within an extended temperature range.

Abstract: A receiver system that includes a clock and data recovery (CDR) system for aligning a local clock signal to an incoming data signal to extract correct timing information from the incoming data signal is provided. A timing error detector generates an output phase error signal representing the phase difference between the incoming data signal and the local clock signal. The timing error detector determines the phase difference according to recovered symbols and the difference between the recovered symbols and digital samples of the incoming data signal. The digital samples of the incoming data signal include intersymbol interference. The output timing information is suitable for aligning the local clock signal to the incoming data signal.

Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may support dynamic clock switching within a transmission time interval (TTI) to allow for more efficient and flexible processing within the TTI. In particular, a user equipment (UE) may be configured to use multiple clock speeds for processing signals within a TTI, and the UE may determine a clock speed to use for processing data within a TTI based on control information received from a base station. For example, the UE may determine an amount of time available for processing data based on the control information received from the base station, and the UE may adjust its clock speed to finish processing the data in the determined amount of time.

Abstract: A mounting system having a dual plunger arrangement wherein the side of each plunger has a pull down cam to provide a desired pull down action in relation to at least two studs, the cams moving relative to one another and axially aligning relative to one another relative to the two axially spaced pull down studs to allow the plungers to provide a maximum hold down force for the two pull down studs, balance the hold down forces thereby maximizing performance and reducing unlocking forces.

Abstract: A hybrid PLL is provided that includes an digital integral path and an analog proportional path.

Abstract: Techniques for interleaving information for media data are described. In at least some embodiments, interleaving information is propagated from a network-based service to endpoint devices that participate in communication sessions. The endpoint devices may utilize the interleaving information to interleave media data of communication sessions.

Abstract: A loop filter with an active discrete-level loop filter capacitor can be used in a VCO (such as for CDR). A loop filter capacitor function is simulated by sensing input loop filter current (such as with a current mirror and source follower in the input leg), and forcing back a loop filter (VCO) control voltage. Loop filter voltage control is provided using a VDAC with a discrete-level VDAC feedback voltage, incremented/decremented based on the sensed loop filter current. In one embodiment, the VDAC voltage is provided as the non-inverting input to an amplifier, with the inverting input providing the control voltage, forced to the VDAC feedback voltage. The VDAC feedback voltage can be provided by increment/decrement comparators based on a voltage deviation on a C2 capacitor (from a reference voltage) that receives the sensed loop filter current (effectively multiplying the C2 capacitance to provide a simulated loop filter capacitance).

Abstract: A low-power RF receiver has a decreased current consumption. The receiver may be used in control devices, such as battery-powered motorized window treatments and two-wire dimmer switches. The receiver uses an RF sub-sampling technique to check for RF signals and then puts the receiver to sleep for a sleep time that is longer than a packet length of a transmitted packet to conserve battery power. The receiver compares detected RF energy to a threshold that may be increased to decrease the sensitivity of the receiver and increase the battery lifetime. After detecting an RF signal, the receiver is put to sleep for a snooze time that is longer than the sleep time and just slightly shorter than the time between two consecutive transmitted packets.

Abstract: A frequency-generating circuit includes a frequency synthesizer circuit and a controller. The frequency synthesizer circuit generates a radio-frequency clock signal according to a reference clock signal and a channel number. The controller is coupled to the frequency synthesizer circuit, generates a power-down control signal for controlling at least a portion of the frequency synthesizer circuit to power down. The frequency synthesizer circuit includes an accumulator for generating an accumulated value according to the channel number. The frequency synthesizer circuit generates the radio-frequency clock signal according to the reference clock signal and the accumulated value. The controller maintains the accumulated value of the accumulator when the portion of the frequency synthesizer circuit powers down.

Abstract: The invention provides an audio noise reduction circuit, an intelligent terminal and a teaching method using this audio noise reduction circuit, where a dual microphone array is used for abatement of noise, ICA algorithm is used for blind source analysis; the audio noise reduction circuit is used to realize the extraction and separation of voice and improve the voice quality in noisy environment, so that the user can also obtain clear voice communication or recording effect even in noise environment; through real-time acquisition and recording of the audio information of teacher, the invention realizes the real-time recording of teaching voice data and solves the following problem: when the learning content is preset in the intelligent terminal, the learning experience is relatively monotonous, leading to unsatisfactory results of learning.

Abstract: Methods and systems for calibrating a transceiver using frequency separation are disclosed. A method configured to calibrate a transceiver that includes connecting an output of a transmitter to an input of a receiver. A receiver local oscillator signal having a receiver local oscillator frequency (fRXLO) is provided to a receiver mixer. A transmitter local oscillator signal having a transmitter local oscillator frequency (fTXLO) to is provided to a transmitter mixer. The receiver local oscillator frequency is separated from the transmitter local oscillator frequency by a nonzero intermediate frequency (fIF). The method includes upconverting a test signal having a baseband frequency (fBB) using the transmitter mixer and downconverting the output signal of the transmitter mixer with the receiver mixer to generate a calibration signal. The transceiver is calibrated based on the calibration signal.

Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.

Abstract: Examples herein are directed to communicating on a communication bus in accordance with a message-based signal protocol. One or more messages are generated with a data field, in which a portion of the data field is reserved for a signature. The signature has a bit length corresponding to a bit length of the reserved portion of the data field. The signature is coded in the portion of the data field reserved for the signature, and at least one message is transmitted with the signature coded therein. Each message received on the communication bus and having a signature coded in a data field therein is authenticated based on the signature, and processed by removing the signature from the data field and decoding the message with the signature removed.

Abstract: A cable network gateway receives a downstream broadband signal via service provider cabling at an interface. An Analog to Digital Converter (ADC) converts the downstream broadband signal to a digital downstream broadband signal. A digital filter attenuates an upper spectrum from the digital downstream broadband signal to produce a filtered digitized downstream broadband signal. An in-home communications transceiver produces a digital in-home communications signal that overlaps the upper spectrum. Summing circuitry sums the filtered digitized downstream broadband signal with the digital in-home communications signal to produce a combined digital signal. A Digital to Analog Converter (DAC) converts the combined digital signal to a combined analog signal and an in-home cable interface transmits the combined analog signal via in-home cabling. The downstream broadband signal may be a Data over Cable System Interface Specification (DOCSIS) 3.0/3.

Abstract: The present invention provides an electronic device including a coupler, a noise-estimation apparatus and an assembly unit. The coupler receives a baseband signal. The noise-estimation apparatus receives the baseband signal and subtracts a predetermined synchronization preamble from the baseband signal to obtain a noise-estimation signal, and the predetermined synchronization preamble is a transmission signal that conforms to the standards of 802.11bg and/or IEEE 802.11n. The assembly unit receives the baseband signal and subtracts a noise-estimation signal from the baseband signal to obtain an output signal.

Abstract: Apparatus and methods relating to synchronization of communication equipment are disclosed. Synchronization information received from a bonded communication link can be used to synchronize local and/or remote communication equipment, such as femtocell sites coupled to nodes in a ring network. This may involve isolating a frequency reference signal from a DSL (Digital Subscriber Line) communication link which is a constituent link of a bonded communication link, for example. In a ring network, received synchronization information could be used in synchronizing a locally connected installation of communication equipment, and passed for transmission in the ring network for synchronizing other communication equipment. Such dropping and passing of an analog frequency reference signal could be applied in networks having other topologies as well. At least some embodiments of the invention are applicable to optical links.

Abstract: A frequency-agile frequency source. The frequency source includes an oscillator having an output and being configured to generate a signal at a first frequency at the output, a first direct digital synthesizer (DDS) having an output and a sampling clock input connected to the output of the oscillator, a filter amplifier block having an input directly connected to the output of the first DDS and an output, and a second DDS having a sampling clock input directly connected to the output of the filter amplifier block. The filter amplifier block is a substantially linear time-invariant element having a frequency response, the magnitude of the frequency response being at least 12 dB lower, at a second frequency within the first Nyquist zone of the first frequency, than at a third frequency above the first Nyquist zone of the first frequency.

Abstract: A phase locked loop (PLL) circuit includes a frequency multiplier and a fractional-N type PLL. The clock output of the frequency multiplier is electrically connected to the clock input of the fractional-N type PLL. The loop bandwidth of the frequency multiplier of the PLL is smaller than the loop bandwidth of the fractional-N type PLL of the PLL.

Abstract: Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.

Abstract: In the stop state of a VCO and an injection locked frequency divider, an ILFD controller sets the control parameter of an injection locked frequency divider on the basis of the frequencies of a reference signal and the frequency-divided signal measured according to the control parameter of the injection locked frequency divider. While the injection locked frequency divider is operated and in the stop state of the VCO, the ILFD controller sets the control parameter of the injection locked frequency divider on the basis of the frequencies of the reference signal and the frequency-divided signal measured according to the control parameter of the injection locked frequency divider.

Abstract: In order to provide a circuit arrangement (100) and also a method for clock and/or data recovery (CDR) having low power consumption, having low power loss and also having scalability of the power loss from the clock and/or data recovery at the data rate, at least one frequency regulation circuit and at least one phase regulation circuit are proposed, wherein firstly only the frequency regulation circuit is active for the purpose of setting the frequency on the basis of the data rate that can be applied to the data input and then changeover to the phase regulation circuit occurs for the purpose of ascertaining the phase difference between the data input and the clock input.

Abstract: A frequency synthesizer device provides amplitude control. Using switch circuit operating in a first mode, a charge voltage is applied to an oscillator circuit that an inductive-capacitive (LC) tank circuit. The LC tank circuit has a capacitive element, and an inductive element that is connected to the capacitive element. Using the switch circuit operating in a second mode, the LC tank circuit is enabled to oscillate. Using driver circuits that are response to a voltage applied to the tank circuit, current is reinforced in the LC tank, and the reinforcement is based upon a transconductance gain of the driver circuits. Using a calibration circuit, an amplitude of an output signal from the oscillator circuit is detected. In response to the detected amplitude, the transconductance gain is adjusted by enabling or disabling auxiliary circuits from plurality of auxiliary circuits.

Abstract: A circuit for implementing a dual-mode oscillator is disclosed. The circuit comprises a first oscillator portion having a first inductor coupled in parallel with a first capacitor between a first node and a second node; a first pair of output nodes coupled to the first and second nodes; a second oscillator portion inductively coupled to the first oscillator portion, the second oscillator portion having a second inductor coupled in parallel with a second capacitor between a third node and a fourth node; a second pair of output nodes coupled to the third and fourth nodes; and a control circuit coupled to enable a supply of current to either the first oscillator portion or the second oscillator portion. A method of implementing a dual-mode oscillator is also disclosed.

Abstract: The present invention discloses a base station and a handover processing method for digital trunking communication. The handover processing method comprises: a base station transmitting a System Parameter and Neighbor Channel Assignment Message (SNCAM) to a terminal at a normal period; the base station receiving a handover request from the terminal; the base station transmitting the SNCAM to the terminal at a preset period; the preset period is set to be shorter than the normal period and ensures that the power consumption of the base station is lower than a threshold which leads to power overload. The present invention has increased the possibility that the terminal receives the SNCAM, and can also avoid the power overload of the system, thus not only the user experience is improved, but also the life of the base station is prolonged.

Abstract: A clock signal generation circuit provides an output clock signal to a digital system. The digital system is powered by a power supply voltage, VDD, that may include transients associated with the impedance of the packaged digital system. The clock signal generation circuit dynamically scales an output clock frequency based on monitored changed to VDD. The output clock frequency may be selected to approximate a maximum (margin-less) system Fmax for the monitored VDD. The average clock frequency may be improved compared with operating at a fixed output clock frequency.

Abstract: To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.

Abstract: An oscillator circuit may include a local oscillator to generate a carrier signal having a tunable frequency, a first modulator and a power amplifier coupled in cascade to the local oscillator to generate an output signal. The first modulator may be activated from a first modulating signal having a first frequency alternatively defining ON and OFF states of the first modulator. An estimator unit may receive the carrier signal during a time window and detect an estimated frequency variation of the carrier signal during the ON and OFF states. A compensation unit may include a second modulator to generate a compensation signal proportional to the estimated frequency variation and modulated with a second modulating frequency. The second modulating frequency may be substantially the same as the first modulating frequency, and the compensation signal may be added to a bias signal of the local oscillator to tune the tunable frequency.

Abstract: An ILFD control unit sets a control parameter of an injection locked frequency divider based on each frequency of a reference signal and a frequency-divided signal measured in response to the control parameter of the injection locked frequency divider, in a stop state of a VCO and an injection locked frequency divider. The ILFD control unit runs the injection locked frequency divider and sets a control parameter of the injection locked frequency divider based on each frequency of the reference signal and the frequency-divided signal measured in response to the control parameter of the injection locked frequency divider, in the stop state of the VCO.

Abstract: A circuit, electrical device or other apparatus for band stacking and/or band translating multiple transmissions. Such transmissions may be satellite transmissions, terrestrial transmissions, signals carried across a wired network such as a cable network, and so forth. Two sets of left-hand polarized and right-hand polarized signals may be accepted by an embodiment. One left-hand polarized signal and one right-hand polarized signal may be band stacked such that the left-hand polarized signal occupies a first frequency and the right-hand polarized signal occupies a second frequency, thereby permitting the two signals to be transmitted simultaneously across a single transmission line as a first unique signal. The second left-hand polarized signal and second right-hand polarized signal may likewise be combined into a second unique signal for transmission. The first and second unique signals may be stacked as a first stacked output and a second stacked output by a band translating circuit.

Abstract: A radio receiver supporting cancellation of thermal and phase noise in a down-converted RF signal. An inbound RF signal and blocking signal are provided directly to a passive mixer for down-conversion into a first baseband signal having data, thermal noise, and reciprocal mixing (RM) noise components. The inbound signals are also provided to a transconductance circuit, the output of which is provided to a second passive mixer for conversion into a current signal having data and blocking signal components, and a RM image. The blocking signal component and the RM image are mixed with a second LO signal, derived from the blocking signal, to produce a RM noise cancellation signal. The data component of the current signal is converted into a second baseband signal having data and thermal noise components. The first baseband signal, second baseband signal and RM noise cancellation signal are then combined through harmonic recombination.

Abstract: Provided are a semiconductor device including an oscillator and a manufacturing method thereof, in which cost is low and design flexibility is high. The semiconductor device includes a wiring structure region and an oscillator region. The semiconductor device also includes, in the oscillator region, a metal resistive element as the same layer as a conducting film over uppermost metal wiring in the wiring structure region.

Abstract: It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no supplied signal in a circuit which performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The present invention provides a configuration including a PLL circuit and an oscillator circuit, where a switch for switching an output between a signal from the PLL circuit and a signal from the oscillator circuit to the signal output portion is provided to switch from a connection to the PLL circuit to a connection to the oscillator circuit in a case where there is no received signal.

Abstract: Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.

Abstract: A calibration system may be provided for calibrating wireless communications circuitry in an electronic device during manufacturing. The calibration system may include data acquisition equipment and calibration computing equipment for receiving and processing test and calibration signals from wireless communications circuitry to be calibrated. During testing and calibration operations, a device may be provided with initial pre-distortion calibration values. The initial pre-distortion calibration values may be generated at least in part based on calibration operations performed for other wireless electronic devices. The device may generate a test signal using the initial pre-distortion calibration values. The calibration system may determine whether the test signal is within an acceptable range of a known reference signal.

Abstract: A transmit (TX) signal path circuit in a multiple-input, multiple-output (MIMO) transceiver responsive to a digital front end (DFE) for generating receive (RX) path phase alignment signals is disclosed. A digital up-conversion block uses a first numerically-controlled oscillator (NCO) for generating digital intermediate frequency (IF) signals for ordinary TX signal generation, and a different, second NCO for generating digital IF signals for RX phase alignment signal generation. An RF up-conversion block uses a TX local oscillator (LO) for generating analog RF signals for ordinary TX signal generation, and a different feedback (FB) LO for generating analog RF signals for RX phase alignment signal generation. Thus, phase alignment of the circuitry used for ordinary TX signal generation is left undisturbed by RX phase alignment signal generation.

Abstract: An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.

Abstract: A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to output a data recovery stream and a data recovery clock based on an input signal and a clock signal. The frequency comparison circuit is coupled to the clock recovery circuit. The frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and the clock signal to adjust the frequency of the clock signal based on a comparison result. The signal detecting circuit is coupled to the frequency comparison circuit. The signal detecting circuit is configured to receive and detect the input signal, and the signal detecting circuit determines whether to enable the frequency comparison circuit according to the detection result. Furthermore, a method for generating a data recovery clock is also provided.

Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

Abstract: Receiver synchronization techniques (RST), contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of the receiver clock, and phase and frequency recovery techniques, comprising a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing signals or time referencing messages wherein SCCS includes a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality.